2 PARTNUM=xc3s1500-5fg456
4 all: project command xst ngd ncd ncd2 bit
7 xst -ifn ${FILENAME}.cmd -ofn xst.log
10 ngdbuild -nt timestamp -p ${PARTNUM} ${FILENAME}
13 rm -rf ${FILENAME}.ncd
14 map -detail -cm speed -k 8 -retiming on -equivalent_register_removal on -timing -ol high -pr b -p ${PARTNUM} ${FILENAME}.ngd -o ${FILENAME}.ncd ${FILENAME}.pcf
16 # Place and route ncd file into new ncd file
18 par -ol high -xe n -w ${FILENAME}.ncd ${FILENAME} ${FILENAME}.pcf
21 bitgen -w ${FILENAME}.ncd -b ${FILENAME}.bit
24 @rm -rf ${FILENAME}.ngc *.lst *.bit *.lso *.xst *.stx *.syr \
25 *.ngr *.cmd_log _ngc _xmsgs xst *.html *.srp \
26 *.blc *.bld *.ise_ISE_Backup *~ \
27 *.pad *.ngm *.ngd *.par *.pcf *.unroutes \
28 *.xpi *.bgn *.drc *.bin *.mrp *.csv *.txt \
29 *.rbt *.ncd ${FILENAME} *_cg templates/ tmp/ \
30 output.dat coregen.log *.ngo *.log ${FILENAME}.map \
31 ${FILENAME}_summary.xml ${FILENAME}_usage.xml ${FILENAME}.twr
34 rm -rf ${FILENAME}.cmd
35 @echo "identification" >> ${FILENAME}.cmd
36 @echo "status" >> ${FILENAME}.cmd
37 @echo "time short" >> ${FILENAME}.cmd
38 @echo "memory on" >> ${FILENAME}.cmd
39 @echo "run " >> ${FILENAME}.cmd
40 @echo "-top ${FILENAME}" >> ${FILENAME}.cmd
41 @echo "-ifn ${FILENAME}.prj" >> ${FILENAME}.cmd
42 @echo "-ifmt Verilog " >> ${FILENAME}.cmd
43 @echo "-ofn ${FILENAME} " >> ${FILENAME}.cmd
44 @echo "-p ${PARTNUM}" >> ${FILENAME}.cmd
45 @echo "-bufg 6" >> ${FILENAME}.cmd
46 @echo "-vlgincdir { ../../opencores/i2c/rtl/verilog ../../eth/rtl/verilog/ ../../opencores/spi/rtl/verilog}" >> ${FILENAME}.cmd
50 @echo '`include "../../eth/rtl/verilog/TECH/duram.v" ' >> ${FILENAME}.prj
51 @echo '`include "../../sdr_lib/sign_extend.v" ' >> ${FILENAME}.prj
52 @echo '`include "../../sdr_lib/cordic_stage.v" ' >> ${FILENAME}.prj
53 @echo '`include "../../sdr_lib/cic_int_shifter.v" ' >> ${FILENAME}.prj
54 @echo '`include "../../sdr_lib/cic_dec_shifter.v" ' >> ${FILENAME}.prj
55 @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" ' >> ${FILENAME}.prj
56 @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_regfile.v" ' >> ${FILENAME}.prj
57 @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_fetch.v" ' >> ${FILENAME}.prj
58 @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_decode.v" ' >> ${FILENAME}.prj
59 @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_control.v" ' >> ${FILENAME}.prj
60 @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_aslu.v" ' >> ${FILENAME}.prj
61 @echo '`include "../../eth/rtl/verilog/miim/eth_shiftreg.v" ' >> ${FILENAME}.prj
62 @echo '`include "../../eth/rtl/verilog/miim/eth_outputcontrol.v" ' >> ${FILENAME}.prj
63 @echo '`include "../../eth/rtl/verilog/miim/eth_clockgen.v" ' >> ${FILENAME}.prj
64 @echo '`include "../../eth/rtl/verilog/TECH/eth_clk_switch.v" ' >> ${FILENAME}.prj
65 @echo '`include "../../eth/rtl/verilog/TECH/eth_clk_div2.v" ' >> ${FILENAME}.prj
66 @echo '`include "../../eth/rtl/verilog/Reg_int.v" ' >> ${FILENAME}.prj
67 @echo '`include "../../eth/rtl/verilog/RMON/RMON_dpram.v" ' >> ${FILENAME}.prj
68 @echo '`include "../../eth/rtl/verilog/RMON/RMON_ctrl.v" ' >> ${FILENAME}.prj
69 @echo '`include "../../eth/rtl/verilog/RMON/RMON_addr_gen.v" ' >> ${FILENAME}.prj
70 @echo '`include "../../eth/rtl/verilog/MAC_tx/flow_ctrl.v" ' >> ${FILENAME}.prj
71 @echo '`include "../../eth/rtl/verilog/MAC_tx/Ramdon_gen.v" ' >> ${FILENAME}.prj
72 @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v" ' >> ${FILENAME}.prj
73 @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v" ' >> ${FILENAME}.prj
74 @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v" ' >> ${FILENAME}.prj
75 @echo '`include "../../eth/rtl/verilog/MAC_tx/CRC_gen.v" ' >> ${FILENAME}.prj
76 @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v" ' >> ${FILENAME}.prj
77 @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v" ' >> ${FILENAME}.prj
78 @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v" ' >> ${FILENAME}.prj
79 @echo '`include "../../eth/rtl/verilog/MAC_rx/CRC_chk.v" ' >> ${FILENAME}.prj
80 @echo '`include "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v" ' >> ${FILENAME}.prj
81 @echo '`include "../../control_lib/ram_2port.v" ' >> ${FILENAME}.prj
82 @echo '`include "../../sdr_lib/cordic.v" ' >> ${FILENAME}.prj
83 @echo '`include "../../sdr_lib/cic_interp.v" ' >> ${FILENAME}.prj
84 @echo '`include "../../sdr_lib/cic_decim.v" ' >> ${FILENAME}.prj
85 @echo '`include "../../opencores/spi/rtl/verilog/spi_shift.v" ' >> ${FILENAME}.prj
86 @echo '`include "../../opencores/spi/rtl/verilog/spi_clgen.v" ' >> ${FILENAME}.prj
87 @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" ' >> ${FILENAME}.prj
88 @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_core.v" ' >> ${FILENAME}.prj
89 @echo '`include "../../eth/rtl/verilog/eth_miim.v" ' >> ${FILENAME}.prj
90 @echo '`include "../../eth/rtl/verilog/RMON.v" ' >> ${FILENAME}.prj
91 @echo '`include "../../eth/rtl/verilog/Phy_int.v" ' >> ${FILENAME}.prj
92 @echo '`include "../../eth/rtl/verilog/MAC_tx.v" ' >> ${FILENAME}.prj
93 @echo '`include "../../eth/rtl/verilog/MAC_rx.v" ' >> ${FILENAME}.prj
94 @echo '`include "../../eth/rtl/verilog/Clk_ctrl.v" ' >> ${FILENAME}.prj
95 @echo '`include "../../control_lib/strobe_gen.v" ' >> ${FILENAME}.prj
96 @echo '`include "../../control_lib/ss_rcvr.v" ' >> ${FILENAME}.prj
97 @echo '`include "../../control_lib/shortfifo.v" ' >> ${FILENAME}.prj
98 @echo '`include "../../control_lib/setting_reg.v" ' >> ${FILENAME}.prj
99 @echo '`include "../../control_lib/mux8.v" ' >> ${FILENAME}.prj
100 @echo '`include "../../control_lib/mux4.v" ' >> ${FILENAME}.prj
101 @echo '`include "../../control_lib/longfifo.v" ' >> ${FILENAME}.prj
102 @echo '`include "../../control_lib/decoder_3_8.v" ' >> ${FILENAME}.prj
103 @echo '`include "../../control_lib/buffer_int.v" ' >> ${FILENAME}.prj
104 @echo '`include "../../control_lib/CRC16_D16.v" ' >> ${FILENAME}.prj
105 @echo '`include "../../sdr_lib/tx_control.v" ' >> ${FILENAME}.prj
106 @echo '`include "../../sdr_lib/rx_control.v" ' >> ${FILENAME}.prj
107 @echo '`include "../../sdr_lib/dsp_core_tx.v" ' >> ${FILENAME}.prj
108 @echo '`include "../../sdr_lib/dsp_core_rx.v" ' >> ${FILENAME}.prj
109 @echo '`include "../../opencores/spi/rtl/verilog/spi_top.v" ' >> ${FILENAME}.prj
110 @echo '`include "../../opencores/simple_pic/rtl/simple_pic.v" ' >> ${FILENAME}.prj
111 @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_top.v" ' >> ${FILENAME}.prj
112 @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v" ' >> ${FILENAME}.prj
113 @echo '`include "../../eth/rtl/verilog/MAC_top.v" ' >> ${FILENAME}.prj
114 @echo '`include "../../eth/mac_txfifo_int.v" ' >> ${FILENAME}.prj
115 @echo '`include "../../eth/mac_rxfifo_int.v" ' >> ${FILENAME}.prj
116 @echo '`include "../../control_lib/wb_readback_mux.v" ' >> ${FILENAME}.prj
117 @echo '`include "../../control_lib/wb_1master.v" ' >> ${FILENAME}.prj
118 @echo '`include "../../control_lib/timer.v" ' >> ${FILENAME}.prj
119 @echo '`include "../../control_lib/system_control.v" ' >> ${FILENAME}.prj
120 @echo '`include "../../control_lib/settings_bus.v" ' >> ${FILENAME}.prj
121 @echo '`include "../../control_lib/serdes_tx.v" ' >> ${FILENAME}.prj
122 @echo '`include "../../control_lib/serdes_rx.v" ' >> ${FILENAME}.prj
123 @echo '`include "../../control_lib/ram_wb_harvard.v" ' >> ${FILENAME}.prj
124 @echo '`include "../../control_lib/ram_loader.v" ' >> ${FILENAME}.prj
125 @echo '`include "../../control_lib/nsgpio.v" ' >> ${FILENAME}.prj
126 @echo '`include "../../control_lib/buffer_pool.v" ' >> ${FILENAME}.prj
127 @echo '`include "../u2_basic/u2_basic.v" ' >> ${FILENAME}.prj
128 @echo '`include "u2_fpga_top.v" ' >> ${FILENAME}.prj
129 @echo '`include "../../eth/rtl/verilog/elastic_buffer.v" ' >> ${FILENAME}.prj