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   1 // ////////////////////////////////////////////////////////////////////////////////
   2 // Module Name:    u2_core
   3 // ////////////////////////////////////////////////////////////////////////////////
   4
   5 module u2_core
   6   #(parameter RAM_SIZE=32768)
   7   (// Clocks
   8    input dsp_clk,
   9    input wb_clk,
  10    output clock_ready,
  11    input clk_to_mac,
  12    input pps_in,
  13
  14    // Misc, debug
  15    output [7:0] leds,
  16    output [31:0] debug,
  17    output [1:0] debug_clk,
  18
  19    // Expansion
  20    input exp_pps_in,
  21    output exp_pps_out,
  22
  23    // GMII
  24    //   GMII-CTRL
  25    input GMII_COL,
  26    input GMII_CRS,
  27
  28    //   GMII-TX
  29    output [7:0] GMII_TXD,
  30    output GMII_TX_EN,
  31    output GMII_TX_ER,
  32    output GMII_GTX_CLK,
  33    input GMII_TX_CLK,  // 100mbps clk
  34
  35    //   GMII-RX
  36    input [7:0] GMII_RXD,
  37    input GMII_RX_CLK,
  38    input GMII_RX_DV,
  39    input GMII_RX_ER,
  40
  41    //   GMII-Management
  42    inout MDIO,
  43    output MDC,
  44    input PHY_INTn,   // open drain
  45    output PHY_RESETn,
  46
  47    // SERDES
  48    output ser_enable,
  49    output ser_prbsen,
  50    output ser_loopen,
  51    output ser_rx_en,
  52
  53    output ser_tx_clk,
  54    output [15:0] ser_t,
  55    output ser_tklsb,
  56    output ser_tkmsb,
  57
  58    input ser_rx_clk,
  59    input [15:0] ser_r,
  60    input ser_rklsb,
  61    input ser_rkmsb,
  62
  63    // CPLD interface
  64    output cpld_start,
  65    output cpld_mode,
  66    output cpld_done,
  67    input cpld_din,
  68    input cpld_clk,
  69    input cpld_detached,
  70    output cpld_misc,
  71    input cpld_init_b,
  72    input por,
  73    output config_success,
  74
  75    // ADC
  76    input [13:0] adc_a,
  77    input adc_ovf_a,
  78    output adc_on_a,
  79    output adc_oe_a,
  80
  81    input [13:0] adc_b,
  82    input adc_ovf_b,
  83    output adc_on_b,
  84    output adc_oe_b,
  85
  86    // DAC
  87    output [15:0] dac_a,
  88    output [15:0] dac_b,
  89
  90    // I2C
  91    input scl_pad_i,
  92    output scl_pad_o,
  93    output scl_pad_oen_o,
  94    input sda_pad_i,
  95    output sda_pad_o,
  96    output sda_pad_oen_o,
  97
  98    // Clock Gen Control
  99    output [1:0] clk_en,
 100    output [1:0] clk_sel,
 101    input clk_func,        // FIXME is an input to control the 9510
 102    input clk_status,
 103
 104    // Generic SPI
 105    output sclk,
 106    output mosi,
 107    input miso,
 108    output sen_clk,
 109    output sen_dac,
 110    output sen_tx_db,
 111    output sen_tx_adc,
 112    output sen_tx_dac,
 113    output sen_rx_db,
 114    output sen_rx_adc,
 115    output sen_rx_dac,
 116
 117    // GPIO to DBoards
 118    inout [15:0] io_tx,
 119    inout [15:0] io_rx,
 120
 121    // External RAM
 122    inout [17:0] RAM_D,
 123    output [18:0] RAM_A,
 124    output RAM_CE1n,
 125    output RAM_CENn,
 126    output RAM_CLK,
 127    output RAM_WEn,
 128    output RAM_OEn,
 129    output RAM_LDn,
 130
 131    // Debug stuff
 132    output uart_tx_o,
 133    input uart_rx_i,
 134    output uart_baud_o,
 135    input sim_mode,
 136    input [3:0] clock_divider
 137    );
 138
 139    wire [7:0]   set_addr;
 140    wire [31:0]  set_data;
 141    wire         set_stb;
 142
 143    wire         ram_loader_done;
 144    wire         ram_loader_rst, wb_rst, dsp_rst;
 145
 146    wire [31:0]  status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7;
 147    wire         bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int;
 148
 149    wire [31:0]  debug_gpio_0, debug_gpio_1;
 150    wire [31:0]  atr_lines;
 151
 152    wire [31:0]  debug_rx, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc,
 153                 debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp;
 154
 155    wire [15:0]  ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2;
 156    wire         ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2;
 157    wire         ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2;
 158
 159    wire         serdes_link_up;
 160    wire         epoch;
 161
 162    // ///////////////////////////////////////////////////////////////////////////////////////////////
 163    // Wishbone Single Master INTERCON
 164    localparam   dw = 32;  // Data bus width
 165    localparam   aw = 16;  // Address bus width, for byte addressibility, 16 = 64K byte memory space
 166    localparam   sw = 4;   // Select width -- 32-bit data bus with 8-bit granularity.
 167
 168    wire [dw-1:0] m0_dat_o, m0_dat_i;
 169    wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i,
 170                  s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i,
 171                  s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i, s11_dat_i, s11_dat_o,
 172                  s12_dat_i, s12_dat_o, s13_dat_i, s13_dat_o, s14_dat_i, s14_dat_o;
 173    wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr,s12_adr, s13_adr, s14_adr;
 174    wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel,s12_sel, s13_sel, s14_sel;
 175    wire          m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack,s12_ack, s13_ack, s14_ack;
 176    wire          m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb,s12_stb, s13_stb, s14_stb;
 177    wire          m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc,s12_cyc, s13_cyc, s14_cyc;
 178    wire          m0_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err,s12_err, s13_err, s14_err;
 179    wire          m0_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty, s13_rty, s14_rty;
 180    wire          m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we,s13_we, s14_we;
 181
 182    wb_1master #(.s0_addr_w(1),.s0_addr(1'b0),.s1_addr_w(2),.s1_addr(2'b10),
 183                 .s215_addr_w(6),.s2_addr(6'b1100_00),.s3_addr(6'b1100_01),.s4_addr(6'b1100_10),
 184                 .s5_addr(6'b1100_11),.s6_addr(6'b1101_00),.s7_addr(6'b1101_01),.s8_addr(6'b1101_10),
 185                 .s9_addr(6'b1101_11),.s10_addr(6'b1110_00),.s11_addr(6'b1110_01),.s12_addr(6'b1110_10),
 186                 .s13_addr(6'b1110_11),.s14_addr(6'b1111_00),.s15_addr(6'b1111_01),
 187                 .dw(dw),.aw(aw),.sw(sw)) wb_1master
 188      (.clk_i(wb_clk),.rst_i(wb_rst),
 189       .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
 190       .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
 191       .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o  (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
 192       .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty),
 193       .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o  (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
 194       .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty),
 195       .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o  (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
 196       .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty),
 197       .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o  (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
 198       .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty),
 199       .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o  (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
 200       .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty),
 201       .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o  (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
 202       .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty),
 203       .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o  (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
 204       .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty),
 205       .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o  (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
 206       .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty),
 207       .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o  (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb),
 208       .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(s8_err),.s8_rty_i(s8_rty),
 209       .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o  (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
 210       .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(s9_err),.s9_rty_i(s9_rty),
 211       .s10_dat_o(s10_dat_o),.s10_adr_o(s10_adr),.s10_sel_o(s10_sel),.s10_we_o(s10_we),.s10_cyc_o(s10_cyc),.s10_stb_o(s10_stb),
 212       .s10_dat_i(s10_dat_i),.s10_ack_i(s10_ack),.s10_err_i(s10_err),.s10_rty_i(s10_rty),
 213       .s11_dat_o(s11_dat_o),.s11_adr_o(s11_adr),.s11_sel_o(s11_sel),.s11_we_o(s11_we),.s11_cyc_o(s11_cyc),.s11_stb_o(s11_stb),
 214       .s11_dat_i(s11_dat_i),.s11_ack_i(s11_ack),.s11_err_i(s11_err),.s11_rty_i(s11_rty),
 215       .s12_dat_o(s12_dat_o),.s12_adr_o(s12_adr),.s12_sel_o(s12_sel),.s12_we_o(s12_we),.s12_cyc_o(s12_cyc),.s12_stb_o(s12_stb),
 216       .s12_dat_i(s12_dat_i),.s12_ack_i(s12_ack),.s12_err_i(s12_err),.s12_rty_i(s12_rty),
 217       .s13_dat_o(s13_dat_o),.s13_adr_o(s13_adr),.s13_sel_o(s13_sel),.s13_we_o(s13_we),.s13_cyc_o(s13_cyc),.s13_stb_o(s13_stb),
 218       .s13_dat_i(s13_dat_i),.s13_ack_i(s13_ack),.s13_err_i(s13_err),.s13_rty_i(s13_rty),
 219       .s14_dat_o(s14_dat_o),.s14_adr_o(s14_adr),.s14_sel_o(s14_sel),.s14_we_o(s14_we),.s14_cyc_o(s14_cyc),.s14_stb_o(s14_stb),
 220       .s14_dat_i(s14_dat_i),.s14_ack_i(s14_ack),.s14_err_i(s14_err),.s14_rty_i(s14_rty),
 221       .s15_dat_i(0),.s15_ack_i(0),.s15_err_i(0),.s15_rty_i(0)  );
 222
 223    //////////////////////////////////////////////////////////////////////////////////////////
 224    // Reset Controller
 225    system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por),
 226                            .ram_loader_rst_o(ram_loader_rst),
 227                            .wb_rst_o(wb_rst),
 228                            .ram_loader_done_i(ram_loader_done));
 229
 230    assign        config_success = ram_loader_done;
 231    reg           takeover = 0;
 232
 233    wire          cpld_start_int, cpld_mode_int, cpld_done_int;
 234
 235    always @(posedge wb_clk)
 236      if(ram_loader_done)
 237        takeover = 1;
 238    assign        cpld_misc = ~takeover;
 239
 240    wire          sd_clk, sd_csn, sd_mosi, sd_miso;
 241
 242    assign        sd_miso = cpld_din;
 243    assign        cpld_start = takeover ? sd_clk : cpld_start_int;
 244    assign        cpld_mode = takeover ? sd_csn : cpld_mode_int;
 245    assign        cpld_done = takeover ? sd_mosi : cpld_done_int;
 246
 247    // ///////////////////////////////////////////////////////////////////
 248    // RAM Loader
 249
 250    wire [31:0]   ram_loader_dat, iwb_dat;
 251    wire [15:0]   ram_loader_adr, iwb_adr;
 252    wire [3:0]    ram_loader_sel;
 253    wire          ram_loader_stb, ram_loader_we, ram_loader_ack;
 254    wire          iwb_ack, iwb_stb;
 255    ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE))
 256      ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
 257                  // CPLD Interface
 258                  .cfg_clk_i(cpld_clk),
 259                  .cfg_data_i(cpld_din),
 260                  .start_o(cpld_start_int),
 261                  .mode_o(cpld_mode_int),
 262                  .done_o(cpld_done_int),
 263                  .detached_i(cpld_detached),
 264                  // Wishbone Interface
 265                  .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr),
 266                  .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel),
 267                  .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack),
 268                  .ram_loader_done_o(ram_loader_done));
 269
 270    // Processor
 271    aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1))
 272      aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
 273            // Instruction Wishbone bus to I-RAM
 274            .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr),
 275            .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack),
 276            // Data Wishbone bus to system bus fabric
 277            .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
 278            .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
 279            // Interrupts and exceptions
 280            .sys_int_i(proc_int),.sys_exc_i(bus_error) );
 281
 282    assign        bus_error = m0_err | m0_rty;
 283
 284    // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone
 285    // I-port connects directly to processor and ram loader
 286
 287    wire          flush_icache;
 288    ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
 289      sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
 290
 291              .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat),
 292              .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel),
 293              .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack),
 294              .ram_loader_done_i(ram_loader_done),
 295
 296              .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb),
 297              .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack),
 298
 299              .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
 300              .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel),
 301              .flush_icache(flush_icache));
 302
 303    assign        s0_err = 1'b0;
 304    assign        s0_rty = 1'b0;
 305
 306    setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
 307                                          .in(set_data),.out(),.changed(flush_icache));
 308
 309    // Buffer Pool, slave #1
 310    wire          rd0_read, rd0_sop, rd0_error, rd0_done, rd0_eop;
 311    wire          rd1_read, rd1_sop, rd1_error, rd1_done, rd1_eop;
 312    wire          rd2_read, rd2_sop, rd2_error, rd2_done, rd2_eop;
 313    wire          rd3_read, rd3_sop, rd3_error, rd3_done, rd3_eop;
 314    wire [31:0]   rd0_dat, rd1_dat, rd2_dat, rd3_dat;
 315
 316    wire          wr0_write, wr0_done, wr0_error, wr0_ready, wr0_full;
 317    wire          wr1_write, wr1_done, wr1_error, wr1_ready, wr1_full;
 318    wire          wr2_write, wr2_done, wr2_error, wr2_ready, wr2_full;
 319    wire          wr3_write, wr3_done, wr3_error, wr3_ready, wr3_full;
 320    wire [31:0]   wr0_dat, wr1_dat, wr2_dat, wr3_dat;
 321
 322    buffer_pool buffer_pool
 323      (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
 324       .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),
 325       .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty),
 326
 327       .stream_clk(dsp_clk), .stream_rst(dsp_rst),
 328       .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
 329       .status(status),.sys_int_o(buffer_int),
 330
 331       .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3),
 332       .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7),
 333
 334       // Write Interfaces
 335       .wr0_dat_i(wr0_dat), .wr0_write_i(wr0_write), .wr0_done_i(wr0_done),
 336       .wr0_error_i(wr0_error), .wr0_ready_o(wr0_ready), .wr0_full_o(wr0_full),
 337       .wr1_dat_i(wr1_dat), .wr1_write_i(wr1_write), .wr1_done_i(wr1_done),
 338       .wr1_error_i(wr1_error), .wr1_ready_o(wr1_ready), .wr1_full_o(wr1_full),
 339       .wr2_dat_i(wr2_dat), .wr2_write_i(wr2_write), .wr2_done_i(wr2_done),
 340       .wr2_error_i(wr2_error), .wr2_ready_o(wr2_ready), .wr2_full_o(wr2_full),
 341       .wr3_dat_i(wr3_dat), .wr3_write_i(wr3_write), .wr3_done_i(wr3_done),
 342       .wr3_error_i(wr3_error), .wr3_ready_o(wr3_ready), .wr3_full_o(wr3_full),
 343       // Read Interfaces
 344       .rd0_dat_o(rd0_dat), .rd0_read_i(rd0_read), .rd0_done_i(rd0_done),
 345       .rd0_error_i(rd0_error), .rd0_sop_o(rd0_sop), .rd0_eop_o(rd0_eop),
 346       .rd1_dat_o(rd1_dat), .rd1_read_i(rd1_read), .rd1_done_i(rd1_done),
 347       .rd1_error_i(rd1_error), .rd1_sop_o(rd1_sop), .rd1_eop_o(rd1_eop),
 348       .rd2_dat_o(rd2_dat), .rd2_read_i(rd2_read), .rd2_done_i(rd2_done),
 349       .rd2_error_i(rd2_error), .rd2_sop_o(rd2_sop), .rd2_eop_o(rd2_eop),
 350       .rd3_dat_o(rd3_dat), .rd3_read_i(rd3_read), .rd3_done_i(rd3_done),
 351       .rd3_error_i(rd3_error), .rd3_sop_o(rd3_sop), .rd3_eop_o(rd3_eop)
 352       );
 353
 354    // SPI -- Slave #2
 355    spi_top shared_spi
 356      (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o),
 357       .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
 358       .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(s2_err),.wb_int_o(spi_int),
 359       .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
 360       .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
 361
 362    assign        s2_rty = 1'b0;
 363
 364    // I2C -- Slave #3
 365    i2c_master_top #(.ARST_LVL(1))
 366      i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0),
 367           .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]),
 368           .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
 369           .wb_ack_o(s3_ack),.wb_inta_o(i2c_int),
 370           .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
 371           .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
 372
 373    assign        s3_dat_i[31:8] = 24'd0;
 374    assign        s3_err = 1'b0;
 375    assign        s3_rty = 1'b0;
 376
 377    // GPIOs -- Slave #4
 378    nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
 379                  .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
 380                  .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
 381                  .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
 382                  .gpio( {io_tx,io_rx} ) );
 383    assign        s4_err = 1'b0;
 384    assign        s4_rty = 1'b0;
 385
 386    // Buffer Pool Status -- Slave #5
 387    wb_readback_mux buff_pool_status
 388      (.wb_clk_i(wb_clk),
 389       .wb_rst_i(wb_rst),
 390       .wb_stb_i(s5_stb),
 391       .wb_adr_i(s5_adr),
 392       .wb_dat_o(s5_dat_i),
 393       .wb_ack_o(s5_ack),
 394
 395       .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
 396       .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
 397       .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0),
 398       .word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0)
 399       );
 400
 401    assign        s5_err = 1'b0;
 402    assign        s5_rty = 1'b0;
 403
 404    // Slave, #6 Ethernet MAC, see below
 405
 406    // Settings Bus -- Slave #7
 407    settings_bus settings_bus
 408      (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o),
 409       .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack),
 410       .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data));
 411
 412    assign        s7_err = 1'b0;
 413    assign        s7_rty = 1'b0;
 414    assign        s7_dat_i = 32'd0;
 415
 416    // Output control lines
 417    wire [7:0]    clock_outs, serdes_outs, adc_outs;
 418    assign        {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
 419    assign        {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0];
 420    assign        {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0];
 421
 422    wire          phy_reset;
 423    assign        PHY_RESETn = ~phy_reset;
 424
 425    setting_reg #(.my_addr(0)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),
 426                                       .in(set_data),.out(clock_outs),.changed());
 427    setting_reg #(.my_addr(1)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
 428                                       .in(set_data),.out(serdes_outs),.changed());
 429    setting_reg #(.my_addr(2)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
 430                                       .in(set_data),.out(adc_outs),.changed());
 431    setting_reg #(.my_addr(4)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
 432                                       .in(set_data),.out(phy_reset),.changed());
 433
 434    // /////////////////////////////////////////////////////////////////////////
 435    //  LEDS
 436    //    register 8 determines whether leds are controlled by SW or not
 437    //    1 = controlled by HW, 0 = by SW
 438    //    In Rev3 there are only 6 leds, and the highest one is on the ETH connector
 439
 440    wire [7:0]    led_src, led_sw;
 441    wire [7:0]    led_hw = {clk_status,serdes_link_up};
 442
 443    setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
 444                                       .in(set_data),.out(led_sw),.changed());
 445    setting_reg #(.my_addr(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
 446                                           .in(set_data),.out(led_src),.changed());
 447
 448    assign        leds = (led_src & led_hw) | (~led_src & led_sw);
 449
 450    // /////////////////////////////////////////////////////////////////////////
 451    // Ethernet MAC  Slave #6
 452
 453    wire          Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, Tx_mac_eop;
 454    wire          Rx_mac_empty, Rx_mac_rd, Rx_mac_sop, Rx_mac_eop, Rx_mac_err;
 455    wire [31:0]   Tx_mac_data, Rx_mac_data;
 456    wire [1:0]    Tx_mac_BE, Rx_mac_BE;
 457    wire          rst_mac;
 458
 459    oneshot_2clk mac_rst_1shot (.clk_in(wb_clk),.in(wb_rst),.clk_out(clk_to_mac),.out(rst_mac));
 460
 461    MAC_top #(.TX_FF_DEPTH(9), .RX_FF_DEPTH(11))
 462      MAC_top
 463        (.Clk_125M(clk_to_mac),.Clk_user(dsp_clk),
 464         .rst_mac(rst_mac),.rst_user(dsp_rst),
 465         .RST_I(wb_rst),.CLK_I(wb_clk),.STB_I(s6_stb),.CYC_I(s6_cyc),.ADR_I(s6_adr[8:2]),
 466         .WE_I(s6_we),.DAT_I(s6_dat_o),.DAT_O(s6_dat_i),.ACK_O(s6_ack),
 467         .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),.Rx_mac_BE(Rx_mac_BE),
 468         .Rx_mac_sop(Rx_mac_sop),.Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err),
 469         .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data),
 470         .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop),
 471         .Gtx_clk(GMII_GTX_CLK),.Tx_clk(GMII_TX_CLK),.Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD),
 472         .Rx_clk(GMII_RX_CLK),.Rx_er(GMII_RX_ER),.Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD),
 473         .Crs(GMII_CRS),.Col(GMII_COL),
 474         .Mdio(MDIO),.Mdc(MDC),
 475         .rx_fifo_occupied(eth_rx_occ2),.rx_fifo_full(eth_rx_full2),.rx_fifo_empty(eth_rx_empty2),
 476         .tx_fifo_occupied(),.tx_fifo_full(),.tx_fifo_empty(),
 477         .debug0(debug_mac0),.debug1(debug_mac1) );
 478
 479    assign        s6_err = 1'b0;
 480    assign        s6_rty = 1'b0;
 481
 482    mac_rxfifo_int mac_rxfifo_int
 483      (.clk(dsp_clk),.rst(dsp_rst),
 484       .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),
 485       .Rx_mac_BE(Rx_mac_BE),.Rx_mac_sop(Rx_mac_sop),
 486       .Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err),
 487       .wr_dat_o(wr2_dat),.wr_write_o(wr2_write),.wr_done_o(wr2_done),
 488       .wr_error_o(wr2_error),.wr_ready_i(wr2_ready),.wr_full_i(wr2_full),
 489       .fifo_occupied(eth_rx_occ),.fifo_full(eth_rx_full),.fifo_empty(eth_rx_empty) );
 490
 491    mac_txfifo_int mac_txfifo_int
 492      (.clk(dsp_clk),.rst(dsp_rst),.mac_clk(clk_to_mac),
 493       .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data),
 494       .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop),
 495       .rd_dat_i(rd2_dat),.rd_read_o(rd2_read),.rd_done_o(rd2_done),
 496       .rd_error_o(rd2_error),.rd_sop_i(rd2_sop),.rd_eop_i(rd2_eop),
 497       .fifo_occupied(eth_tx_occ),.fifo_full(eth_tx_full),.fifo_empty(eth_tx_empty) );
 498
 499    // /////////////////////////////////////////////////////////////////////////
 500    // Interrupt Controller, Slave #8
 501
 502    wire [15:0]   irq={{4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int},
 503                       {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}};
 504
 505    simple_pic #(.is(16),.dwidth(32)) simple_pic
 506      (.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]),
 507       .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
 508       .irq(irq) );
 509    assign        s8_err = 0;
 510    assign        s8_rty = 0;
 511
 512    // /////////////////////////////////////////////////////////////////////////
 513    // Master Timer, Slave #9
 514
 515    wire [31:0]   master_time;
 516    timer timer
 517      (.wb_clk_i(wb_clk),.rst_i(wb_rst),
 518       .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]),
 519       .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack),
 520       .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) );
 521    assign        s9_err = 0;
 522    assign        s9_rty = 0;
 523
 524    // /////////////////////////////////////////////////////////////////////////
 525    // UART, Slave #10
 526
 527    simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart  // depth of 3 is 128 entries
 528      (.clk_i(wb_clk),.rst_i(wb_rst),
 529       .we_i(s10_we),.stb_i(s10_stb),.cyc_i(s10_cyc),.ack_o(s10_ack),
 530       .adr_i(s10_adr[4:2]),.dat_i(s10_dat_o),.dat_o(s10_dat_i),
 531       .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int),
 532       .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o));
 533
 534    assign        s10_err = 0;
 535    assign        s10_rty = 0;
 536
 537    // /////////////////////////////////////////////////////////////////////////
 538    // ATR Controller, Slave #11
 539
 540    wire          run_rx, run_tx;
 541    reg           run_rx_d1;
 542    always @(posedge dsp_clk)
 543      run_rx_d1 <= run_rx;
 544
 545    atr_controller atr_controller
 546      (.clk_i(wb_clk),.rst_i(wb_rst),
 547       .adr_i(s11_adr[5:0]),.sel_i(s11_sel),.dat_i(s11_dat_o),.dat_o(s11_dat_i),
 548       .we_i(s11_we),.stb_i(s11_stb),.cyc_i(s11_cyc),.ack_o(s11_ack),
 549       .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) );
 550    assign        s11_err = 0;
 551    assign        s11_rty = 0;
 552
 553    // //////////////////////////////////////////////////////////////////////////
 554    // Time Sync, Slave #12
 555
 556    reg           pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1;
 557    always @(negedge dsp_clk) pps_negedge <= pps_in;
 558    always @(posedge dsp_clk) pps_posedge <= pps_in;
 559    always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge;
 560    always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge;
 561
 562    wire          pps_o;
 563    time_sync time_sync
 564      (.wb_clk_i(wb_clk),.rst_i(wb_rst),
 565       .cyc_i(s12_cyc),.stb_i(s12_stb),.adr_i(s12_adr[4:2]),
 566       .we_i(s12_we),.dat_i(s12_dat_o),.dat_o(s12_dat_i),.ack_o(s12_ack),
 567       .sys_clk_i(dsp_clk),.master_time_o(master_time),
 568       .pps_posedge(pps_posedge),.pps_negedge(pps_negedge),
 569       .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out),
 570       .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) );
 571    assign        s12_err = 0;
 572    assign        s12_rty = 0;
 573
 574    // /////////////////////////////////////////////////////////////////////////
 575    // SD Card Reader / Writer, Slave #13
 576
 577    sd_spi_wb sd_spi_wb
 578      (.clk(wb_clk),.rst(wb_rst),
 579       .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
 580       .wb_cyc_i(s13_cyc),.wb_stb_i(s13_stb),.wb_we_i(s13_we),
 581       .wb_adr_i(s13_adr[3:2]),.wb_dat_i(s13_dat_o),.wb_dat_o(s13_dat_i),
 582       .wb_ack_o(s13_ack) );
 583    assign        s13_err = 0;
 584    assign        s13_rty = 0;
 585    // /////////////////////////////////////////////////////////////////////////
 586    // DSP
 587    wire [31:0]   sample_rx, sample_tx;
 588    wire          strobe_rx, strobe_tx;
 589
 590    rx_control #(.FIFOSIZE(10)) rx_control
 591      (.clk(dsp_clk), .rst(dsp_rst),
 592       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
 593       .master_time(master_time),.overrun(overrun),
 594       .wr_dat_o(wr1_dat), .wr_write_o(wr1_write), .wr_done_o(wr1_done), .wr_error_o(wr1_error),
 595       .wr_ready_i(wr1_ready), .wr_full_i(wr1_full),
 596       .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
 597       .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty),
 598       .debug_rx(debug_rx) );
 599
 600    // dummy_rx dsp_core_rx
 601    dsp_core_rx dsp_core_rx
 602      (.clk(dsp_clk),.rst(dsp_rst),
 603       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
 604       .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
 605       .io_rx(io_rx),.sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx),
 606       .debug(debug_rx_dsp) );
 607
 608    tx_control #(.FIFOSIZE(10)) tx_control
 609      (.clk(dsp_clk), .rst(dsp_rst),
 610       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
 611       .master_time(master_time),.underrun(underrun),
 612       .rd_dat_i(rd1_dat), .rd_sop_i(rd1_sop), .rd_eop_i(rd1_eop),
 613       .rd_read_o(rd1_read), .rd_done_o(rd1_done), .rd_error_o(rd1_error),
 614       .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
 615       .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty),
 616       .debug(debug_txc) );
 617
 618    dsp_core_tx dsp_core_tx
 619      (.clk(dsp_clk),.rst(dsp_rst),
 620       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
 621       .dac_a(dac_a),.dac_b(dac_b),
 622       .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_tx_dsp) );
 623
 624    assign dsp_rst = wb_rst;
 625
 626    // ///////////////////////////////////////////////////////////////////////////////////
 627    // SERDES
 628
 629    serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes
 630      (.clk(dsp_clk),.rst(dsp_rst),
 631       .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
 632       .rd_dat_i(rd0_dat),.rd_read_o(rd0_read),.rd_done_o(rd0_done),.rd_error_o(rd0_error),
 633       .rd_sop_i(rd0_sop),.rd_eop_i(rd0_eop),
 634       .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
 635       .wr_dat_o(wr0_dat),.wr_write_o(wr0_write),.wr_done_o(wr0_done),.wr_error_o(wr0_error),
 636       .wr_ready_i(wr0_ready),.wr_full_i(wr0_full),
 637       .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty),
 638       .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
 639       .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) );
 640
 641    // ///////////////////////////////////////////////////////////////////////////////////
 642    // External RAM Interface
 643
 644    localparam PAGE_SIZE = 10;  // PAGE SIZE is in bytes, 10 = 1024 bytes
 645
 646    wire [15:0] bus2ram, ram2bus;
 647    wire [15:0] bridge_adr;
 648    wire [1:0]  bridge_sel;
 649    wire        bridge_stb, bridge_cyc, bridge_we, bridge_ack;
 650
 651    wire [19:0] page;
 652    wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]};
 653    setting_reg #(.my_addr(6)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
 654                                        .in(set_data),.out(page),.changed());
 655
 656    wb_bridge_16_32 bridge
 657      (.wb_clk(wb_clk),.wb_rst(wb_rst),
 658       .A_cyc_i(s14_cyc),.A_stb_i(s14_stb),.A_we_i(s14_we),.A_sel_i(s14_sel),
 659       .A_adr_i(s14_adr),.A_dat_i(s14_dat_o),.A_dat_o(s14_dat_i),.A_ack_o(s14_ack),
 660       .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel),
 661       .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack));
 662
 663    wb_zbt16_b wb_zbt16_b
 664      (.clk(wb_clk),.rst(wb_rst),
 665       .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel),
 666       .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we),
 667       .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn),
 668       .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn),
 669       .sram_mode(),.sram_zz() );
 670
 671    assign      s14_err = 0; assign s14_rty = 0;
 672    assign      RAM_CE1n = 0;
 673    assign      RAM_D[17:16] = 2'bzz;
 674
 675    // /////////////////////////////////////////////////////////////////////////////////////////
 676    // Debug Pins
 677
 678    // FIFO Level Debugging
 679    reg [31:0]  host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo;
 680
 681    always @(posedge dsp_clk)
 682      serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]},
 683                              {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
 684
 685    always @(posedge dsp_clk)
 686      dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]},
 687                              {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
 688
 689    always @(posedge dsp_clk)
 690      host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]},
 691                            {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
 692
 693    always @(posedge dsp_clk)
 694      dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]},
 695                            {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
 696
 697    always @(posedge dsp_clk)
 698      eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]},
 699                         {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} };
 700
 701    assign      debug_clk[0] = 0;
 702    assign      debug_clk[1] = dsp_clk;
 703
 704    assign     debug = host_to_dsp_fifo; // debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo;
 705    assign      debug_gpio_0 = eth_mac_debug;
 706    assign      debug_gpio_1 = 0;
 707
 708 endmodule // u2_core
 709
 710 //   wire        debug_mux;
 711 //   setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
 712 //                                      .in(set_data),.out(debug_mux),.changed());
 713
 714 //assign     debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo;
 715 //assign     debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo;
 716
 717 //assign      debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a},
 718 //              {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}};
 719
 720 //assign      debug = debug_tx_dsp;
 721 //assign      debug = debug_serdes0;
 722
 723 //assign      debug_gpio_0 = 0; //debug_serdes0;
 724 //assign      debug_gpio_1 = 0; //debug_serdes1;
 725
 726 //   assign      debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success},
 727 //            {8'b0},
 728 //      {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done },
 729 //    {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} };
 730
 731 //assign      debug = {dac_a,dac_b};
 732
 733 /*
 734  assign      debug = {{ram_loader_done, takeover, 6'd0},
 735  {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi},
 736  {8'd0},
 737  {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */
 738
 739 /*assign      debug = host_to_dsp_fifo;
 740  assign      debug_gpio_0 = eth_mac_debug;
 741  assign      debug_gpio_1 = 0;
 742  */
 743 // Assign various commonly used debug buses.
 744 /*
 745  wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV,
 746  irq[7:0],
 747  GMII_RXD,
 748  GMII_TXD};
 749
 750  wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] };
 751
 752    wire [31:0] debug_time =  {uart_tx_o, 7'b0,
 753                               irq[7:0],
 754                               6'b0, GMII_RX_DV, GMII_TX_EN,
 755                               4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int};
 756
 757    wire [31:0] debug_irq =  {uart_tx_o, iwb_adr, iwb_ack,
 758                              irq[7:0],
 759                              proc_int,  7'b0 };
 760
 761    wire [31:0] debug_eth =
 762                {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write},
 763                 {8'd0},
 764                 {8'd0},
 765                 {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} };
 766
 767    assign      debug_serdes0 = { { rd0_dat[7:0] },
 768                                  { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done },
 769                                  { ser_t[15:8] },
 770                                  { ser_t[7:0] } };
 771
 772    assign      debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write},
 773                                  { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en },
 774                                  { ser_r[15:8] },
 775                                  { ser_r[7:0] } };
 776
 777    assign      debug_gpio_1 = {uart_tx_o,7'd0,
 778                                3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error,
 779                                debug_txc[15:0]};
 780    assign      debug_gpio_1 = debug_rx;
 781    assign      debug_gpio_1 = debug_serdes1;
 782    assign      debug_gpio_1 = debug_eth;
 783
 784     */
 785