1f78f6d3d5eb49477dd05f9d229fe7aa2fcda76c
[debian/gnuradio] / usrp2 / fpga / top / u2_core / u2_core.v
1 // ////////////////////////////////////////////////////////////////////////////////
2 // Module Name:    u2_core
3 // ////////////////////////////////////////////////////////////////////////////////
4
5 module u2_core
6   #(parameter RAM_SIZE=32768)
7   (// Clocks
8    input dsp_clk,
9    input wb_clk,
10    output clock_ready,
11    input clk_to_mac,
12    input pps_in,
13    
14    // Misc, debug
15    output [7:0] leds,
16    output [31:0] debug,
17    output [1:0] debug_clk,
18
19    // Expansion
20    input exp_pps_in,
21    output exp_pps_out,
22    
23    // GMII
24    //   GMII-CTRL
25    input GMII_COL,
26    input GMII_CRS,
27
28    //   GMII-TX
29    output [7:0] GMII_TXD,
30    output GMII_TX_EN,
31    output GMII_TX_ER,
32    output GMII_GTX_CLK,
33    input GMII_TX_CLK,  // 100mbps clk
34
35    //   GMII-RX
36    input [7:0] GMII_RXD,
37    input GMII_RX_CLK,
38    input GMII_RX_DV,
39    input GMII_RX_ER,
40
41    //   GMII-Management
42    inout MDIO,
43    output MDC,
44    input PHY_INTn,   // open drain
45    output PHY_RESETn,
46
47    // SERDES
48    output ser_enable,
49    output ser_prbsen,
50    output ser_loopen,
51    output ser_rx_en,
52    
53    output ser_tx_clk,
54    output [15:0] ser_t,
55    output ser_tklsb,
56    output ser_tkmsb,
57
58    input ser_rx_clk,
59    input [15:0] ser_r,
60    input ser_rklsb,
61    input ser_rkmsb,
62    
63    // CPLD interface
64    output cpld_start,
65    output cpld_mode,
66    output cpld_done,
67    input cpld_din,
68    input cpld_clk,
69    input cpld_detached,
70    output cpld_misc,
71    input cpld_init_b,
72    input por,
73    output config_success,
74    
75    // ADC
76    input [13:0] adc_a,
77    input adc_ovf_a,
78    output adc_on_a,
79    output adc_oe_a,
80    
81    input [13:0] adc_b,
82    input adc_ovf_b,
83    output adc_on_b,
84    output adc_oe_b,
85    
86    // DAC
87    output [15:0] dac_a,
88    output [15:0] dac_b,
89
90    // I2C
91    input scl_pad_i,
92    output scl_pad_o,
93    output scl_pad_oen_o,
94    input sda_pad_i,
95    output sda_pad_o,
96    output sda_pad_oen_o,
97    
98    // Clock Gen Control
99    output [1:0] clk_en,
100    output [1:0] clk_sel,
101    input clk_func,        // FIXME is an input to control the 9510
102    input clk_status,
103
104    // Generic SPI
105    output sclk,
106    output mosi,
107    input miso,
108    output sen_clk,
109    output sen_dac,
110    output sen_tx_db,
111    output sen_tx_adc,
112    output sen_tx_dac,
113    output sen_rx_db,
114    output sen_rx_adc,
115    output sen_rx_dac,
116    
117    // GPIO to DBoards
118    inout [15:0] io_tx,
119    inout [15:0] io_rx,
120
121    // External RAM
122    inout [17:0] RAM_D,
123    output [18:0] RAM_A,
124    output RAM_CE1n,
125    output RAM_CENn,
126    output RAM_CLK,
127    output RAM_WEn,
128    output RAM_OEn,
129    output RAM_LDn,
130    
131    // Debug stuff
132    output uart_tx_o, 
133    input uart_rx_i,
134    output uart_baud_o,
135    input sim_mode,
136    input [3:0] clock_divider
137    );
138    
139    wire [7:0]   set_addr;
140    wire [31:0]  set_data;
141    wire         set_stb;
142    
143    wire         ram_loader_done;
144    wire         ram_loader_rst, wb_rst, dsp_rst;
145
146    wire [31:0]  status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7;
147    wire         bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int;
148
149    wire [31:0]  debug_gpio_0, debug_gpio_1;
150    wire [31:0]  atr_lines;
151
152    wire [31:0]  debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, 
153                 debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp;
154
155    wire [15:0]  ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2;
156    wire         ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2;
157    wire         ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2;
158         
159    wire         serdes_link_up;
160    wire         epoch;
161    
162    // ///////////////////////////////////////////////////////////////////////////////////////////////
163    // Wishbone Single Master INTERCON
164    localparam   dw = 32;  // Data bus width
165    localparam   aw = 16;  // Address bus width, for byte addressibility, 16 = 64K byte memory space
166    localparam   sw = 4;   // Select width -- 32-bit data bus with 8-bit granularity.  
167    
168    wire [dw-1:0] m0_dat_o, m0_dat_i;
169    wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i,
170                  s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i,
171                  s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o,
172                  sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o;
173    wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr;
174    wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel;
175    wire          m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack;
176    wire          m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb;
177    wire          m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc;
178    wire          m0_err, m0_rty;
179    wire          m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we;
180    
181    wb_1master #(.decode_w(6),
182                 .s0_addr(6'b0000_00),.s0_mask(6'b100000),
183                 .s1_addr(6'b1000_00),.s1_mask(6'b110000),
184                 .s2_addr(6'b1100_00),.s2_mask(6'b111111),
185                 .s3_addr(6'b1100_01),.s3_mask(6'b111111),
186                 .s4_addr(6'b1100_10),.s4_mask(6'b111111),
187                 .s5_addr(6'b1100_11),.s5_mask(6'b111111),
188                 .s6_addr(6'b1101_00),.s6_mask(6'b111111),
189                 .s7_addr(6'b1101_01),.s7_mask(6'b111111),
190                 .s8_addr(6'b1101_10),.s8_mask(6'b111111),
191                 .s9_addr(6'b1101_11),.s9_mask(6'b111111),
192                 .sa_addr(6'b1110_00),.sa_mask(6'b111111),
193                 .sb_addr(6'b1110_01),.sb_mask(6'b111111),
194                 .sc_addr(6'b1110_10),.sc_mask(6'b111111),
195                 .sd_addr(6'b1110_11),.sd_mask(6'b111111),
196                 .se_addr(6'b1111_00),.se_mask(6'b111111),
197                 .sf_addr(6'b1111_01),.sf_mask(6'b111111),
198                 .dw(dw),.aw(aw),.sw(sw)) wb_1master
199      (.clk_i(wb_clk),.rst_i(wb_rst),       
200       .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
201       .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
202       .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o  (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
203       .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0),
204       .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o  (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
205       .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0),
206       .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o  (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
207       .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0),
208       .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o  (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
209       .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0),
210       .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o  (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
211       .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0),
212       .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o  (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
213       .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0),
214       .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o  (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
215       .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0),
216       .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o  (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
217       .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0),
218       .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o  (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb),
219       .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0),
220       .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o  (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
221       .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0),
222       .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb),
223       .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0),
224       .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb),
225       .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0),
226       .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb),
227       .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0),
228       .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb),
229       .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0),
230       .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb),
231       .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0),
232       .sf_dat_i(0),.sf_ack_i(0),.sf_err_i(0),.sf_rty_i(0)  );
233    
234    //////////////////////////////////////////////////////////////////////////////////////////
235    // Reset Controller
236    system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por),
237                            .ram_loader_rst_o(ram_loader_rst),
238                            .wb_rst_o(wb_rst),
239                            .ram_loader_done_i(ram_loader_done));
240
241    assign        config_success = ram_loader_done;
242    reg           takeover = 0;
243
244    wire          cpld_start_int, cpld_mode_int, cpld_done_int;
245    
246    always @(posedge wb_clk)
247      if(ram_loader_done)
248        takeover = 1;
249    assign        cpld_misc = ~takeover;
250
251    wire          sd_clk, sd_csn, sd_mosi, sd_miso;
252    
253    assign        sd_miso = cpld_din;
254    assign        cpld_start = takeover ? sd_clk : cpld_start_int;
255    assign        cpld_mode = takeover ? sd_csn : cpld_mode_int;
256    assign        cpld_done = takeover ? sd_mosi : cpld_done_int;
257    
258    // ///////////////////////////////////////////////////////////////////
259    // RAM Loader
260
261    wire [31:0]   ram_loader_dat, iwb_dat;
262    wire [15:0]   ram_loader_adr, iwb_adr;
263    wire [3:0]    ram_loader_sel;
264    wire          ram_loader_stb, ram_loader_we, ram_loader_ack;
265    wire          iwb_ack, iwb_stb;
266    ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE))
267      ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
268                  // CPLD Interface
269                  .cfg_clk_i(cpld_clk),
270                  .cfg_data_i(cpld_din),
271                  .start_o(cpld_start_int),
272                  .mode_o(cpld_mode_int),
273                  .done_o(cpld_done_int),
274                  .detached_i(cpld_detached),
275                  // Wishbone Interface
276                  .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr),
277                  .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel),
278                  .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack),
279                  .ram_loader_done_o(ram_loader_done));
280
281    // Processor
282    aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1))
283      aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
284            // Instruction Wishbone bus to I-RAM
285            .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr),
286            .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack),
287            // Data Wishbone bus to system bus fabric
288            .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
289            .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
290            // Interrupts and exceptions
291            .sys_int_i(proc_int),.sys_exc_i(bus_error) );
292    
293    assign        bus_error = m0_err | m0_rty;
294    
295    // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone
296    // I-port connects directly to processor and ram loader
297
298    wire          flush_icache;
299    ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
300      sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
301              
302              .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat),
303              .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel),
304              .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack),
305              .ram_loader_done_i(ram_loader_done),
306              
307              .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb),
308              .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack),
309              
310              .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
311              .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel),
312              .flush_icache(flush_icache));
313    
314    setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
315                                          .in(set_data),.out(),.changed(flush_icache));
316
317    // Buffer Pool, slave #1
318    wire          rd0_ready_i, rd0_ready_o;
319    wire          rd1_ready_i, rd1_ready_o;
320    wire          rd2_ready_i, rd2_ready_o;
321    wire          rd3_ready_i, rd3_ready_o;
322    wire [3:0]    rd0_flags, rd1_flags, rd2_flags, rd3_flags;
323    wire [31:0]   rd0_dat, rd1_dat, rd2_dat, rd3_dat;
324
325    wire          wr0_ready_i, wr0_ready_o;
326    wire          wr1_ready_i, wr1_ready_o;
327    wire          wr2_ready_i, wr2_ready_o;
328    wire          wr3_ready_i, wr3_ready_o;
329    wire [3:0]    wr0_flags, wr1_flags, wr2_flags, wr3_flags;
330    wire [31:0]   wr0_dat, wr1_dat, wr2_dat, wr3_dat;
331    
332    buffer_pool #(.BUF_SIZE(9), .SET_ADDR(64)) buffer_pool
333      (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
334       .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),   
335       .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(),
336    
337       .stream_clk(dsp_clk), .stream_rst(dsp_rst),
338       .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
339       .status(status),.sys_int_o(buffer_int),
340
341       .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3),
342       .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7),
343
344       // Write Interfaces
345       .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o),
346       .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o),
347       .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o),
348       .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o),
349       // Read Interfaces
350       .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o),
351       .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o),
352       .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o),
353       .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o)
354       );
355
356    // SPI -- Slave #2
357    spi_top shared_spi
358      (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o),
359       .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
360       .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int),
361       .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
362       .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
363
364    // I2C -- Slave #3
365    i2c_master_top #(.ARST_LVL(1)) 
366      i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), 
367           .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]),
368           .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
369           .wb_ack_o(s3_ack),.wb_inta_o(i2c_int),
370           .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
371           .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
372
373    assign        s3_dat_i[31:8] = 24'd0;
374    
375    // GPIOs -- Slave #4
376    nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
377                  .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
378                  .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
379                  .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
380                  .gpio( {io_tx,io_rx} ) );
381
382    // Buffer Pool Status -- Slave #5
383    wb_readback_mux buff_pool_status
384      (.wb_clk_i(wb_clk),
385       .wb_rst_i(wb_rst),
386       .wb_stb_i(s5_stb),
387       .wb_adr_i(s5_adr),
388       .wb_dat_o(s5_dat_i),
389       .wb_ack_o(s5_ack),
390       
391       .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
392       .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
393       .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0),
394       .word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0)
395       );
396
397    // /////////////////////////////////////////////////////////////////////////
398    // Ethernet MAC  Slave #6
399
400    simple_gemac_wrapper #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper
401      (.clk125(clk_to_mac),  .reset(wb_rst),
402       .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
403       .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
404       .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
405       .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
406       .sys_clk(dsp_clk),
407       .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o),
408       .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i),
409       .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack),
410       .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i),
411       .mdio(MDIO), .mdc(MDC),
412       .debug(debug_mac));
413    
414    // /////////////////////////////////////////////////////////////////////////
415    // Settings Bus -- Slave #7
416    settings_bus settings_bus
417      (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o),
418       .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack),
419       .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data));
420    
421    assign        s7_dat_i = 32'd0;
422
423    // Output control lines
424    wire [7:0]    clock_outs, serdes_outs, adc_outs;
425    assign        {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
426    assign        {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0];
427    assign        {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0];
428
429    wire          phy_reset;
430    assign        PHY_RESETn = ~phy_reset;
431    
432    setting_reg #(.my_addr(0)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),
433                                       .in(set_data),.out(clock_outs),.changed());
434    setting_reg #(.my_addr(1)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
435                                       .in(set_data),.out(serdes_outs),.changed());
436    setting_reg #(.my_addr(2)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
437                                       .in(set_data),.out(adc_outs),.changed());
438    setting_reg #(.my_addr(4)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
439                                       .in(set_data),.out(phy_reset),.changed());
440
441    // /////////////////////////////////////////////////////////////////////////
442    //  LEDS
443    //    register 8 determines whether leds are controlled by SW or not
444    //    1 = controlled by HW, 0 = by SW
445    //    In Rev3 there are only 6 leds, and the highest one is on the ETH connector
446    
447    wire [7:0]    led_src, led_sw;
448    wire [7:0]    led_hw = {clk_status,serdes_link_up};
449    
450    setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
451                                       .in(set_data),.out(led_sw),.changed());
452    setting_reg #(.my_addr(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
453                                           .in(set_data),.out(led_src),.changed());
454
455    assign        leds = (led_src & led_hw) | (~led_src & led_sw);
456    
457    // /////////////////////////////////////////////////////////////////////////
458    // Interrupt Controller, Slave #8
459
460    wire [15:0]   irq={{4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int},
461                       {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}};
462    
463    simple_pic #(.is(16),.dwidth(32)) simple_pic
464      (.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]),
465       .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
466       .irq(irq) );
467          
468    // /////////////////////////////////////////////////////////////////////////
469    // Master Timer, Slave #9
470
471    wire [31:0]   master_time;
472    timer timer
473      (.wb_clk_i(wb_clk),.rst_i(wb_rst),
474       .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]),
475       .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack),
476       .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) );
477
478    // /////////////////////////////////////////////////////////////////////////
479    // UART, Slave #10
480
481    simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart  // depth of 3 is 128 entries
482      (.clk_i(wb_clk),.rst_i(wb_rst),
483       .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack),
484       .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i),
485       .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int),
486       .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o));
487    
488    // /////////////////////////////////////////////////////////////////////////
489    // ATR Controller, Slave #11
490
491    wire          run_rx, run_tx;
492    reg           run_rx_d1;
493    always @(posedge dsp_clk)
494      run_rx_d1 <= run_rx;
495    
496    atr_controller atr_controller
497      (.clk_i(wb_clk),.rst_i(wb_rst),
498       .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i),
499       .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack),
500       .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) );
501    
502    // //////////////////////////////////////////////////////////////////////////
503    // Time Sync, Slave #12 
504
505    reg           pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1;
506    always @(negedge dsp_clk) pps_negedge <= pps_in;
507    always @(posedge dsp_clk) pps_posedge <= pps_in;
508    always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge;
509    always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge;   
510    
511    wire          pps_o;
512    time_sync time_sync
513      (.wb_clk_i(wb_clk),.rst_i(wb_rst),
514       .cyc_i(sc_cyc),.stb_i(sc_stb),.adr_i(sc_adr[4:2]),
515       .we_i(sc_we),.dat_i(sc_dat_o),.dat_o(sc_dat_i),.ack_o(sc_ack),
516       .sys_clk_i(dsp_clk),.master_time_o(master_time),
517       .pps_posedge(pps_posedge),.pps_negedge(pps_negedge),
518       .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out),
519       .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) );
520
521    // /////////////////////////////////////////////////////////////////////////
522    // SD Card Reader / Writer, Slave #13
523
524    sd_spi_wb sd_spi_wb
525      (.clk(wb_clk),.rst(wb_rst),
526       .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
527       .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we),
528       .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o),.wb_dat_o(sd_dat_i),
529       .wb_ack_o(sd_ack) );
530
531    // /////////////////////////////////////////////////////////////////////////
532    // DSP
533    wire [31:0]   sample_rx, sample_tx;
534    wire          strobe_rx, strobe_tx;
535
536    rx_control #(.FIFOSIZE(10)) rx_control
537      (.clk(dsp_clk), .rst(dsp_rst),
538       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
539       .master_time(master_time),.overrun(overrun),
540       .wr_dat_o(wr1_dat), .wr_flags_o(wr1_flags), .wr_ready_o(wr1_ready_i), .wr_ready_i(wr1_ready_o),
541       .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
542       .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty),
543       .debug_rx(debug_rx) );
544    
545    // dummy_rx dsp_core_rx
546    dsp_core_rx dsp_core_rx
547      (.clk(dsp_clk),.rst(dsp_rst),
548       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
549       .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
550       .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx),
551       .debug(debug_rx_dsp) );
552
553    tx_control #(.FIFOSIZE(10)) tx_control
554      (.clk(dsp_clk), .rst(dsp_rst),
555       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
556       .master_time(master_time),.underrun(underrun),
557       .rd_dat_i(rd1_dat), .rd_flags_i(rd1_flags), .rd_ready_i(rd1_ready_o), .rd_ready_o(rd1_ready_i),
558       .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
559       .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty),
560       .debug(debug_txc) );
561    
562    dsp_core_tx dsp_core_tx
563      (.clk(dsp_clk),.rst(dsp_rst),
564       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
565       .dac_a(dac_a),.dac_b(dac_b),
566       .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_tx_dsp) );
567
568    assign dsp_rst = wb_rst;
569
570    // ///////////////////////////////////////////////////////////////////////////////////
571    // SERDES
572
573    serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes
574      (.clk(dsp_clk),.rst(dsp_rst),
575       .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
576       .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o),
577       .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
578       .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o),
579       .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty),
580       .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
581       .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) );
582
583    // ///////////////////////////////////////////////////////////////////////////////////
584    // External RAM Interface
585
586    localparam PAGE_SIZE = 10;  // PAGE SIZE is in bytes, 10 = 1024 bytes
587
588    wire [15:0] bus2ram, ram2bus;
589    wire [15:0] bridge_adr;
590    wire [1:0]  bridge_sel;
591    wire        bridge_stb, bridge_cyc, bridge_we, bridge_ack;
592    
593    wire [19:0] page;
594    wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]};
595    setting_reg #(.my_addr(6)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
596                                        .in(set_data),.out(page),.changed());
597
598    wb_bridge_16_32 bridge
599      (.wb_clk(wb_clk),.wb_rst(wb_rst),
600       .A_cyc_i(se_cyc),.A_stb_i(se_stb),.A_we_i(se_we),.A_sel_i(se_sel),
601       .A_adr_i(se_adr),.A_dat_i(se_dat_o),.A_dat_o(se_dat_i),.A_ack_o(se_ack),
602       .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel),
603       .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack));
604
605    wb_zbt16_b wb_zbt16_b
606      (.clk(wb_clk),.rst(wb_rst),
607       .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel),
608       .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we),
609       .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn),
610       .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn),
611       .sram_mode(),.sram_zz() );
612
613    assign      RAM_CE1n = 0;
614    assign      RAM_D[17:16] = 2'bzz;
615    
616    // /////////////////////////////////////////////////////////////////////////////////////////
617    // Debug Pins
618    
619    // FIFO Level Debugging
620    reg [31:0]  host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo;
621    
622    always @(posedge dsp_clk)
623      serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]},
624                              {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
625
626    always @(posedge dsp_clk)
627      dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]},
628                              {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
629    
630    always @(posedge dsp_clk)
631      host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]},
632                            {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
633    
634    always @(posedge dsp_clk)
635      dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]},
636                            {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
637    
638    always @(posedge dsp_clk)
639      eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]},
640                         {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} };
641    
642    assign  debug_clk[0]  = 0; // wb_clk;
643    assign  debug_clk[1]  = clk_to_mac;  
644 /*
645  
646    wire        mdio_cpy  = MDIO;
647    assign  debug         = { { 1'b0, s6_stb, s6_ack, s6_we, s6_sel[3:0] },
648                              { s6_adr[15:8] },
649                              { s6_adr[7:0] },
650                              { 6'd0, mdio_cpy, MDC } };
651 */
652 /*
653    assign debug          = { { GMII_TXD },
654                              { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK },
655                              { wr2_flags, rd2_flags },
656                              { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } };
657  */        
658    assign debug          = { { GMII_RXD },
659                              { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK },
660                              { wr2_flags, rd2_flags },
661                              { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } };
662           
663    assign  debug_gpio_0 = debug_mac; //eth_mac_debug;
664    assign  debug_gpio_1 = 0;
665    
666 endmodule // u2_core
667
668 //   wire        debug_mux;
669 //   setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
670 //                                      .in(set_data),.out(debug_mux),.changed());
671
672 //assign     debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo;
673 //assign     debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo;
674    
675 //assign      debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a},
676 //              {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}};
677
678 //assign      debug = debug_tx_dsp;
679 //assign      debug = debug_serdes0;
680
681 //assign      debug_gpio_0 = 0; //debug_serdes0;
682 //assign      debug_gpio_1 = 0; //debug_serdes1;
683
684 //   assign      debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success},
685 //            {8'b0},
686 //      {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done },
687 //    {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} };
688
689 //assign      debug = {dac_a,dac_b};
690
691 /*
692  assign      debug = {{ram_loader_done, takeover, 6'd0},
693  {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi},
694  {8'd0},
695  {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */
696
697 /*assign      debug = host_to_dsp_fifo;
698  assign      debug_gpio_0 = eth_mac_debug;
699  assign      debug_gpio_1 = 0;
700  */
701 // Assign various commonly used debug buses.
702 /*
703  wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV,
704  irq[7:0],
705  GMII_RXD,
706  GMII_TXD};
707  
708  wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] };
709    
710    wire [31:0] debug_time =  {uart_tx_o, 7'b0,
711                               irq[7:0],
712                               6'b0, GMII_RX_DV, GMII_TX_EN,
713                               4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int};
714
715    wire [31:0] debug_irq =  {uart_tx_o, iwb_adr, iwb_ack,
716                              irq[7:0],
717                              proc_int,  7'b0 };
718
719    wire [31:0] debug_eth = 
720                {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write},
721                 {8'd0},
722                 {8'd0},
723                 {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} };
724
725    assign      debug_serdes0 = { { rd0_dat[7:0] },
726                                  { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done },
727                                  { ser_t[15:8] },
728                                  { ser_t[7:0] } };
729
730    assign      debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write},
731                                  { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en },
732                                  { ser_r[15:8] },
733                                  { ser_r[7:0] } };
734        
735    assign      debug_gpio_1 = {uart_tx_o,7'd0,
736                                3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error,
737                                debug_txc[15:0]};
738    assign      debug_gpio_1 = debug_rx;
739    assign      debug_gpio_1 = debug_serdes1;
740    assign      debug_gpio_1 = debug_eth;
741       
742     */
743