4 (input wb_clk_i, input rst_i,
5 input cyc_i, input stb_i, input [2:0] adr_i,
6 input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o,
7 input sys_clk_i, input [31:0] master_time_i,
11 always @(posedge wb_clk_i)
12 time_wb <= master_time_i;
19 always @(posedge sys_clk_i)
25 else if(|int_time && (master_time_i == int_time))
36 assign dat_o = time_wb;
37 assign int_o = int_reg;