fullchip sim now compiles again, after moving eth and models over to new simple_gemac
[debian/gnuradio] / usrp2 / fpga / testbench / cmdfile
1
2 # My stuff
3 -y .
4 -y ../top/u2_core
5 -y ../control_lib
6 -y ../control_lib/newfifo
7 -y ../serdes
8 -y ../sdr_lib
9 -y ../timing
10 -y ../coregen
11 -y ../extram
12 -y ../simple_gemac
13 -y ../simple_gemac/miim
14
15 # Models
16 -y ../models
17 -y ../models/CY7C1356C
18
19 # Open Cores
20 -y ../opencores/8b10b
21 -y ../opencores/spi/rtl/verilog
22 +incdir+../opencores/spi/rtl/verilog
23 -y ../opencores/i2c/rtl/verilog
24 +incdir+../opencores/i2c/rtl/verilog
25 -y ../opencores/aemb/rtl/verilog
26 -y ../opencores/simple_pic/rtl
27