git.gag.com Git - debian/gnuradio/blob - usrp2/fpga/testbench/U2_SIM.sav

   1 [size] 1400 971
   2 [pos] -1 -1
   3 *-18.079937 3641000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
   4 @28
   5 u2_sim_top.adc_oen_a
   6 u2_sim_top.adc_oen_b
   7 u2_sim_top.adc_pdn_a
   8 u2_sim_top.adc_pdn_b
   9 u2_sim_top.aux_clk
  10 u2_sim_top.POR
  11 u2_sim_top.clk_fpga
  12 u2_sim_top.clk_en[1:0]
  13 u2_sim_top.clk_sel[1:0]
  14 u2_sim_top.led1
  15 u2_sim_top.led2
  16 u2_sim_top.sclk
  17 u2_sim_top.u2_basic.wb_conbus_top.wb_conbus_arb.gnt[2:0]
  18 u2_sim_top.sda_pad_o
  19 u2_sim_top.sda_pad_oen_o
  20 u2_sim_top.sdi
  21 u2_sim_top.sdo
  22 u2_sim_top.sen_clk
  23 u2_sim_top.sen_dac
  24 u2_sim_top.ser_enable
  25 u2_sim_top.ser_loopen
  26 u2_sim_top.ser_prbsen
  27 u2_sim_top.ser_rx_en
  28 u2_sim_top.u2_basic.sysctrl.start
  29 u2_sim_top.u2_basic.sysctrl.POR
  30 u2_sim_top.u2_basic.done
  31 u2_sim_top.u2_basic.sysctrl.POR
  32 u2_sim_top.u2_basic.sysctrl.aux_clk
  33 u2_sim_top.u2_basic.sysctrl.clk_fpga
  34 u2_sim_top.u2_basic.sysctrl.done
  35 u2_sim_top.u2_basic.bus_writer.start
  36 u2_sim_top.u2_basic.bus_writer.done
  37 @22
  38 u2_sim_top.u2_basic.bus_writer.rom_addr[15:0]
  39 u2_sim_top.u2_basic.bus_writer.rom_data[47:0]
  40 u2_sim_top.u2_basic.bus_writer.state[3:0]
  41 @29
  42 u2_sim_top.u2_basic.bus_writer.wb_ack_i
  43 @22
  44 u2_sim_top.u2_basic.bus_writer.wb_adr_o[15:0]
  45 @28
  46 u2_sim_top.u2_basic.bus_writer.wb_clk_i
  47 u2_sim_top.u2_basic.bus_writer.wb_cyc_o
  48 @22
  49 u2_sim_top.u2_basic.bus_writer.wb_dat_o[31:0]
  50 u2_sim_top.u2_basic.bus_writer.wb_sel_o[3:0]
  51 @28
  52 u2_sim_top.u2_basic.bus_writer.wb_stb_o
  53 u2_sim_top.u2_basic.bus_writer.wb_we_o
  54 u2_sim_top.u2_basic.bus_writer.wb_rst_i
  55 u2_sim_top.u2_basic.wb_conbus_top.wb_conbus_arb.req[7:0]
  56 u2_sim_top.sda_pad_i
  57 u2_sim_top.u2_basic.wb_conbus_top.m0_cyc_i
  58 u2_sim_top.u2_basic.wb_conbus_top.s0_cyc_o
  59 @22
  60 u2_sim_top.u2_basic.wb_conbus_top.m0_adr_i[15:0]
  61 u2_sim_top.u2_basic.wb_conbus_top.m1_adr_i[15:0]
  62 @28
  63 u2_sim_top.u2_basic.wb_conbus_top.m0_stb_i
  64 u2_sim_top.u2_basic.wb_conbus_top.m1_stb_i
  65 u2_sim_top.u2_basic.wb_conbus_top.s0_stb_o
  66 u2_sim_top.u2_basic.wb_conbus_top.s1_stb_o
  67 u2_sim_top.u2_basic.wb_conbus_top.s2_stb_o
  68 u2_sim_top.u2_basic.wb_conbus_top.s3_stb_o
  69 u2_sim_top.u2_basic.wb_conbus_top.s0_ack_i
  70 u2_sim_top.u2_basic.control_lines.wb_cyc_i
  71 u2_sim_top.u2_basic.control_lines.wb_stb_i
  72 u2_sim_top.u2_basic.control_lines.wb_we_i
  73 u2_sim_top.u2_basic.control_lines.wb_ack_o
  74 u2_sim_top.u2_basic.s0_ack
  75 @22
  76 u2_sim_top.u2_basic.control_lines.internal_reg[31:0]
  77 u2_sim_top.u2_basic.control_lines.port_output[31:0]
  78 @28
  79 u2_sim_top.u2_basic.led1
  80 u2_sim_top.u2_basic.led2
  81 @22
  82 u2_sim_top.u2_basic.misc_outs[7:0]
  83 u2_sim_top.u2_basic.clock_outs[7:0]
  84 u2_sim_top.u2_basic.adc_outs[7:0]
  85 u2_sim_top.u2_basic.serdes_outs[7:0]
  86 @28
  87 u2_sim_top.u2_basic.shared_spi.miso_pad_i
  88 u2_sim_top.u2_basic.shared_spi.mosi_pad_o
  89 @22
  90 u2_sim_top.u2_basic.shared_spi.ss[7:0]
  91 u2_sim_top.u2_basic.shared_spi.divider[15:0]
  92 @28
  93 u2_sim_top.u2_basic.shared_spi.sclk_pad_o
  94 @22
  95 u2_sim_top.u2_basic.shared_spi.ss_pad_o[7:0]