3 *-16.314999 5250420000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
5 [treeopen] u2_sim_top.u2_basic.
6 [treeopen] u2_sim_top.u2_basic.MAC_top.
7 [treeopen] u2_sim_top.u2_basic.MAC_top.U_MAC_tx.
9 u2_sim_top.GMII_TXD[7:0]
15 u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.fc_hwmark[15:0]
16 u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.fc_lwmark[15:0]
18 u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.pause_frame_send_en
20 u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.pause_quanta_set[15:0]
22 u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rst
23 u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rx_clk
25 u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rx_fifo_space[15:0]
27 u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.tx_clk
31 u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_gen
32 u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_gen_complete
33 u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_int
34 u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_int_d1
38 u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_gen
39 u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_gen_complete
40 u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_int
41 u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_int_d1
45 u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_apply
47 u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta[15:0]
48 u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_counter[15:0]
50 u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_sub
51 u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_val
52 u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pqval_d1
53 u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pqval_d2
54 u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.rst
55 u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.tx_clk
56 u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.tx_pause_en
57 u2_sim_top.u2_basic.proc_int
59 u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.countdown[21:0]
60 u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_counter[15:0]
62 u2_sim_top.u2_basic.MAC_top.U_MAC_tx.U_MAC_tx_ctrl.Current_state[3:0]