git.gag.com Git - debian/gnuradio/blob - usrp2/fpga/testbench/BOOTSTRAP.sav

   1 [size] 1400 971
   2 [pos] -1 -1
   3 *-26.028666 3485926000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
   4 @28
   5 u2_sim_top.cpld_clk
   6 u2_sim_top.cpld_detached
   7 u2_sim_top.cpld_din
   8 u2_sim_top.cpld_done
   9 u2_sim_top.cpld_start
  10 u2_sim_top.aux_clk
  11 u2_sim_top.clk_fpga
  12 u2_sim_top.clk_sel[1:0]
  13 u2_sim_top.clk_en[1:0]
  14 u2_sim_top.u2_basic.ram_loader_rst
  15 u2_sim_top.u2_basic.wb_rst
  16 u2_sim_top.u2_basic.sysctrl.POR
  17 u2_sim_top.u2_basic.sysctrl.ram_loader_done_i
  18 u2_sim_top.cpld_model.sclk
  19 u2_sim_top.cpld_model.start
  20 u2_sim_top.u2_basic.ram_loader.rst_i
  21 u2_sim_top.sen_clk
  22 u2_sim_top.sen_dac
  23 u2_sim_top.sclk
  24 @22
  25 u2_sim_top.u2_basic.shared_spi.wb_sel_i[3:0]
  26 u2_sim_top.u2_basic.shared_spi.wb_adr_i[4:0]
  27 u2_sim_top.u2_basic.shared_spi.wb_dat_i[31:0]
  28 @28
  29 u2_sim_top.u2_basic.shared_spi.wb_we_i
  30 u2_sim_top.u2_basic.shared_spi.wb_stb_i
  31 u2_sim_top.u2_basic.shared_spi.wb_ack_o
  32 @22
  33 u2_sim_top.u2_basic.shared_spi.ss_pad_o[7:0]
  34 u2_sim_top.u2_basic.shared_spi.ctrl[13:0]
  35 u2_sim_top.u2_basic.shared_spi.divider[15:0]
  36 u2_sim_top.u2_basic.shared_spi.char_len[6:0]
  37 u2_sim_top.u2_basic.shared_spi.ss[7:0]
  38 u2_sim_top.u2_basic.shared_spi.wb_dat_o[31:0]
  39 u2_sim_top.u2_basic.shared_spi.rx[127:0]
  40 @28
  41 u2_sim_top.u2_basic.control_lines.wb_stb_i
  42 u2_sim_top.u2_basic.control_lines.wb_we_i
  43 @22
  44 u2_sim_top.u2_basic.control_lines.wb_dat_i[31:0]
  45 u2_sim_top.u2_basic.control_lines.wb_dat_o[31:0]
  46 u2_sim_top.u2_basic.control_lines.wb_sel_i[3:0]
  47 @28
  48 u2_sim_top.u2_basic.control_lines.wb_cyc_i
  49 @22
  50 u2_sim_top.u2_basic.control_lines.wb_sel_i[3:0]
  51 @28
  52 u2_sim_top.clock_ready
  53 u2_sim_top.u2_basic.ram_loader.done_o
  54 u2_sim_top.u2_basic.dsp_rst
  55 u2_sim_top.u2_basic.ram_loader_rst
  56 u2_sim_top.u2_basic.wb_rst
  57 @22
  58 u2_sim_top.u2_basic.ID_ram.dwb_adr_i[12:0]
  59 @28
  60 u2_sim_top.u2_basic.aeMB.iwb_ack_i
  61 u2_sim_top.u2_basic.ram_loader_done
  62 @22
  63 u2_sim_top.u2_basic.iram_rd_adr[15:0]
  64 u2_sim_top.u2_basic.iram_rd_dat[31:0]
  65 @28
  66 u2_sim_top.u2_basic.iram_wr_we
  67 u2_sim_top.u2_basic.iram_wr_stb
  68 @22
  69 u2_sim_top.u2_basic.iram_wr_sel[3:0]
  70 u2_sim_top.u2_basic.iram_wr_dat[31:0]
  71 u2_sim_top.u2_basic.iram_wr_adr[15:0]
  72 @28
  73 u2_sim_top.u2_basic.ram_loader.ram_loader_done_o
  74 u2_sim_top.u2_basic.ID_ram.dwb_we_i
  75 u2_sim_top.u2_basic.ID_ram.iwb_we_i
  76 u2_sim_top.u2_basic.ram_loader.ram_we
  77 u2_sim_top.u2_basic.ram_loader.ram_we_q
  78 u2_sim_top.u2_basic.ram_loader.ram_we_s
  79 u2_sim_top.u2_basic.ram_loader.wb_ack_i
  80 u2_sim_top.u2_basic.ID_ram.iwb_ack_o
  81 u2_sim_top.u2_basic.ID_ram.iwb_stb_i
  82 u2_sim_top.u2_basic.ID_ram.wb_rst_i