2 module simple_gemac_wrapper
3 #(parameter RXFIFOSIZE=9,
4 parameter TXFIFOSIZE=6)
5 (input clk125, input reset,
7 output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD,
8 input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
10 // Client FIFO Interfaces
12 output [35:0] rx_f36_data, output rx_f36_src_rdy, input rx_f36_dst_rdy,
13 input [35:0] tx_f36_data, input tx_f36_src_rdy, output tx_f36_dst_rdy,
16 input wb_clk, input wb_rst, input wb_stb, input wb_cyc, output wb_ack, input wb_we,
17 input [7:0] wb_adr, input [31:0] wb_dat_i, output [31:0] wb_dat_o,
20 inout mdio, output mdc,
24 wire [7:0] rx_data, tx_data;
25 wire tx_clk, tx_valid, tx_error, tx_ack;
26 wire rx_clk, rx_valid, rx_error, rx_ack;
28 wire [47:0] ucast_addr, mcast_addr;
29 wire pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all;
31 wire pause_request_en, pause_respect_en;
32 wire [15:0] pause_time, pause_thresh, pause_time_req, rx_fifo_space;
34 wire tx_reset, rx_reset;
35 reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(tx_reset));
36 reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rx_reset));
38 simple_gemac simple_gemac
39 (.clk125(clk125), .reset(reset),
40 .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
41 .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
42 .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
43 .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
44 .pause_req(pause_req), .pause_time_req(pause_time_req),
45 .pause_respect_en(pause_respect_en),
46 .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
47 .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast),
48 .pass_pause(pass_pause), .pass_all(pass_all),
49 .rx_clk(rx_clk), .rx_data(rx_data),
50 .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
51 .tx_clk(tx_clk), .tx_data(tx_data),
52 .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)
55 simple_gemac_wb simple_gemac_wb
56 (.wb_clk(wb_clk), .wb_rst(wb_rst),
57 .wb_cyc(wb_cyc), .wb_stb(wb_stb), .wb_ack(wb_ack), .wb_we(wb_we),
58 .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
59 .mdio(mdio), .mdc(mdc),
60 .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
61 .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast),
62 .pass_pause(pass_pause), .pass_all(pass_all),
63 .pause_respect_en(pause_respect_en), .pause_request_en(pause_request_en),
64 .pause_time(pause_time), .pause_thresh(pause_thresh) );
67 wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
69 wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2;
70 wire rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n;
72 wire [7:0] rx_ll_data, rx_ll_data2;
74 wire [35:0] rx_f36_data_int1;
75 wire rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1;
78 (.clk(rx_clk), .reset(rx_reset), .clear(0),
79 .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
80 .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(), // error also encoded in sof/eof
81 .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
83 ll8_shortfifo rx_sfifo
84 (.clk(rx_clk), .reset(rx_reset), .clear(0),
85 .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
86 .error_i(0), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
87 .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
88 .error_o(), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
90 assign rx_ll_dst_rdy2 = ~rx_ll_dst_rdy2_n;
91 assign rx_ll_src_rdy2_n = ~rx_ll_src_rdy2;
92 assign rx_ll_sof2_n = ~rx_ll_sof2;
93 assign rx_ll_eof2_n = ~rx_ll_eof2;
95 ll8_to_fifo36 ll8_to_fifo36
96 (.clk(rx_clk), .reset(rx_reset), .clear(0),
97 .ll_data(rx_ll_data2), .ll_sof_n(rx_ll_sof2_n), .ll_eof_n(rx_ll_eof2_n),
98 .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n),
99 .f36_data(rx_f36_data_int1), .f36_src_rdy_o(rx_f36_src_rdy_int1), .f36_dst_rdy_i(rx_f36_dst_rdy_int1));
101 fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo
102 (.wclk(rx_clk), .datain(rx_f36_data_int1),
103 .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .space(rx_fifo_space),
104 .rclk(sys_clk), .dataout(rx_f36_data),
105 .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .occupied(), .arst(reset));
108 wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
109 wire tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2;
110 wire tx_ll_sof2_n, tx_ll_eof2_n, tx_ll_src_rdy2_n, tx_ll_dst_rdy2_n;
111 wire [7:0] tx_ll_data, tx_ll_data2;
112 wire [35:0] tx_f36_data_int1;
113 wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1;
115 fifo_2clock_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo
116 (.wclk(sys_clk), .datain(tx_f36_data),
117 .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(),
118 .rclk(tx_clk), .dataout(tx_f36_data_int1),
119 .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(), .arst(reset));
121 fifo36_to_ll8 fifo36_to_ll8
122 (.clk(tx_clk), .reset(tx_reset), .clear(clear),
123 .f36_data(tx_f36_data_int1), .f36_src_rdy_i(tx_f36_src_rdy_int1), .f36_dst_rdy_o(tx_f36_dst_rdy_int1),
124 .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n),
125 .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(tx_ll_dst_rdy2_n));
127 assign tx_ll_sof2 = ~tx_ll_sof2_n;
128 assign tx_ll_eof2 = ~tx_ll_eof2_n;
129 assign tx_ll_src_rdy2 = ~tx_ll_src_rdy2_n;
130 assign tx_ll_dst_rdy2_n = ~tx_ll_dst_rdy2;
132 ll8_shortfifo tx_sfifo
133 (.clk(tx_clk), .reset(tx_reset), .clear(clear),
134 .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
135 .error_i(0), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
136 .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
137 .error_o(), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
139 ll8_to_txmac ll8_to_txmac
140 (.clk(tx_clk), .reset(tx_reset), .clear(clear),
141 .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
142 .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
143 .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack));
145 flow_ctrl_rx flow_ctrl_rx
146 (.pause_request_en(pause_request_en), .pause_time(pause_time), .pause_thresh(pause_thresh),
147 .rx_clk(rx_clk), .rx_reset(rx_reset), .rx_fifo_space(rx_fifo_space),
148 .tx_clk(tx_clk), .tx_reset(tx_reset), .pause_req(pause_req), .pause_time_req(pause_time_req));
150 wire [31:0] debug_tx, debug_rx;
152 assign debug_tx = { { tx_ll_data },
153 { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy,
154 tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2 },
155 { tx_valid, tx_error, tx_ack, tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_data_int1[34:32]},
157 assign debug_rx = { { rx_ll_data },
158 { rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy,
159 rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2 },
160 { rx_valid, rx_error, rx_ack, rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1, rx_f36_data_int1[34:32]},
163 assign debug = debug_rx;
165 endmodule // simple_gemac_wrapper