2 module simple_gemac_wrapper
3 #(parameter RXFIFOSIZE=9,
4 parameter TXFIFOSIZE=6)
5 (input clk125, input reset,
7 output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD,
8 input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
10 // Client FIFO Interfaces
12 output [35:0] rx_f36_data, output rx_f36_src_rdy, input rx_f36_dst_rdy,
13 input [35:0] tx_f36_data, input tx_f36_src_rdy, output tx_f36_dst_rdy,
16 input wb_clk, input wb_rst, input wb_stb, input wb_cyc, output wb_ack, input wb_we,
17 input [7:0] wb_adr, input [31:0] wb_dat_i, output [31:0] wb_dat_o,
20 inout mdio, output mdc,
23 wire [7:0] rx_data, tx_data;
24 wire tx_clk, tx_valid, tx_error, tx_ack;
25 wire rx_clk, rx_valid, rx_error, rx_ack;
27 wire [47:0] ucast_addr, mcast_addr;
28 wire pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all;
29 wire pause_request_en, pause_respect_en;
30 wire [15:0] pause_time, pause_thresh, pause_time_req, rx_fifo_space;
32 wire tx_reset, rx_reset;
33 reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(tx_reset));
34 reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rx_reset));
36 simple_gemac simple_gemac
37 (.clk125(clk125), .reset(reset),
38 .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
39 .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
40 .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
41 .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
42 .pause_req(pause_req), .pause_time_req(pause_time_req),
43 .pause_respect_en(pause_respect_en),
44 .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
45 .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast),
46 .pass_pause(pass_pause), .pass_all(pass_all),
47 .rx_clk(rx_clk), .rx_data(rx_data),
48 .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
49 .tx_clk(tx_clk), .tx_data(tx_data),
50 .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)
53 simple_gemac_wb simple_gemac_wb
54 (.wb_clk(wb_clk), .wb_rst(wb_rst),
55 .wb_cyc(wb_cyc), .wb_stb(wb_stb), .wb_ack(wb_ack), .wb_we(wb_we),
56 .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
57 .mdio(mdio), .mdc(mdc),
58 .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
59 .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast),
60 .pass_pause(pass_pause), .pass_all(pass_all),
61 .pause_respect_en(pause_respect_en), .pause_request_en(pause_request_en),
62 .pause_time(pause_time), .pause_thresh(pause_thresh) );
65 wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
67 wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2;
68 wire rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n;
70 wire [7:0] rx_ll_data, rx_ll_data2;
72 wire [35:0] rx_f36_data_int1;
73 wire rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1;
76 (.clk(rx_clk), .reset(rx_reset), .clear(0),
77 .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
78 .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(rx_ll_error),
79 .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
81 ll8_shortfifo rx_sfifo
82 (.clk(rx_clk), .reset(rx_reset), .clear(0),
83 .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
84 .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
85 .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
86 .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
88 assign rx_ll_dst_rdy2 = ~rx_ll_dst_rdy2_n;
89 assign rx_ll_src_rdy2_n = ~rx_ll_src_rdy2;
90 assign rx_ll_sof2_n = ~rx_ll_sof2;
91 assign rx_ll_eof2_n = ~rx_ll_eof2;
93 ll8_to_fifo36 ll8_to_fifo36
94 (.clk(rx_clk), .reset(rx_reset), .clear(0),
95 .ll_data(rx_ll_data2), .ll_sof_n(rx_ll_sof2_n), .ll_eof_n(rx_ll_eof2_n),
96 .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n),
97 .f36_data(rx_f36_data_int1), .f36_src_rdy_o(rx_f36_src_rdy_int1), .f36_dst_rdy_i(rx_f36_dst_rdy_int1));
99 fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo
100 (.wclk(rx_clk), .datain(rx_f36_data_int1),
101 .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .space(rx_fifo_space),
102 .rclk(sys_clk), .dataout(rx_f36_data),
103 .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .occupied(), .arst(reset));
106 wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
107 wire tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2;
108 wire tx_ll_sof2_n, tx_ll_eof2_n, tx_ll_src_rdy2_n, tx_ll_dst_rdy2_n;
109 wire [7:0] tx_ll_data, tx_ll_data2;
110 wire [35:0] tx_f36_data_int1;
111 wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1;
113 fifo_2clock_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo
114 (.wclk(sys_clk), .datain(tx_f36_data),
115 .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(),
116 .rclk(tx_clk), .dataout(tx_f36_data_int1),
117 .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(), .arst(reset));
119 fifo36_to_ll8 fifo36_to_ll8
120 (.clk(tx_clk), .reset(tx_reset), .clear(clear),
121 .f36_data(tx_f36_data_int1), .f36_src_rdy_i(tx_f36_src_rdy_int1), .f36_dst_rdy_o(tx_f36_dst_rdy_int1),
122 .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n),
123 .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(tx_ll_dst_rdy2_n));
125 assign tx_ll_sof2 = ~tx_ll_sof2_n;
126 assign tx_ll_eof2 = ~tx_ll_eof2_n;
127 assign tx_ll_src_rdy2 = ~tx_ll_src_rdy2_n;
128 assign tx_ll_dst_rdy2_n = ~tx_ll_dst_rdy2;
130 ll8_shortfifo tx_sfifo
131 (.clk(tx_clk), .reset(tx_reset), .clear(clear),
132 .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
133 .error_i(0), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
134 .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
135 .error_o(), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
137 ll8_to_txmac ll8_to_txmac
138 (.clk(tx_clk), .reset(tx_reset), .clear(clear),
139 .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
140 .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
141 .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack));
143 flow_ctrl_rx flow_ctrl_rx
144 (.pause_request_en(pause_request_en), .pause_time(pause_time), .pause_thresh(pause_thresh),
145 .rx_clk(rx_clk), .rx_reset(rx_reset), .rx_fifo_space(rx_fifo_space),
146 .tx_clk(tx_clk), .tx_reset(tx_reset), .pause_req(pause_req), .pause_time_req(pause_time_req));
148 wire [31:0] debug_tx, debug_rx;
150 assign debug_tx = { { tx_ll_data },
151 { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy,
152 tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2 },
153 { tx_valid, tx_error, tx_ack, tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_data_int1[34:32]},
155 assign debug_rx = { { rx_ll_data },
156 { rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy,
157 rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2 },
158 { rx_valid, rx_error, rx_ack, rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1, rx_f36_data_int1[34:32]},
161 assign debug = debug_rx;
163 endmodule // simple_gemac_wrapper