git.gag.com Git - debian/gnuradio/blob - usrp2/fpga/simple_gemac/simple_gemac_tb.v

   1
   2
   3 module simple_gemac_tb;
   4 `include "eth_tasks.v"
   5
   6    reg clk = 0;
   7    reg reset = 1;
   8
   9    initial #1000 reset = 0;
  10    always #50 clk = ~clk;
  11
  12    wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;
  13    wire [7:0] GMII_RXD, GMII_TXD;
  14
  15    wire rx_valid, rx_error, rx_ack;
  16    wire tx_ack, tx_valid, tx_error;
  17
  18    wire [7:0] rx_data, tx_data;
  19
  20    reg [15:0] pause_time;
  21    reg pause_req      = 0;
  22
  23    wire GMII_RX_CLK   = GMII_GTX_CLK;
  24
  25    reg [7:0] FORCE_DAT_ERR = 0;
  26    reg FORCE_ERR = 0;
  27
  28    // Loopback
  29    assign GMII_RX_DV  = GMII_TX_EN;
  30    assign GMII_RX_ER  = GMII_TX_ER | FORCE_ERR;
  31    assign GMII_RXD    = GMII_TXD ^ FORCE_DAT_ERR;
  32
  33    simple_gemac simple_gemac
  34      (.clk125(clk),  .reset(reset),
  35       .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
  36       .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
  37       .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
  38       .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
  39       .pause_req(pause_req), .pause_time(pause_time), .pause_en(1),
  40       .rx_clk(rx_clk), .rx_data(rx_data),
  41       .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
  42       .tx_clk(tx_clk), .tx_data(tx_data),
  43       .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)
  44       );
  45
  46    wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
  47    wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2;
  48    reg rx_ll_dst_rdy2 = 1;
  49    wire [7:0] rx_ll_data, rx_ll_data2;
  50    wire rx_ll_error, rx_ll_error2;
  51
  52    rxmac_to_ll8 rx_adapt
  53      (.clk(clk), .reset(reset), .clear(0),
  54       .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
  55       .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(rx_ll_error),
  56       .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
  57
  58    ll8_shortfifo rx_sfifo
  59      (.clk(clk), .reset(reset), .clear(0),
  60       .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
  61       .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
  62       .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
  63       .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
  64
  65    wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
  66    reg tx_ll_sof2=0, tx_ll_eof2=0;
  67    reg tx_ll_src_rdy2 = 0;
  68    wire tx_ll_dst_rdy2;
  69    wire [7:0] tx_ll_data;
  70    reg [7:0] tx_ll_data2 = 0;
  71    wire tx_ll_error;
  72    wire tx_ll_error2 = 0;
  73
  74    ll8_shortfifo tx_sfifo
  75      (.clk(clk), .reset(reset), .clear(clear),
  76       .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
  77       .error_i(tx_ll_error2), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
  78       .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
  79       .error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
  80
  81    ll8_to_txmac ll8_to_txmac
  82      (.clk(clk), .reset(reset), .clear(clear),
  83       .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
  84       .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
  85       .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack));
  86
  87    initial $dumpfile("simple_gemac_tb.vcd");
  88    initial $dumpvars(0,simple_gemac_tb);
  89
  90    integer i;
  91    reg [7:0] pkt_rom[0:65535];
  92    reg [1023:0] ROMFile;
  93
  94    initial
  95      for (i=0;i<65536;i=i+1)
  96        pkt_rom[i] <= 8'h0;
  97
  98    initial
  99      begin
 100         @(negedge reset);
 101         repeat (10)
 102           @(posedge clk);
 103         SendFlowCtrl(16'h0007);  // Send flow control
 104         @(posedge clk);
 105         #30000;
 106         @(posedge clk);
 107         SendFlowCtrl(16'h0009);  // Increas flow control before it expires
 108         #10000;
 109         @(posedge clk);
 110         SendFlowCtrl(16'h0000);  // Cancel flow control before it expires
 111         @(posedge clk);
 112
 113         SendPacket_to_ll8(8'hAA,10);    // This packet gets dropped by the filters
 114         repeat (10)
 115           @(posedge clk);
 116
 117         SendPacketFromFile_ll8(60,0,0);  // The rest are valid packets
 118         repeat (10)
 119           @(posedge clk);
 120
 121         SendPacketFromFile_ll8(61,0,0);
 122         repeat (10)
 123           @(posedge clk);
 124         SendPacketFromFile_ll8(62,0,0);
 125         repeat (10)
 126           @(posedge clk);
 127         SendPacketFromFile_ll8(63,0,0);
 128         repeat (1)
 129           @(posedge clk);
 130         SendPacketFromFile_ll8(64,0,0);
 131         repeat (10)
 132           @(posedge clk);
 133         SendPacketFromFile_ll8(59,0,0);
 134         repeat (1)
 135           @(posedge clk);
 136         SendPacketFromFile_ll8(58,0,0);
 137         repeat (1)
 138           @(posedge clk);
 139         SendPacketFromFile_ll8(100,0,0);
 140         repeat (1)
 141           @(posedge clk);
 142         SendPacketFromFile_ll8(200,150,30);  // waiting 14 empties the fifo, 15 underruns
 143         repeat (1)
 144           @(posedge clk);
 145         SendPacketFromFile_ll8(100,0,30);
 146         #10000 $finish;
 147      end
 148
 149    // Force a CRC error
 150     initial
 151      begin
 152         #90000;
 153         @(posedge clk);
 154         FORCE_DAT_ERR <= 8'h10;
 155         @(posedge clk);
 156         FORCE_DAT_ERR <= 8'h00;
 157      end
 158
 159    // Force an RX_ER error (i.e. link loss)
 160    initial
 161      begin
 162         #116000;
 163         @(posedge clk);
 164         FORCE_ERR <= 1;
 165         @(posedge clk);
 166         FORCE_ERR <= 0;
 167      end
 168
 169    // Cause receive fifo to fill, causing an RX overrun
 170    initial
 171      begin
 172         #126000;
 173         @(posedge clk);
 174         rx_ll_dst_rdy2 <= 0;
 175         repeat (30)          // Repeat of 14 fills the shortfifo, but works.  15 overflows
 176           @(posedge clk);
 177         rx_ll_dst_rdy2 <= 1;
 178      end
 179
 180    // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun
 181    // Still need to test: CRC errors on Pause Frames
 182
 183    always @(posedge clk)
 184      if(rx_ll_src_rdy2 & rx_ll_dst_rdy2)
 185        begin
 186           if(rx_ll_sof2 & ~rx_ll_eof2)
 187             $display("RX-PKT-START %d",$time);
 188           $display("RX-PKT SOF %d EOF %d ERR%d DAT %x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2);
 189           if(rx_ll_eof2 & ~rx_ll_sof2)
 190             $display("RX-PKT-END %d",$time);
 191        end
 192
 193 endmodule // simple_gemac_tb