git.gag.com Git - debian/gnuradio/blob - usrp2/fpga/simple_gemac/simple_gemac_tb.v

   1
   2
   3 module simple_gemac_tb;
   4 `include "eth_tasks.v"
   5
   6    reg clk = 0;
   7    reg reset = 1;
   8
   9    initial #1000 reset = 0;
  10    always #50 clk = ~clk;
  11
  12    wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;
  13    wire [7:0] GMII_RXD, GMII_TXD;
  14
  15    wire rx_valid, rx_error, rx_ack;
  16    wire tx_ack, tx_valid, tx_error;
  17
  18    wire [7:0] rx_data, tx_data;
  19
  20    reg [15:0] pause_time;
  21    reg pause_req      = 0;
  22
  23    wire GMII_RX_CLK   = GMII_GTX_CLK;
  24
  25    reg [7:0] FORCE_DAT_ERR = 0;
  26    reg FORCE_ERR = 0;
  27
  28    // Loopback
  29    assign GMII_RX_DV  = GMII_TX_EN;
  30    assign GMII_RX_ER  = GMII_TX_ER | FORCE_ERR;
  31    assign GMII_RXD    = GMII_TXD ^ FORCE_DAT_ERR;
  32
  33    wire [47:0] ucast_addr = 48'hF1F2_F3F4_F5F6;
  34    wire [47:0] mcast_addr = 0;
  35    wire        pass_ucast  =1, pass_mcast=0, pass_bcast=1, pass_pause=0, pass_all=0;
  36
  37    simple_gemac simple_gemac
  38      (.clk125(clk),  .reset(reset),
  39       .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
  40       .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
  41       .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
  42       .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
  43       .pause_req(pause_req), .pause_time(pause_time), .pause_en(1),
  44       .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
  45       .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast),
  46       .pass_pause(pass_pause), .pass_all(pass_all),
  47       .rx_clk(rx_clk), .rx_data(rx_data),
  48       .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
  49       .tx_clk(tx_clk), .tx_data(tx_data),
  50       .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)
  51       );
  52
  53    wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
  54    wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2;
  55    reg rx_ll_dst_rdy2 = 1;
  56    wire [7:0] rx_ll_data, rx_ll_data2;
  57    wire rx_ll_error, rx_ll_error2;
  58
  59    rxmac_to_ll8 rx_adapt
  60      (.clk(clk), .reset(reset), .clear(0),
  61       .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
  62       .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(rx_ll_error),
  63       .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
  64
  65    ll8_shortfifo rx_sfifo
  66      (.clk(clk), .reset(reset), .clear(0),
  67       .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
  68       .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
  69       .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
  70       .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
  71
  72    wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
  73    reg tx_ll_sof2=0, tx_ll_eof2=0;
  74    reg tx_ll_src_rdy2 = 0;
  75    wire tx_ll_dst_rdy2;
  76    wire [7:0] tx_ll_data;
  77    reg [7:0] tx_ll_data2 = 0;
  78    wire tx_ll_error;
  79    wire tx_ll_error2 = 0;
  80
  81    ll8_shortfifo tx_sfifo
  82      (.clk(clk), .reset(reset), .clear(clear),
  83       .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
  84       .error_i(tx_ll_error2), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
  85       .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
  86       .error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
  87
  88    ll8_to_txmac ll8_to_txmac
  89      (.clk(clk), .reset(reset), .clear(clear),
  90       .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
  91       .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
  92       .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack));
  93
  94    initial $dumpfile("simple_gemac_tb.vcd");
  95    initial $dumpvars(0,simple_gemac_tb);
  96
  97    integer i;
  98    reg [7:0] pkt_rom[0:65535];
  99    reg [1023:0] ROMFile;
 100
 101    initial
 102      for (i=0;i<65536;i=i+1)
 103        pkt_rom[i] <= 8'h0;
 104
 105    initial
 106      begin
 107         @(negedge reset);
 108         repeat (10)
 109           @(posedge clk);
 110         SendFlowCtrl(16'h0007);  // Send flow control
 111         @(posedge clk);
 112         #30000;
 113         @(posedge clk);
 114         SendFlowCtrl(16'h0009);  // Increas flow control before it expires
 115         #10000;
 116         @(posedge clk);
 117         SendFlowCtrl(16'h0000);  // Cancel flow control before it expires
 118         @(posedge clk);
 119
 120         SendPacket_to_ll8(8'hAA,10);    // This packet gets dropped by the filters
 121         repeat (10)
 122           @(posedge clk);
 123
 124         SendPacketFromFile_ll8(60,0,0);  // The rest are valid packets
 125         repeat (10)
 126           @(posedge clk);
 127
 128         SendPacketFromFile_ll8(61,0,0);
 129         repeat (10)
 130           @(posedge clk);
 131         SendPacketFromFile_ll8(62,0,0);
 132         repeat (10)
 133           @(posedge clk);
 134         SendPacketFromFile_ll8(63,0,0);
 135         repeat (1)
 136           @(posedge clk);
 137         SendPacketFromFile_ll8(64,0,0);
 138         repeat (10)
 139           @(posedge clk);
 140         SendPacketFromFile_ll8(59,0,0);
 141         repeat (1)
 142           @(posedge clk);
 143         SendPacketFromFile_ll8(58,0,0);
 144         repeat (1)
 145           @(posedge clk);
 146         SendPacketFromFile_ll8(100,0,0);
 147         repeat (1)
 148           @(posedge clk);
 149         SendPacketFromFile_ll8(200,150,30);  // waiting 14 empties the fifo, 15 underruns
 150         repeat (1)
 151           @(posedge clk);
 152         SendPacketFromFile_ll8(100,0,30);
 153         #10000 $finish;
 154      end
 155
 156    // Force a CRC error
 157     initial
 158      begin
 159         #90000;
 160         @(posedge clk);
 161         FORCE_DAT_ERR <= 8'h10;
 162         @(posedge clk);
 163         FORCE_DAT_ERR <= 8'h00;
 164      end
 165
 166    // Force an RX_ER error (i.e. link loss)
 167    initial
 168      begin
 169         #116000;
 170         @(posedge clk);
 171         FORCE_ERR <= 1;
 172         @(posedge clk);
 173         FORCE_ERR <= 0;
 174      end
 175
 176    // Cause receive fifo to fill, causing an RX overrun
 177    initial
 178      begin
 179         #126000;
 180         @(posedge clk);
 181         rx_ll_dst_rdy2 <= 0;
 182         repeat (30)          // Repeat of 14 fills the shortfifo, but works.  15 overflows
 183           @(posedge clk);
 184         rx_ll_dst_rdy2 <= 1;
 185      end
 186
 187    // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun
 188    // Still need to test: CRC errors on Pause Frames
 189
 190    always @(posedge clk)
 191      if(rx_ll_src_rdy2 & rx_ll_dst_rdy2)
 192        begin
 193           if(rx_ll_sof2 & ~rx_ll_eof2)
 194             $display("RX-PKT-START %d",$time);
 195           $display("RX-PKT SOF %d EOF %d ERR%d DAT %x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2);
 196           if(rx_ll_eof2 & ~rx_ll_sof2)
 197             $display("RX-PKT-END %d",$time);
 198        end
 199
 200 endmodule // simple_gemac_tb