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   1
   2
   3 task SendFlowCtrl;
   4    input [15:0] fc_len;
   5    begin
   6       $display("Sending Flow Control, quanta = %d, time = %d", fc_len,$time);
   7       pause_time <= fc_len;
   8       @(posedge eth_clk);
   9       pause_req <= 1;
  10       @(posedge eth_clk);
  11       pause_req <= 0;
  12       $display("Sent Flow Control");
  13    end
  14 endtask // SendFlowCtrl
  15
  16 task SendPacket_to_fifo36;
  17    input [31:0] data_start;
  18    input [15:0] data_len;
  19    reg [15:0]   count;
  20    begin
  21       $display("Sending Packet Len=%d, %d", data_len, $time);
  22       count   <= 2;
  23       tx_f36_data <= {2'b0, 1'b0, 1'b1, data_start};
  24       tx_f36_src_rdy  <= 1;
  25       #1;
  26       while(count < data_len)
  27         begin
  28            while(~tx_f36_dst_rdy)
  29              @(posedge sys_clk);
  30            @(posedge sys_clk);
  31            tx_f36_data[31:0] = tx_f36_data[31:0] + 32'h0101_0101;
  32            count           = count + 4;
  33            tx_f36_data[32] <= 0;
  34         end
  35       tx_f36_data[33]     <= 1;
  36       while(~tx_f36_dst_rdy)
  37         @(posedge sys_clk);
  38       @(posedge sys_clk);
  39       tx_f36_src_rdy <= 0;
  40    end
  41 endtask // SendPacket_to_fifo36
  42
  43 /*
  44 task Waiter;
  45    input [31:0] wait_length;
  46    begin
  47       tx_ll_src_rdy2 <= 0;
  48       repeat(wait_length)
  49         @(posedge clk);
  50       tx_ll_src_rdy2 <= 1;
  51    end
  52 endtask // Waiter
  53 */
  54
  55 /*
  56 task SendPacketFromFile_f36;
  57    input [31:0] data_len;
  58    input [31:0] wait_length;
  59    input [31:0] wait_time;
  60
  61    integer count;
  62    begin
  63       $display("Sending Packet From File to LL8 Len=%d, %d",data_len,$time);
  64       $readmemh("test_packet.mem",pkt_rom );
  65
  66       while(~tx_f36_dst_rdy)
  67         @(posedge clk);
  68       tx_f36_data <= pkt_rom[0];
  69       tx_f36_src_rdy <= 1;
  70       tx_f36_eof     <= 0;
  71       @(posedge clk);
  72
  73       for(i=1;i<data_len-1;i=i+1)
  74         begin
  75            while(~tx_ll_dst_rdy2)
  76              @(posedge clk);
  77            tx_ll_data2 <= pkt_rom[i];
  78            tx_ll_sof2  <= 0;
  79            @(posedge clk);
  80 //         if(i==wait_time)
  81 //           Waiter(wait_length);
  82         end
  83
  84       while(~tx_ll_dst_rdy2)
  85         @(posedge clk);
  86       tx_ll_eof2 <= 1;
  87       tx_ll_data2 <= pkt_rom[data_len-1];
  88       @(posedge clk);
  89       tx_ll_src_rdy2 <= 0;
  90    end
  91 endtask
  92 */