4 // LS-Byte is sent first, MS-Byte is second
6 // K0.0 000-00000 Error detected
7 // K31.7 111-11111 Loss of input signal
11 // K28.1 001-11100 Alternate COMMA?
15 // K28.5 101-11100 Standard COMMA?
17 // K28.7 111-11100 Bad COMMA?
24 #(parameter FIFOSIZE = 9)
30 output reg [15:0] ser_t,
34 // TX Stream Interface
35 input [31:0] rd_dat_i,
36 input [3:0] rd_flags_i,
40 // Flow control interface
47 output [15:0] fifo_occupied,
55 localparam K_COMMA = 8'b101_11100; // 0xBC K28.5
56 localparam K_IDLE = 8'b001_11100; // 0x3C K28.1
57 localparam K_PKT_START = 8'b110_11100; // 0xDC K28.6
58 localparam K_PKT_END = 8'b100_11100; // 0x9C K28.4
59 localparam K_XON = 8'b010_11100; // 0x5C K28.2
60 localparam K_XOFF = 8'b011_11100; // 0x7C K28.3
61 localparam K_LOS = 8'b111_11111; // 0xFF K31.7
62 localparam K_ERROR = 8'b000_00000; // 0x00 K00.0
63 localparam D_56 = 8'b110_00101; // 0xC5 D05.6
64 assign ser_tx_clk = clk;
66 localparam IDLE = 3'd0;
67 localparam RUN1 = 3'd1;
68 localparam RUN2 = 3'd2;
69 localparam DONE = 3'd3;
70 localparam SENDCRC = 3'd4;
71 localparam WAIT = 3'd5;
79 // Internal FIFO, size 9 is 2K, size 10 is 4K bytes
83 wire rd_sop_i = rd_flags_i[0];
84 wire rd_eop_i = rd_flags_i[1];
85 wire [1:0] rd_occ_i = rd_flags_i[3:2]; // Unused
87 wire have_data, empty;
88 fifo_cascade #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo
89 (.clk(clk),.reset(rst),.clear(0),
90 .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .src_rdy_i(rd_ready_i), .dst_rdy_o(rd_ready_o),
91 .dataout({sop_o,eop_o,data_o}), .dst_rdy_i(read), .src_rdy_o(have_data),
92 .space(), .occupied(fifo_occupied) );
94 assign fifo_full = ~rd_ready_o;
95 assign empty = ~have_data;
96 assign fifo_empty = empty;
98 // FIXME Implement flow control
99 reg [15:0] second_word;
102 assign read = (~send_xon & ~send_xoff & (state==RUN2)) | ((state==IDLE) & ~empty & ~sop_o);
103 assign sent = send_xon | send_xoff;
104 // 2nd half of above probably not necessary. Just in case we get junk between packets
106 always @(posedge clk)
111 {ser_tkmsb,ser_tklsb,ser_t} <= 18'd0;
112 //{2'b10,K_COMMA,K_COMMA};
113 // make tkmsb and tklsb different so they can go in IOFFs
117 {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_XON,K_XON};
119 {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_XOFF,K_XOFF};
124 if(sop_o & ~empty & ~inhibit_tx)
126 {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_PKT_START,K_PKT_START};
130 {ser_tkmsb,ser_tklsb,ser_t} <= {2'b10,K_COMMA,D_56};
134 if(empty | inhibit_tx)
135 {ser_tkmsb,ser_tklsb,ser_t} <= {2'b10,K_COMMA,D_56};
138 {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,data_o[15:0]};
144 {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,data_o[31:16]};
152 {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_PKT_END,K_PKT_END};
157 {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,CRC};
163 {ser_tkmsb,ser_tklsb,ser_t} <= {2'b10,K_COMMA,D_56};
167 wait_count <= wait_count - 1;
171 endcase // case(state)
173 always @(posedge clk)
176 else if(state == IDLE)
178 else if( (~empty & ~inhibit_tx & (state==RUN1)) || (state==RUN2) )
181 CRC16_D16 crc_blk( (state==RUN1) ? data_o[15:0] : data_o[31:16], CRC, nextCRC);
183 assign debug = { 28'd0, state[2:0] };
185 endmodule // serdes_tx