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copied over from other project
[debian/gnuradio]
/
usrp2
/
fpga
/
serdes
/
serdes_fc_tx.v
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module serdes_fc_tx
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(input clk, input rst,
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input xon_rcvd, input xoff_rcvd, output reg inhibit_tx);
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// XOFF means stop sending, XON means start sending
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// clock domain stuff happens elsewhere, everything here is on main clk
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reg [15:0] state;
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always @(posedge clk)
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if(rst)
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state <= 0;
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else if(xoff_rcvd)
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state <= 255;
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else if(xon_rcvd)
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state <= 0;
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else if(state !=0)
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state <= state - 1;
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always @(posedge clk)
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inhibit_tx <= (state != 0);
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endmodule // serdes_fc_tx