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   1
   2 // SERDES TX and RX along with all flow control logic
   3
   4 module serdes
   5   #(parameter TXFIFOSIZE = 9,
   6     parameter RXFIFOSIZE = 9)
   7     (input clk, input rst,
   8      // TX side
   9      output ser_tx_clk, output [15:0] ser_t, output ser_tklsb, output ser_tkmsb,
  10      input [31:0] rd_dat_i, output rd_read_o, output rd_done_o, output rd_error_o,
  11      input rd_sop_i, input rd_eop_i,
  12      // RX side
  13      input ser_rx_clk, input [15:0] ser_r, input ser_rklsb, input ser_rkmsb,
  14      output [31:0] wr_dat_o, output wr_write_o, output wr_done_o, output wr_error_o,
  15      input wr_ready_i, input wr_full_i,
  16
  17      output [15:0] tx_occupied, output tx_full, output tx_empty,
  18      output [15:0] rx_occupied, output rx_full, output rx_empty,
  19
  20      output serdes_link_up,
  21
  22      output [31:0] debug0,
  23      output [31:0] debug1);
  24
  25    wire [15:0] fifo_space;
  26    wire        xon_rcvd, xoff_rcvd, inhibit_tx, send_xon, send_xoff, sent;
  27    wire [31:0] debug_rx, debug_tx;
  28
  29    serdes_tx #(.FIFOSIZE(TXFIFOSIZE)) serdes_tx
  30      (.clk(clk),.rst(rst),
  31       .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
  32       .rd_dat_i(rd_dat_i),.rd_read_o(rd_read_o),.rd_done_o(rd_done_o),.rd_error_o(rd_error_o),
  33       .rd_sop_i(rd_sop_i),.rd_eop_i(rd_eop_i),
  34       .inhibit_tx(inhibit_tx), .send_xon(send_xon), .send_xoff(send_xoff), .sent(sent),
  35       .fifo_occupied(tx_occupied),.fifo_full(tx_full),.fifo_empty(tx_empty),
  36       .debug(debug_tx) );
  37
  38    serdes_rx #(.FIFOSIZE(RXFIFOSIZE)) serdes_rx
  39      (.clk(clk),.rst(rst),
  40       .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
  41       .wr_dat_o(wr_dat_o),.wr_write_o(wr_write_o),.wr_done_o(wr_done_o),.wr_error_o(wr_error_o),
  42       .wr_ready_i(wr_ready_i),.wr_full_i(wr_full_i),
  43       .fifo_space(fifo_space), .xon_rcvd(xon_rcvd), .xoff_rcvd(xoff_rcvd),
  44       .fifo_occupied(rx_occupied),.fifo_full(rx_full),.fifo_empty(rx_empty),
  45       .serdes_link_up(serdes_link_up), .debug(debug_rx) );
  46
  47    serdes_fc_tx serdes_fc_tx
  48      (.clk(clk),.rst(rst),
  49       .xon_rcvd(xon_rcvd),.xoff_rcvd(xoff_rcvd),.inhibit_tx(inhibit_tx) );
  50
  51    serdes_fc_rx #(.LWMARK(32),.HWMARK(128)) serdes_fc_rx
  52      (.clk(clk),.rst(rst),
  53       .fifo_space(fifo_space),.send_xon(send_xon),.send_xoff(send_xoff),.sent(sent) );
  54
  55    //assign      debug = { fifo_space, send_xon, send_xoff, debug_rx[13:0] };
  56    //assign      debug = debug_rx;
  57
  58    assign      debug0 = { { debug_tx[3:0] /* xfer_active,state[2:0] */, rd_read_o, rd_done_o, rd_sop_i, rd_eop_i },
  59                           { debug_tx[5:4] /* full,empty */ , inhibit_tx, send_xon, send_xoff, sent, ser_tkmsb, ser_tklsb},
  60                           { ser_t[15:8] },
  61                           { ser_t[7:0] } };
  62
  63    assign      debug1 = { { debug_rx[7:0] }, /*  odd,xfer_active,sop_i,eop_i,error_i,state[2:0] */
  64                           { wr_write_o, wr_error_o, wr_ready_i, wr_done_o,  xon_rcvd, xoff_rcvd, ser_rkmsb, ser_rklsb },
  65                           { ser_r[15:8] },
  66                           { ser_r[7:0] } };
  67 endmodule // serdes