3 // Parameters for instantiation
4 parameter clocks = 9'd2 ; // Number of clocks per input
5 parameter decim = 1 ; // Sets the filter to decimate
6 parameter rate = 2 ; // Sets the decimation rate
12 reg signed [17:0] data_in ;
14 wire signed [17:0] data_out ;
18 $dumpfile("hb_dec_tb.vcd");
19 $dumpvars(0,hb_dec_tb);
23 initial clock = 1'b0 ;
24 always #5 clock <= ~clock ;
26 // Come out of reset after a while
27 initial reset = 1'b1 ;
28 initial #1000 reset = 1'b0 ;
30 // Enable the entire system
31 initial enable = 1'b1 ;
43 .strobe_in ( strobe_in ),
45 .strobe_out ( strobe_out ),
46 .data_out ( data_out )
51 small_hb_dec #(.WIDTH(18)) uut
52 (.clk(clock),.rst(reset),.bypass(0),.stb_in(strobe_in),.data_in(data_in),
53 .stb_out(strobe_out),.data_out(data_out) );
55 integer i, ri, ro, infile, outfile ;
57 always @(posedge clock)
65 infile = $fopen("input.dat","r") ;
66 outfile = $fopen("output.dat","r") ;
67 $timeformat(-9, 2, " ns", 10) ;
71 reg signed [17:0] compare ;
80 // Wait for reset to go away
83 // While we're still simulating ...
84 while( !endofsim ) begin
86 // Write the input from the file or 0 if EOF...
87 @( posedge clock ) begin
91 ri = $fscanf( infile, "%d", data_in ) ;
96 // Clocked in - set the strobe to 0 if the number of
97 // clocks per sample is greater than 1
98 if( clocks > 1 ) begin
99 @(posedge clock) begin
103 // Wait for the specified number of cycles
104 for( i = 0 ; i < (clocks-2) ; i = i + 1 ) begin
105 @(posedge clock) #1 ;
110 // Print out the number of errors that occured
112 $display( "FAILED: %d errors during simulation", noe ) ;
114 $display( "PASSED: Simulation successful" ) ;
119 // Output comparison of simulated values versus known good values
120 always @ (posedge clock) begin
124 if( !$feof(outfile) ) begin
125 if( strobe_out ) begin
126 ro = $fscanf( outfile, "%d\n", compare ) ;
127 if( compare != data_out ) begin
128 //$display( "%t: %d != %d", $realtime, data_out, compare ) ;
133 // Signal end of simulation when no more outputs
139 endmodule // hb_dec_tb