work in progress
[debian/gnuradio] / usrp2 / fpga / sdr_lib / rx_dcoffset_tb.v
1
2 `timescale 1ns/1ns
3 module rx_dcoffset_tb();
4    
5    reg clk, rst;
6
7    initial rst = 1;
8    initial #1000 rst = 0;
9    initial clk = 0;
10    always #5 clk = ~clk;
11    
12    initial $dumpfile("rx_dcoffset_tb.vcd");
13    initial $dumpvars(0,rx_dcoffset_tb);
14
15    reg [13:0] adc_in = 7;
16    wire [13:0] adc_out;
17
18    always @(posedge clk)
19      $display("%d\t%d",adc_in,adc_out);
20    
21    rx_dcoffset #(.WIDTH(14),.ADDR(0))
22      rx_dcoffset(.clk(clk),.rst(rst),.set_stb(0),.set_addr(0),.set_data(0),
23                  .adc_in(adc_in),.adc_out(adc_out));
24    
25 endmodule // longfifo_tb