git.gag.com Git - debian/gnuradio/blob - usrp2/fpga/sdr_lib/hb_tb.v

   1
   2 module hb_tb();
   3
   4    localparam SWIDTH = 17;
   5    localparam CWIDTH = 18;
   6    localparam TWIDTH = 20;
   7    localparam ACC_WIDTH = 40;
   8
   9    reg clk = 0, rst = 1;
  10    wire strobe_in, strobe_out;
  11    reg [SWIDTH-1:0] sample_in;
  12    wire signed [SWIDTH:0] sample_out;
  13
  14    reg         set_stb;
  15    reg [7:0]   set_addr;
  16    reg [31:0]  set_data;
  17
  18    localparam  DECIM = 3;
  19
  20    initial $dumpfile("hb_tb.vcd");
  21    initial $dumpvars(0,hb_tb);
  22
  23    always #5 clk <= ~clk;
  24    initial
  25      begin
  26         @(posedge clk);
  27         @(negedge clk);
  28         rst <= 0;
  29      end
  30
  31    reg [7:0] stb_counter;
  32    always @(posedge clk)
  33      if(rst)
  34        stb_counter <= 0;
  35      else
  36        if(stb_counter == 0)
  37          stb_counter <= DECIM;
  38        else
  39          stb_counter <= stb_counter - 1;
  40    assign    strobe_in = (stb_counter == 0);
  41
  42    hb_decim #(.SWIDTH(SWIDTH),.CWIDTH(CWIDTH),
  43               .TWIDTH(TWIDTH),.ACC_WIDTH(ACC_WIDTH)) hb_decim
  44      (.clk(clk), .rst(rst),
  45       .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
  46       .sample_in(sample_in),
  47       .strobe_in(strobe_in),
  48       .sample_out(sample_out),
  49       .strobe_out(strobe_out)
  50       );
  51
  52    initial
  53      begin : load_coeffs
  54         @(negedge rst);
  55         @(posedge clk);
  56         set_addr <= 124;   // load coeffs
  57         set_stb <= 1;
  58         set_data <= -18'd49;
  59         @(posedge clk);
  60         set_data <= 18'd165;
  61         @(posedge clk);
  62         set_data <= -18'd412;
  63         @(posedge clk);
  64         set_data <= 18'd873;
  65         @(posedge clk);
  66         set_data <= -18'd1681;
  67         @(posedge clk);
  68         set_data <= 18'd3135;
  69         @(posedge clk);
  70         set_data <= -18'd6282;
  71         @(posedge clk);
  72         set_data <= 18'd20628;
  73         @(posedge clk);
  74         set_addr <=125;  // load table
  75         // { stb_out, accum, load_accum, done, even_addr, odd_addr_a, odd_addr_b, coeff_addr }
  76         set_data <= {1'b1,1'b1,1'b0,1'b1,4'd15,4'd15,4'd0,4'd0}; // Phase 8
  77         @(posedge clk);
  78         set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd14,4'd1,4'd1}; // Phase 7
  79         @(posedge clk);
  80         set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd13,4'd2,4'd2}; // Phase 6
  81         @(posedge clk);
  82         set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd12,4'd3,4'd3}; // Phase 5
  83         @(posedge clk);
  84         set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd11,4'd4,4'd4}; // Phase 4
  85         @(posedge clk);
  86         set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd10,4'd5,4'd5}; // Phase 3
  87         @(posedge clk);
  88         set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd9,4'd6,4'd6};  // Phase 2
  89         @(posedge clk);
  90         set_data <= {1'b0,1'b0,1'b1,1'b0,4'd15,4'd8,4'd7,4'd7};   // Phase 1
  91         @(posedge clk);
  92         set_data <= {1'b0,1'b0,1'b0,1'b0,4'd15,4'd8,4'd7,4'd7};   // Phase 0
  93         @(posedge clk);
  94         set_stb <= 0;
  95      end // block: load_coeffs
  96
  97    initial
  98      begin
  99         sample_in <= 0;
 100         repeat(40)
 101           @(posedge strobe_in);
 102         $display("EVEN");
 103         sample_in <= 0;
 104         repeat(10)
 105           @(posedge strobe_in);
 106         sample_in <= 1;
 107         @(posedge strobe_in);
 108         sample_in <= 0;
 109         repeat(40)
 110           @(posedge strobe_in);
 111         sample_in <= 1;
 112         repeat(40)
 113           @(posedge strobe_in);
 114         sample_in <= 0;
 115         repeat(60)
 116           @(posedge strobe_in);
 117         sample_in <= 1;
 118         repeat(2)
 119           @(posedge strobe_in);
 120         sample_in <= 0;
 121         repeat(60)
 122           @(posedge strobe_in);
 123         $display("ODD");
 124         sample_in <= 0;
 125         repeat(10)
 126           @(posedge strobe_in);
 127         sample_in <= 1;
 128         @(posedge strobe_in);
 129         sample_in <= 0;
 130         repeat(40)
 131           @(posedge strobe_in);
 132         sample_in <= 1;
 133         repeat(40)
 134           @(posedge strobe_in);
 135         sample_in <= 0;
 136         repeat(60)
 137           @(posedge strobe_in);
 138         sample_in <= 1;
 139         repeat(2)
 140           @(posedge strobe_in);
 141         sample_in <= 0;
 142         repeat(60)
 143           @(posedge strobe_in);
 144         $finish;
 145      end
 146
 147    always @(posedge clk)
 148      if(strobe_in)
 149        $display(sample_in);
 150
 151       always @(posedge clk)
 152         if(strobe_out)
 153           $display("\t",sample_out);
 154
 155 endmodule // hb_tb