2 `define DSP_CORE_TX_BASE 128
6 input set_stb, input [7:0] set_addr, input [31:0] set_data,
8 output reg [15:0] dac_a,
9 output reg [15:0] dac_b,
18 wire [15:0] i, q, scale_i, scale_q;
19 wire [31:0] phase_inc;
21 wire [7:0] interp_rate;
22 wire [3:0] dacmux_a, dacmux_b;
23 wire enable_hb1, enable_hb2;
25 setting_reg #(.my_addr(`DSP_CORE_TX_BASE+0)) sr_0
26 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
27 .in(set_data),.out(phase_inc),.changed());
29 setting_reg #(.my_addr(`DSP_CORE_TX_BASE+1)) sr_1
30 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
31 .in(set_data),.out({scale_i,scale_q}),.changed());
33 setting_reg #(.my_addr(`DSP_CORE_TX_BASE+2)) sr_2
34 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
35 .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed());
37 setting_reg #(.my_addr(`DSP_CORE_TX_BASE+4)) sr_4
38 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
39 .in(set_data),.out({dacmux_b,dacmux_a}),.changed());
41 // Strobes are all now delayed by 1 cycle for timing reasons
42 wire strobe_cic_pre, strobe_hb1_pre, strobe_hb2_pre;
47 cic_strober #(.WIDTH(8))
48 cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate),
49 .strobe_fast(1),.strobe_slow(strobe_cic_pre) );
50 cic_strober #(.WIDTH(2))
51 hb2_strober(.clock(clk),.reset(rst),.enable(run),.rate(enable_hb2 ? 2 : 1),
52 .strobe_fast(strobe_cic_pre),.strobe_slow(strobe_hb2_pre) );
53 cic_strober #(.WIDTH(2))
54 hb1_strober(.clock(clk),.reset(rst),.enable(run),.rate(enable_hb1 ? 2 : 1),
55 .strobe_fast(strobe_hb2_pre),.strobe_slow(strobe_hb1_pre) );
57 always @(posedge clk) strobe_hb1 <= strobe_hb1_pre;
58 always @(posedge clk) strobe_hb2 <= strobe_hb2_pre;
59 always @(posedge clk) strobe_cic <= strobe_cic_pre;
68 phase <= phase + phase_inc;
70 wire signed [17:0] da, db;
71 wire signed [35:0] prod_i, prod_q;
73 wire [17:0] bb_i = {sample[31:16],2'b0};
74 wire [17:0] bb_q = {sample[15:0],2'b0};
75 wire [17:0] i_interp, q_interp;
77 wire [17:0] hb1_i, hb1_q, hb2_i, hb2_q;
79 wire [7:0] cpo = enable_hb2 ? ({interp_rate,1'b0}) : interp_rate;
80 // Note that max CIC rate is 128, which would give an overflow on cpo if enable_hb2 is true,
81 // but the default case inside hb_interp handles this
83 hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(24)) hb_interp_i
84 (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in(bb_i),.stb_out(strobe_hb2),.data_out(hb1_i));
85 hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(24)) hb_interp_q
86 (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in(bb_q),.stb_out(strobe_hb2),.data_out(hb1_q));
88 small_hb_int #(.WIDTH(18)) small_hb_interp_i
89 (.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_i),
90 .output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_i));
91 small_hb_int #(.WIDTH(18)) small_hb_interp_q
92 (.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_q),
93 .output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_q));
95 cic_interp #(.bw(18),.N(4),.log2_of_max_rate(7))
96 cic_interp_i(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate),
97 .strobe_in(strobe_cic),.strobe_out(1),
98 .signal_in(hb2_i),.signal_out(i_interp));
100 cic_interp #(.bw(18),.N(4),.log2_of_max_rate(7))
101 cic_interp_q(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate),
102 .strobe_in(strobe_cic),.strobe_out(1),
103 .signal_in(hb2_q),.signal_out(q_interp));
105 assign strobe = strobe_hb1;
107 localparam cwidth = 24; // was 18
108 localparam zwidth = 24; // was 16
110 wire [cwidth-1:0] da_c, db_c;
112 cordic_z24 #(.bitwidth(cwidth))
113 cordic(.clock(clk), .reset(rst), .enable(run),
114 .xi({i_interp,{(cwidth-18){1'b0}}}),.yi({q_interp,{(cwidth-18){1'b0}}}),
115 .zi(phase[31:32-zwidth]),
116 .xo(da_c),.yo(db_c),.zo() );
118 MULT18X18S MULT18X18S_inst
119 (.P(prod_i), // 36-bit multiplier output
120 .A(da_c[cwidth-1:cwidth-18]), // 18-bit multiplier input
121 .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input
122 .C(clk), // Clock input
123 .CE(1), // Clock enable input
124 .R(rst) // Synchronous reset input
127 MULT18X18S MULT18X18S_inst_2
128 (.P(prod_q), // 36-bit multiplier output
129 .A(db_c[cwidth-1:cwidth-18]), // 18-bit multiplier input
130 .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input
131 .C(clk), // Clock input
132 .CE(1), // Clock enable input
133 .R(rst) // Synchronous reset input
136 always @(posedge clk)
138 0 : dac_a <= prod_i[28:13];
139 1 : dac_a <= prod_q[28:13];
140 default : dac_a <= 0;
141 endcase // case(dacmux_a)
143 always @(posedge clk)
145 0 : dac_b <= prod_i[28:13];
146 1 : dac_b <= prod_q[28:13];
147 default : dac_b <= 0;
148 endcase // case(dacmux_b)
150 assign debug = {strobe_cic, strobe_hb1, strobe_hb2,run};
152 endmodule // dsp_core