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   1 // -*- verilog -*-
   2 //
   3 //  USRP - Universal Software Radio Peripheral
   4 //
   5 //  Copyright (C) 2003 Matt Ettus
   6 //
   7 //  This program is free software; you can redistribute it and/or modify
   8 //  it under the terms of the GNU General Public License as published by
   9 //  the Free Software Foundation; either version 2 of the License, or
  10 //  (at your option) any later version.
  11 //
  12 //  This program is distributed in the hope that it will be useful,
  13 //  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 //  GNU General Public License for more details.
  16 //
  17 //  You should have received a copy of the GNU General Public License
  18 //  along with this program; if not, write to the Free Software
  19 //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
  20 //
  21
  22
  23 module cic_decim
  24   #(parameter bw = 16, parameter N = 4, parameter log2_of_max_rate = 7)
  25     (input clock,
  26      input reset,
  27      input enable,
  28      input [7:0] rate,
  29      input strobe_in,
  30      input strobe_out,
  31      input [bw-1:0] signal_in,
  32      output reg [bw-1:0] signal_out);
  33
  34    localparam        maxbitgain = N * log2_of_max_rate;
  35
  36    wire [bw+maxbitgain-1:0] signal_in_ext;
  37    reg [bw+maxbitgain-1:0]  integrator [0:N-1];
  38    reg [bw+maxbitgain-1:0]  differentiator [0:N-1];
  39    reg [bw+maxbitgain-1:0]  pipeline [0:N-1];
  40    reg [bw+maxbitgain-1:0]  sampler;
  41
  42    integer                  i;
  43
  44    sign_extend #(bw,bw+maxbitgain)
  45      ext_input (.in(signal_in),.out(signal_in_ext));
  46
  47    always @(posedge clock)
  48      if(reset)
  49        for(i=0;i<N;i=i+1)
  50          integrator[i] <= 0;
  51      else if (enable && strobe_in)
  52        begin
  53           integrator[0] <= integrator[0] + signal_in_ext;
  54           for(i=1;i<N;i=i+1)
  55             integrator[i] <= integrator[i] + integrator[i-1];
  56        end
  57
  58    always @(posedge clock)
  59      if(reset)
  60        begin
  61           sampler <= 0;
  62           for(i=0;i<N;i=i+1)
  63             begin
  64                pipeline[i] <= 0;
  65                differentiator[i] <= 0;
  66             end
  67        end
  68      else if (enable && strobe_out)
  69        begin
  70           sampler <= integrator[N-1];
  71           differentiator[0] <= sampler;
  72           pipeline[0] <= sampler - differentiator[0];
  73           for(i=1;i<N;i=i+1)
  74             begin
  75                differentiator[i] <= pipeline[i-1];
  76                pipeline[i] <= pipeline[i-1] - differentiator[i];
  77             end
  78        end // if (enable && strobe_out)
  79
  80    wire [bw-1:0] signal_out_unreg;
  81
  82    cic_dec_shifter #(bw)
  83      cic_dec_shifter(rate,pipeline[N-1],signal_out_unreg);
  84
  85    always @(posedge clock)
  86      signal_out <= signal_out_unreg;
  87
  88 endmodule // cic_decim