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   1
   2 module add2_and_round_reg
   3   #(parameter WIDTH=16)
   4     (input clk,
   5      input [WIDTH-1:0] in1,
   6      input [WIDTH-1:0] in2,
   7      output reg [WIDTH-1:0] sum);
   8
   9    wire [WIDTH-1:0] sum_int;
  10
  11    add2_and_round #(.WIDTH(WIDTH)) add2_n_rnd (.in1(in1),.in2(in2),.sum(sum_int));
  12
  13    always @(posedge clk)
  14      sum <= sum_int;
  15
  16 endmodule // add2_and_round_reg