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   1 /////////////////////////////////////////////////////////////////////
   2 ////                                                             ////
   3 ////  WISHBONE Master Model                                      ////
   4 ////                                                             ////
   5 ////                                                             ////
   6 ////  Author: Rudolf Usselmann                                   ////
   7 ////          rudi@asics.ws                                      ////
   8 ////                                                             ////
   9 ////                                                             ////
  10 /////////////////////////////////////////////////////////////////////
  11 ////                                                             ////
  12 //// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
  13 ////                         www.asics.ws                        ////
  14 ////                         rudi@asics.ws                       ////
  15 ////                                                             ////
  16 //// This source file may be used and distributed without        ////
  17 //// restriction provided that this copyright statement is not   ////
  18 //// removed from the file and that any derivative work contains ////
  19 //// the original copyright notice and the associated disclaimer.////
  20 ////                                                             ////
  21 ////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
  22 //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
  23 //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
  24 //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
  25 //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
  26 //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
  27 //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
  28 //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
  29 //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
  30 //// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
  31 //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
  32 //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
  33 //// POSSIBILITY OF SUCH DAMAGE.                                 ////
  34 ////                                                             ////
  35 /////////////////////////////////////////////////////////////////////
  36
  37 //  CVS Log
  38 //
  39 //  $Id: wb_mast_model.v,v 1.1.1.1 2003/04/19 08:40:15 johny Exp $
  40 //
  41 //  $Date: 2003/04/19 08:40:15 $
  42 //  $Revision: 1.1.1.1 $
  43 //  $Author: johny $
  44 //  $Locker:  $
  45 //  $State: Exp $
  46 //
  47 // Change History:
  48 //               $Log: wb_mast_model.v,v $
  49 //               Revision 1.1.1.1  2003/04/19 08:40:15  johny
  50 //               no message
  51 //
  52 //               Revision 1.2  2002/10/03 05:40:03  rudi
  53 //               Fixed a minor bug in parameter passing, updated headers and specification.
  54 //
  55 //               Revision 1.1.1.1  2001/10/19 11:04:23  rudi
  56 //               WISHBONE CONMAX IP Core
  57 //
  58 //
  59 //
  60 //
  61 //
  62
  63 `include "wb_model_defines.v"
  64
  65 module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
  66
  67 input           clk, rst;
  68 output  [31:0]  adr;
  69 input   [31:0]  din;
  70 output  [31:0]  dout;
  71 output          cyc, stb;
  72 output  [3:0]   sel;
  73 output          we;
  74 input           ack, err, rty;
  75
  76 ////////////////////////////////////////////////////////////////////
  77 //
  78 // Local Wires
  79 //
  80
  81 parameter mem_size = 4096;
  82
  83 reg     [31:0]  adr;
  84 reg     [31:0]  dout;
  85 reg             cyc, stb;
  86 reg     [3:0]   sel;
  87 reg             we;
  88
  89 reg     [31:0]  mem[mem_size:0];
  90 integer         cnt;
  91
  92 ////////////////////////////////////////////////////////////////////
  93 //
  94 // Memory Logic
  95 //
  96
  97 initial
  98    begin
  99         //adr = 32'hxxxx_xxxx;
 100         //adr = 0;
 101         adr = 32'hffff_ffff;
 102         dout = 32'hxxxx_xxxx;
 103         cyc = 0;
 104         stb = 0;
 105         sel = 4'hx;
 106         we = 1'hx;
 107         cnt = 0;
 108         #1;
 109         $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
 110    end
 111
 112
 113
 114 task mem_fill;
 115
 116 integer n;
 117 begin
 118 cnt = 0;
 119 cnt = 0;
 120 for(n=0;n<mem_size;n=n+1)
 121    begin
 122         mem[n] = $random;
 123    end
 124 end
 125 endtask
 126
 127 ////////////////////////////////////////////////////////////////////
 128 //
 129 // Write 1 Word Task
 130 //
 131
 132 task wb_wr1;
 133 input   [31:0]  a;
 134 input   [3:0]   s;
 135 input   [31:0]  d;
 136
 137 begin
 138
 139 //@(posedge clk);
 140 #1;
 141 adr = a;
 142 dout = d;
 143 cyc = 1;
 144 stb = 1;
 145 we=1;
 146 sel = s;
 147
 148 @(posedge clk);
 149 while(~ack & ~err)      @(posedge clk);
 150 #1;
 151 cyc=0;
 152 stb=0;
 153 adr = 32'hxxxx_xxxx;
 154 //adr = 32'hffff_ffff;
 155 //adr = 0;
 156 dout = 32'hxxxx_xxxx;
 157 we = 1'hx;
 158 sel = 4'hx;
 159 adr = $random;
 160
 161 end
 162 endtask
 163
 164 ////////////////////////////////////////////////////////////////////
 165 //
 166 // Write 4 Words Task
 167 //
 168
 169 task wb_wr4;
 170 input   [31:0]  a;
 171 input   [3:0]   s;
 172 input           delay;
 173 input   [31:0]  d1;
 174 input   [31:0]  d2;
 175 input   [31:0]  d3;
 176 input   [31:0]  d4;
 177
 178 integer         delay;
 179
 180 begin
 181
 182 @(posedge clk);
 183 #1;
 184 cyc = 1;
 185 sel = s;
 186
 187 adr = $random;
 188 repeat(delay)
 189    begin
 190         @(posedge clk);
 191         #1;
 192    end
 193 adr = a;
 194 dout = d1;
 195 stb = 1;
 196 we=1;
 197 while(~ack & ~err)      @(posedge clk);
 198 #2;
 199 stb=0;
 200 we=1'bx;
 201 dout = 32'hxxxx_xxxx;
 202 adr = $random;
 203
 204
 205 repeat(delay)
 206    begin
 207         @(posedge clk);
 208         #1;
 209    end
 210 stb=1;
 211 adr = a+4;
 212 dout = d2;
 213 we=1;
 214 @(posedge clk);
 215 while(~ack & ~err)      @(posedge clk);
 216 #2;
 217 stb=0;
 218 we=1'bx;
 219 dout = 32'hxxxx_xxxx;
 220
 221 repeat(delay)
 222    begin
 223         @(posedge clk);
 224         #1;
 225    end
 226 stb=1;
 227 adr = a+8;
 228 dout = d3;
 229 we=1;
 230 @(posedge clk);
 231 while(~ack & ~err)      @(posedge clk);
 232 #2;
 233 stb=0;
 234 we=1'bx;
 235 dout = 32'hxxxx_xxxx;
 236 adr = $random;
 237
 238 repeat(delay)
 239    begin
 240         @(posedge clk);
 241         #1;
 242    end
 243 stb=1;
 244 adr = a+12;
 245 dout = d4;
 246 we=1;
 247 @(posedge clk);
 248 while(~ack & ~err)      @(posedge clk);
 249 #1;
 250 stb=0;
 251 cyc=0;
 252
 253 adr = 32'hxxxx_xxxx;
 254 adr = $random;
 255 //adr = 0;
 256 //adr = 32'hffff_ffff;
 257 dout = 32'hxxxx_xxxx;
 258 we = 1'hx;
 259 sel = 4'hx;
 260
 261 end
 262 endtask
 263
 264
 265 task wb_wr_mult;
 266 input   [31:0]  a;
 267 input   [3:0]   s;
 268 input           delay;
 269 input           count;
 270
 271 integer         delay;
 272 integer         count;
 273 integer         n;
 274
 275 begin
 276
 277 //@(posedge clk);
 278 #1;
 279 cyc = 1;
 280 adr = $random;
 281 for(n=0;n<count;n=n+1)
 282    begin
 283         repeat(delay)
 284            begin
 285                 @(posedge clk);
 286                 #1;
 287            end
 288         adr = a + (n*4);
 289         dout = mem[n + cnt];
 290         stb = 1;
 291         we=1;
 292         sel = s;
 293         if(n!=0)        @(posedge clk);
 294         while(~ack & ~err)      @(posedge clk);
 295         #2;
 296         stb=0;
 297         we=1'bx;
 298         sel = 4'hx;
 299         dout = 32'hxxxx_xxxx;
 300         //adr = 32'hxxxx_xxxx;
 301         adr = $random;
 302    end
 303
 304 cyc=0;
 305
 306 adr = 32'hxxxx_xxxx;
 307 //adr = 32'hffff_ffff;
 308
 309 cnt = cnt + count;
 310 end
 311 endtask
 312
 313
 314 task wb_rmw;
 315 input   [31:0]  a;
 316 input   [3:0]   s;
 317 input           delay;
 318 input           rcount;
 319 input           wcount;
 320
 321 integer         delay;
 322 integer         rcount;
 323 integer         wcount;
 324 integer         n;
 325
 326 begin
 327
 328 @(posedge clk);
 329 #1;
 330 cyc = 1;
 331 we = 0;
 332 sel = s;
 333 repeat(delay)   @(posedge clk);
 334
 335 for(n=0;n<rcount-1;n=n+1)
 336    begin
 337         adr = a + (n*4);
 338         stb = 1;
 339         while(~ack & ~err)      @(posedge clk);
 340         mem[n + cnt] = din;
 341         //$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
 342         #2;
 343         stb=0;
 344         we = 1'hx;
 345         sel = 4'hx;
 346         adr = 32'hxxxx_xxxx;
 347         repeat(delay)
 348            begin
 349                 @(posedge clk);
 350                 #1;
 351            end
 352         we = 0;
 353         sel = s;
 354    end
 355
 356 adr = a+(n*4);
 357 stb = 1;
 358 @(posedge clk);
 359 while(~ack & ~err)      @(posedge clk);
 360 mem[n + cnt] = din;
 361 //$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
 362 #1;
 363 stb=0;
 364 we = 1'hx;
 365 sel = 4'hx;
 366 adr = 32'hxxxx_xxxx;
 367
 368 cnt = cnt + rcount;
 369
 370 //@(posedge clk);
 371
 372
 373 for(n=0;n<wcount;n=n+1)
 374    begin
 375         repeat(delay)
 376            begin
 377                 @(posedge clk);
 378                 #1;
 379            end
 380         adr = a + (n*4);
 381         dout = mem[n + cnt];
 382         stb = 1;
 383         we=1;
 384         sel = s;
 385 //      if(n!=0)
 386                 @(posedge clk);
 387         while(~ack & ~err)      @(posedge clk);
 388         #2;
 389         stb=0;
 390         we=1'bx;
 391         sel = 4'hx;
 392         dout = 32'hxxxx_xxxx;
 393         adr = 32'hxxxx_xxxx;
 394    end
 395
 396 cyc=0;
 397
 398 adr = 32'hxxxx_xxxx;
 399 //adr = 32'hffff_ffff;
 400
 401 cnt = cnt + wcount;
 402 end
 403 endtask
 404
 405
 406
 407
 408 task wb_wmr;
 409 input   [31:0]  a;
 410 input   [3:0]   s;
 411 input           delay;
 412 input           rcount;
 413 input           wcount;
 414
 415 integer         delay;
 416 integer         rcount;
 417 integer         wcount;
 418 integer         n;
 419
 420 begin
 421
 422 @(posedge clk);
 423 #1;
 424 cyc = 1;
 425 we = 1'bx;
 426 sel = 4'hx;
 427 sel = s;
 428
 429 for(n=0;n<wcount;n=n+1)
 430    begin
 431         repeat(delay)
 432            begin
 433                 @(posedge clk);
 434                 #1;
 435            end
 436         adr = a + (n*4);
 437         dout = mem[n + cnt];
 438         stb = 1;
 439         we=1;
 440         sel = s;
 441         @(posedge clk);
 442         while(~ack & ~err)      @(posedge clk);
 443         #2;
 444         stb=0;
 445         we=1'bx;
 446         sel = 4'hx;
 447         dout = 32'hxxxx_xxxx;
 448         adr = 32'hxxxx_xxxx;
 449    end
 450
 451 cnt = cnt + wcount;
 452 stb=0;
 453 repeat(delay)   @(posedge clk);
 454 #1;
 455
 456 sel = s;
 457 we = 0;
 458 for(n=0;n<rcount-1;n=n+1)
 459    begin
 460         adr = a + (n*4);
 461         stb = 1;
 462         while(~ack & ~err)      @(posedge clk);
 463         mem[n + cnt] = din;
 464         //$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
 465         #2;
 466         stb=0;
 467         we = 1'hx;
 468         sel = 4'hx;
 469         adr = 32'hxxxx_xxxx;
 470         repeat(delay)
 471            begin
 472                 @(posedge clk);
 473                 #1;
 474            end
 475         we = 0;
 476         sel = s;
 477    end
 478
 479 adr = a+(n*4);
 480 stb = 1;
 481 @(posedge clk);
 482 while(~ack & ~err)      @(posedge clk);
 483 mem[n + cnt] = din;
 484 cnt = cnt + rcount;
 485 //$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
 486 #1;
 487
 488 cyc = 0;
 489 stb = 0;
 490 we  = 1'hx;
 491 sel = 4'hx;
 492 adr = 32'hxxxx_xxxx;
 493
 494 end
 495 endtask
 496
 497
 498
 499
 500 ////////////////////////////////////////////////////////////////////
 501 //
 502 // Read 1 Word Task
 503 //
 504
 505 task wb_rd1;
 506 input   [31:0]  a;
 507 input   [3:0]   s;
 508 output  [31:0]  d;
 509
 510 begin
 511
 512 //@(posedge clk);
 513 #1;
 514 adr = a;
 515 cyc = 1;
 516 stb = 1;
 517 we  = 0;
 518 sel = s;
 519
 520 //@(posedge clk);
 521 while(~ack & ~err)      @(posedge clk);
 522 d = din;
 523 #1;
 524 cyc=0;
 525 stb=0;
 526 //adr = 32'hxxxx_xxxx;
 527 //adr = 0;
 528 adr = 32'hffff_ffff;
 529 dout = 32'hxxxx_xxxx;
 530 we = 1'hx;
 531 sel = 4'hx;
 532 adr = $random;
 533
 534 end
 535 endtask
 536
 537
 538 ////////////////////////////////////////////////////////////////////
 539 //
 540 // Read 4 Words Task
 541 //
 542
 543
 544 task wb_rd4;
 545 input   [31:0]  a;
 546 input   [3:0]   s;
 547 input           delay;
 548 output  [31:0]  d1;
 549 output  [31:0]  d2;
 550 output  [31:0]  d3;
 551 output  [31:0]  d4;
 552
 553 integer         delay;
 554 begin
 555
 556 @(posedge clk);
 557 #1;
 558 cyc = 1;
 559 we = 0;
 560 adr = $random;
 561 sel = s;
 562 repeat(delay)   @(posedge clk);
 563
 564 adr = a;
 565 stb = 1;
 566 while(~ack & ~err)      @(posedge clk);
 567 d1 = din;
 568 #2;
 569 stb=0;
 570 we = 1'hx;
 571 sel = 4'hx;
 572 adr = $random;
 573 repeat(delay)
 574    begin
 575         @(posedge clk);
 576         #1;
 577    end
 578 we = 0;
 579 sel = s;
 580
 581 adr = a+4;
 582 stb = 1;
 583 @(posedge clk);
 584 while(~ack & ~err)      @(posedge clk);
 585 d2 = din;
 586 #2;
 587 stb=0;
 588 we = 1'hx;
 589 sel = 4'hx;
 590 adr = $random;
 591 repeat(delay)
 592    begin
 593         @(posedge clk);
 594         #1;
 595    end
 596 we = 0;
 597 sel = s;
 598
 599
 600 adr = a+8;
 601 stb = 1;
 602 @(posedge clk);
 603 while(~ack & ~err)      @(posedge clk);
 604 d3 = din;
 605 #2;
 606 stb=0;
 607 we = 1'hx;
 608 sel = 4'hx;
 609 adr = $random;
 610 repeat(delay)
 611    begin
 612         @(posedge clk);
 613         #1;
 614    end
 615 we = 0;
 616 sel = s;
 617
 618 adr = a+12;
 619 stb = 1;
 620 @(posedge clk);
 621 while(~ack & ~err)      @(posedge clk);
 622 d4 = din;
 623 #1;
 624 stb=0;
 625 cyc=0;
 626 we = 1'hx;
 627 sel = 4'hx;
 628 adr = 32'hffff_ffff;
 629 adr = $random;
 630 end
 631 endtask
 632
 633
 634
 635 task wb_rd_mult;
 636 input   [31:0]  a;
 637 input   [3:0]   s;
 638 input           delay;
 639 input           count;
 640
 641 integer         delay;
 642 integer         count;
 643 integer         n;
 644
 645 begin
 646
 647 //@(posedge clk);
 648 #1;
 649 cyc = 1;
 650 we = 0;
 651 sel = s;
 652 repeat(delay)   @(posedge clk);
 653
 654 for(n=0;n<count-1;n=n+1)
 655    begin
 656         adr = a + (n*4);
 657         stb = 1;
 658         while(~ack & ~err)      @(posedge clk);
 659         mem[n + cnt] = din;
 660         #2;
 661         stb=0;
 662         we = 1'hx;
 663         sel = 4'hx;
 664         //adr = 32'hxxxx_xxxx;
 665         adr = $random;
 666         repeat(delay)
 667            begin
 668                 @(posedge clk);
 669                 #1;
 670            end
 671         we = 0;
 672         sel = s;
 673    end
 674
 675 adr = a+(n*4);
 676 stb = 1;
 677 @(posedge clk);
 678 while(~ack & ~err)      @(posedge clk);
 679 mem[n + cnt] = din;
 680 #1;
 681 stb=0;
 682 cyc=0;
 683 we = 1'hx;
 684 sel = 4'hx;
 685 //adr = 32'hffff_ffff;
 686 //adr = 32'hxxxx_xxxx;
 687 adr = $random;
 688
 689 cnt = cnt + count;
 690 end
 691 endtask
 692
 693 endmodule