git.gag.com Git - debian/gnuradio/blob - usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/run_sim.scr

   1 #!/bin/csh -f
   2
   3
   4 # GLOBAL VARIABLES
   5 ###################
   6
   7 set sim_top  = testbench;
   8 set arg_tool = "NCSim";        # By default NCSim is used as simulation tool
   9 set arg_wave = 0;              # By default waveform is not recorded
  10 set arg_verb = 0;              # By default basic display on monitor (no verbose)
  11 set arg_test = 0;              # By default all testcases are simulated
  12
  13
  14 # GETTING PARAMETERS FROM COMMAND LINE
  15 #######################################
  16
  17 set cur_arg = 1;
  18
  19 if ($#argv < 1) then
  20     echo ""
  21     echo "    Verification without any argument:"
  22 else
  23
  24     while ($cur_arg <= $#argv)
  25
  26         switch ("$argv[$cur_arg]")
  27         # HELP ARGUMENT
  28         case "-h":
  29             goto help
  30             breaksw
  31         case "help":
  32             goto help
  33             breaksw
  34         # TOOL ARGUMENT
  35         case "-m":
  36             set arg_tool = "ModelSim";
  37             echo "      $argv[$cur_arg] - ModelSim tool"
  38             breaksw
  39         case "modelsim"
  40             set arg_tool = "ModelSim";
  41             echo "      $argv[$cur_arg] - ModelSim tool"
  42             breaksw
  43         # WAVEFORM ARGUMENT
  44         case "-w":
  45             @ arg_wave = 1;
  46             echo "      $argv[$cur_arg] - Waveform"
  47             breaksw
  48         case "waveform":
  49             @ arg_wave = 1;
  50             echo "      $argv[$cur_arg] - Waveform"
  51             breaksw
  52         # VERBOSE ARGUMENT
  53         case "-v":
  54             @ arg_verb = 1;
  55             echo "      $argv[$cur_arg] - Verbose"
  56             breaksw
  57         case "verbose":
  58             @ arg_verb = 1;
  59             echo "      $argv[$cur_arg] - Verbose"
  60             breaksw
  61         # TESTCASE ARGUMENT
  62         default:
  63             if (-e ../../../bench/verilog/testcases/$argv[$cur_arg].v) then
  64                 set arg_test = $argv[$cur_arg];
  65                 echo "      $argv[$cur_arg] - Testcase"
  66         # INVALID ARGUMENT
  67             else
  68                 echo ""
  69                 echo "    Invalid verification argument: $argv[$cur_arg]"
  70                 goto help
  71             endif
  72             breaksw
  73         endsw
  74
  75         @ cur_arg++
  76     end
  77
  78 endif
  79
  80
  81 # SIMULATION LOOP
  82 ##################
  83
  84 set cur_test_num = 0;
  85
  86 simulate:
  87
  88
  89     # DELETING FILES
  90     #################
  91
  92     # Prepared files
  93     if (-e ./file_list.lst) then
  94         rm -rf ./file_list.lst
  95     endif
  96     if (-e ../bin/cds.lib) then
  97         rm -rf ../bin/cds.lib
  98     endif
  99     if (-e ../bin/hdl.var) then
 100         rm -rf ../bin/hdl.var
 101     endif
 102     if (-e ./compile.args) then
 103         rm -rf ./compile.args
 104     endif
 105     if (-e ./elab.args) then
 106         rm -rf ./elab.args
 107     endif
 108     if (-e ./sim.args) then
 109         rm -rf ./sim.args
 110     endif
 111     if (-e ./sim.tcl) then
 112         rm -rf ./sim.tcl
 113     endif
 114     if (-e ./sim.do) then
 115         rm -rf ./sim.do
 116     endif
 117
 118     # Projects, Libraries and Logs
 119     if (-e ./uart.mpf) then
 120         rm -rf ./uart.mpf
 121     endif
 122     if (-e ./work) then
 123         rm -rf ./work
 124     endif
 125     if (-e ./INCA_libs/worklib) then
 126         rm -rf ./INCA_libs/worklib
 127     endif
 128
 129
 130     # PREPARING FILE LIST
 131     ######################
 132
 133     # Design files
 134     echo "../../../rtl/verilog/uart_top.v"                    >> ./file_list.lst
 135     echo "../../../rtl/verilog/uart_wb.v"                     >> ./file_list.lst
 136     echo "../../../rtl/verilog/uart_transmitter.v"            >> ./file_list.lst
 137     echo "../../../rtl/verilog/uart_receiver.v"               >> ./file_list.lst
 138     echo "../../../rtl/verilog/uart_tfifo.v"                  >> ./file_list.lst
 139     echo "../../../rtl/verilog/uart_rfifo.v"                  >> ./file_list.lst
 140     echo "../../../rtl/verilog/uart_regs.v"                   >> ./file_list.lst
 141     echo "../../../rtl/verilog/uart_debug_if.v"               >> ./file_list.lst
 142
 143     # Testcase file
 144     if ($arg_test == 0) then
 145         set i = 0;
 146         foreach testcase (../../../bench/verilog/testcases/uart*.v)
 147             if ($i == $cur_test_num) then
 148                 set testcase_i = $testcase:t:r
 149             endif
 150             @ i++
 151         end
 152         set max_test_num = $i;
 153     else
 154         set testcase_i   = $arg_test;
 155         set max_test_num = 1;
 156     endif
 157     echo "//////////////////////////////////////////////////" >  ./file_list.lst
 158     echo "// File created within script ${0}"                 >> ./file_list.lst
 159     echo "//     path: $cwd"                                  >> ./file_list.lst
 160     echo "//     user: $user"                                 >> ./file_list.lst
 161     echo "//////////////////////////////////////////////////" >> ./file_list.lst
 162     echo "../../../bench/verilog/testcases/$testcase_i.v"     >> ./file_list.lst
 163     # Delete vawe out file for this testcase, if it already exists
 164     if (-e ../out/$testcase_i.wlf) then
 165         rm -rf ../out/$testcase_i.wlf
 166     endif
 167     # Delete log out file for this testcase, if it already exists
 168     if (-e ../log/$testcase_i.log) then
 169         rm -rf ../log/$testcase_i.log
 170     endif
 171
 172     # Testbench files
 173     echo "../../../bench/verilog/uart_testbench.v"            >> ./file_list.lst
 174     echo "../../../bench/verilog/wb_master_model.v"           >> ./file_list.lst
 175     echo "../../../bench/verilog/uart_device.v"               >> ./file_list.lst
 176     echo "../../../bench/verilog/uart_testbench_utilities.v"  >> ./file_list.lst
 177     echo "../../../bench/verilog/uart_wb_utilities.v"         >> ./file_list.lst
 178     echo "../../../bench/verilog/uart_device_utilities.v"     >> ./file_list.lst
 179
 180
 181     # COMPILING & ELABORATING
 182     ##########################
 183
 184     if ("$arg_tool" == "NCSim") then
 185
 186         # cds.lib library file
 187         echo "//////////////////////////////////////////////////" >  ../bin/cds.lib
 188         echo "// File created within script ${0}"                 >> ../bin/cds.lib
 189         echo "//     path: $cwd"                                  >> ../bin/cds.lib
 190         echo "//     user: $0"                                    >> ../bin/cds.lib
 191         echo "//////////////////////////////////////////////////" >> ../bin/cds.lib
 192         echo "DEFINE worklib ./INCA_libs/worklib"                 >> ../bin/cds.lib
 193
 194         # hdl.var variable file
 195         echo "//////////////////////////////////////////////////" >  ../bin/hdl.var
 196         echo "// File created within script ${0}"                 >> ../bin/hdl.var
 197         echo "//     path: $cwd"                                  >> ../bin/hdl.var
 198         echo "//     user: $0"                                    >> ../bin/hdl.var
 199         echo "//////////////////////////////////////////////////" >> ../bin/hdl.var
 200         echo "INCLUDE \$CDS_INST_DIR/tools/inca/files/hdl.var"    >> ../bin/hdl.var
 201         echo "DEFINE WORK worklib"                                >> ../bin/hdl.var
 202
 203         # compile.args argument file
 204         echo "//////////////////////////////////////////////////" >  ./compile.args
 205         echo "// File created within script ${0}"                 >> ./compile.args
 206         echo "//     path: $cwd"                                  >> ./compile.args
 207         echo "//     user: $0"                                    >> ./compile.args
 208         echo "//////////////////////////////////////////////////" >> ./compile.args
 209         echo "-CDSLIB ../bin/cds.lib"                             >> ./compile.args
 210         echo "-HDLVAR ../bin/hdl.var"                             >> ./compile.args
 211         echo "-MESSAGES"                                          >> ./compile.args
 212         echo "-NOCOPYRIGHT"                                       >> ./compile.args
 213         echo "-INCDIR ../../../rtl/verilog"                       >> ./compile.args
 214         echo "-INCDIR ../../../bench/verilog"                     >> ./compile.args
 215         echo "-INCDIR ../../../bench/verilog/testcases"           >> ./compile.args
 216         if ($arg_verb == 1) then
 217           echo "-DEFINE VERBOSE"                                  >> ./compile.args
 218         endif
 219         cat ./file_list.lst                                       >> ./compile.args
 220
 221         # compiling
 222         ncvlog -LOGFILE ../log/$testcase_i.compile.log -f ./compile.args #> /dev/null
 223
 224         # elab.args argument file
 225         echo "//////////////////////////////////////////////////" >  ./elab.args
 226         echo "// File created within script ${0}"                 >> ./elab.args
 227         echo "//     path: $cwd"                                  >> ./elab.args
 228         echo "//     user: $0"                                    >> ./elab.args
 229         echo "//////////////////////////////////////////////////" >> ./elab.args
 230         echo "-CDSLIB ../bin/cds.lib"                             >> ./elab.args
 231         echo "-HDLVAR ../bin/hdl.var"                             >> ./elab.args
 232         echo "-MESSAGES"                                          >> ./elab.args
 233         echo "-NOCOPYRIGHT"                                       >> ./elab.args
 234         echo "-NOTIMINGCHECKS"                                    >> ./elab.args
 235         echo "-SNAPSHOT worklib.testbench:rtl"                    >> ./elab.args
 236         echo "-NO_TCHK_MSG"                                       >> ./elab.args
 237         echo "-ACCESS +RWC"                                       >> ./elab.args
 238         echo "worklib.$sim_top"                                   >> ./elab.args
 239
 240         # elaborating
 241         ncelab -LOGFILE ../log/$testcase_i.elab.log -f ./elab.args #> /dev/null
 242     else
 243
 244         # compile.args argument file
 245         echo "+libext+.v"                               >> ./compile.args
 246         echo "-y ../../../rtl/verilog"                  >> ./compile.args
 247         echo "-y ../../../bench/verilog"                >> ./compile.args
 248         echo "-y ../../../bench/verilog/testcases"      >> ./compile.args
 249         echo "-work ./work"                             >> ./compile.args
 250         echo "+incdir+../../../rtl/verilog"             >> ./compile.args
 251         echo "+incdir+../../../bench/verilog"           >> ./compile.args
 252         echo '+define+LOG_DIR=\"../log/$testcase_i\"'   >> ./compile.args
 253         if ($arg_verb == 1) then
 254           echo "+define+VERBOSE"                        >> ./compile.args
 255         endif
 256         cat ./file_list.lst                             >> ./compile.args
 257
 258         # open project
 259 #        echo "project new ./ testbench ./work"           >> ./sim.do
 260         vlib -dos ./work
 261
 262         # compiling
 263  #       echo "vlog -f ./compile.args"                   >> ./sim.do
 264         vlog -f ./compile.args
 265     endif
 266
 267
 268     # SIMULATING
 269     #############
 270
 271     if ("$arg_tool" == "NCSim") then
 272
 273         # sim.args argument file
 274         echo "//////////////////////////////////////////////////" >  ./sim.args
 275         echo "// File created within script ${0}"                 >> ./sim.args
 276         echo "//     path: $cwd"                                  >> ./sim.args
 277         echo "//     user: $0"                                    >> ./sim.args
 278         echo "//////////////////////////////////////////////////" >> ./sim.args
 279         echo "-CDSLIB ../bin/cds.lib"                             >> ./sim.args
 280         echo "-HDLVAR ../bin/hdl.var"                             >> ./sim.args
 281         echo "-MESSAGES"                                          >> ./sim.args
 282         echo "-NOCOPYRIGHT"                                       >> ./sim.args
 283         echo "-INPUT ./sim.tcl"                                   >> ./sim.args
 284         echo "worklib.testbench:rtl"                              >> ./sim.args
 285
 286         # sim.tcl file
 287         echo "//////////////////////////////////////////////////"              >  ./sim.tcl
 288         echo "// File created within script ${0}"                              >> ./sim.tcl
 289         echo "//     path: $cwd"                                               >> ./sim.tcl
 290         echo "//     user: $0"                                                 >> ./sim.tcl
 291         echo "//////////////////////////////////////////////////"              >> ./sim.tcl
 292         if ($arg_wave) then
 293             echo "database -open waves -shm -into ../out/waves.shm"            >> ./sim.tcl
 294             echo "probe -create -database waves $sim_top -shm -all -depth all" >> ./sim.tcl
 295             echo "run"                                                         >> ./sim.tcl
 296         else
 297             echo "run"                                                         >> ./sim.tcl
 298         endif
 299         echo     "quit"                                                        >> ./sim.tcl
 300
 301         # simulating
 302         ncsim -LICQUEUE -LOGFILE ../log/$testcase_i.sim.log -f ./sim.args
 303     else
 304
 305         # sim.do do file
 306         echo "vsim work.testbench work.testbench_utilities work.uart_wb_utilities work.uart_device_utilities work.testcase -wlf ../out/$testcase_i.wlf" >> ./sim.do
 307         if ($arg_wave) then
 308           echo "log -r -internal -ports /testbench/*"                          >> ./sim.do
 309         endif
 310         echo "run -all"                                                        >> ./sim.do
 311
 312         vsim -c -do ./sim.do
 313
 314     endif
 315
 316     @ cur_test_num++
 317
 318     if ($cur_test_num < $max_test_num) then
 319         goto simulate
 320     endif
 321
 322 exit
 323
 324
 325 # HELP DISPLAY
 326 ###############
 327
 328 help:
 329     echo ""
 330     echo "    Valid verification arguments:"
 331     echo "      'help'     / '-h' : This help is displayed"
 332     echo "      'modelsim' / '-m' : ModelSim simulation tool is used, otherwise"
 333     echo "                          NCSim is used (default)"
 334     echo "      'waveform' / '-w' : Waveform output is recorded, otherwise"
 335     echo "                          NO waveform is recorded (default)"
 336     echo "      'verbose'  / '-v' : Verbose display on monitor, otherwise"
 337     echo "                          basic display on monitor (default)"
 338     echo "      '\042testcase\042'      : Testcase which is going to be simulated, otherwise"
 339     echo "                          ALL testcases are simulated - regression (default);"
 340     echo "                          Available testcases:"
 341     foreach testcase (../../../bench/verilog/testcases/uart*.v)
 342         echo "                            "$testcase:t:r
 343     end
 344     echo ""
 345 exit