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   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  uart_TX_FIFO.v                                              ////
   4 ////                                                              ////
   5 ////                                                              ////
   6 ////  This file is part of the "UART 16550 compatible" project    ////
   7 ////  http://www.opencores.org/cores/uart16550/                   ////
   8 ////                                                              ////
   9 ////  Documentation related to this project:                      ////
  10 ////  - http://www.opencores.org/cores/uart16550/                 ////
  11 ////                                                              ////
  12 ////  Projects compatibility:                                     ////
  13 ////  - WISHBONE                                                  ////
  14 ////  RS232 Protocol                                              ////
  15 ////  16550D uart (mostly supported)                              ////
  16 ////                                                              ////
  17 ////  Overview (main Features):                                   ////
  18 ////  UART core WISHBONE interface.                               ////
  19 ////                                                              ////
  20 ////  Known problems (limits):                                    ////
  21 ////  Inserts one wait state on all transfers.                    ////
  22 ////  Note affected signals and the way they are affected.        ////
  23 ////                                                              ////
  24 ////  To Do:                                                      ////
  25 ////  Nothing.                                                    ////
  26 ////                                                              ////
  27 ////  Author(s):                                                  ////
  28 ////      - gorban@opencores.org                                  ////
  29 ////      - Jacob Gorban                                          ////
  30 ////                                                              ////
  31 ////  Created:        2001/05/12                                  ////
  32 ////  Last Updated:   2001/05/17                                  ////
  33 ////                  (See log for the revision history)          ////
  34 ////                                                              ////
  35 ////                                                              ////
  36 //////////////////////////////////////////////////////////////////////
  37 ////                                                              ////
  38 //// Copyright (C) 2000 Jacob Gorban, gorban@opencores.org        ////
  39 ////                                                              ////
  40 //// This source file may be used and distributed without         ////
  41 //// restriction provided that this copyright statement is not    ////
  42 //// removed from the file and that any derivative work contains  ////
  43 //// the original copyright notice and the associated disclaimer. ////
  44 ////                                                              ////
  45 //// This source file is free software; you can redistribute it   ////
  46 //// and/or modify it under the terms of the GNU Lesser General   ////
  47 //// Public License as published by the Free Software Foundation; ////
  48 //// either version 2.1 of the License, or (at your option) any   ////
  49 //// later version.                                               ////
  50 ////                                                              ////
  51 //// This source is distributed in the hope that it will be       ////
  52 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  53 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  54 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  55 //// details.                                                     ////
  56 ////                                                              ////
  57 //// You should have received a copy of the GNU Lesser General    ////
  58 //// Public License along with this source; if not, download it   ////
  59 //// from http://www.opencores.org/lgpl.shtml                     ////
  60 ////                                                              ////
  61 //////////////////////////////////////////////////////////////////////
  62 //
  63 // CVS Revision History
  64 //
  65 // $Log: uart_wb.v,v $
  66 // Revision 1.4  2001/05/31 20:08:01  gorban
  67 // FIFO changes and other corrections.
  68 //
  69 // Revision 1.3  2001/05/21 19:12:01  gorban
  70 // Corrected some Linter messages.
  71 //
  72 // Revision 1.2  2001/05/17 18:34:18  gorban
  73 // First 'stable' release. Should be sythesizable now. Also added new header.
  74 //
  75 // Revision 1.0  2001-05-17 21:27:13+02  jacob
  76 // Initial revision
  77 //
  78 //
  79
  80 // UART core WISHBONE interface
  81 //
  82 // Author: Jacob Gorban   (jacob.gorban@flextronicssemi.com)
  83 // Company: Flextronics Semiconductor
  84 //
  85
  86 `include "timescale.v"
  87
  88 module uart_wb (clk,
  89         wb_rst_i,
  90         wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,
  91         we_o, re_o // Write and read enable output for the core
  92
  93         );
  94
  95 input                           clk;
  96
  97 // WISHBONE interface
  98 input                           wb_rst_i;
  99 input                           wb_we_i;
 100 input                           wb_stb_i;
 101 input                           wb_cyc_i;
 102 output                          wb_ack_o;
 103 output                          we_o;
 104 output                          re_o;
 105
 106 wire                            we_o;
 107 reg                             wb_ack_o;
 108
 109 always @(posedge clk or posedge wb_rst_i)
 110 begin
 111         if (wb_rst_i)
 112         begin
 113                 wb_ack_o <= #1 1'b0;
 114         end
 115         else
 116         begin
 117 //              wb_ack_o <= #1 wb_stb_i & wb_cyc_i; // 1 clock wait state on all transfers
 118                 wb_ack_o <= #1 wb_stb_i & wb_cyc_i & ~wb_ack_o; // 1 clock wait state on all transfers
 119         end
 120 end
 121
 122 assign we_o =  wb_we_i & wb_cyc_i & wb_stb_i; //WE for registers
 123 assign re_o = ~wb_we_i & wb_cyc_i & wb_stb_i; //RE for registers
 124
 125 endmodule