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   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  uart_top.v                                                  ////
   4 ////                                                              ////
   5 ////                                                              ////
   6 ////  This file is part of the "UART 16550 compatible" project    ////
   7 ////  http://www.opencores.org/cores/uart16550/                   ////
   8 ////                                                              ////
   9 ////  Documentation related to this project:                      ////
  10 ////  - http://www.opencores.org/cores/uart16550/                 ////
  11 ////                                                              ////
  12 ////  Projects compatibility:                                     ////
  13 ////  - WISHBONE                                                  ////
  14 ////  RS232 Protocol                                              ////
  15 ////  16550D uart (mostly supported)                              ////
  16 ////                                                              ////
  17 ////  Overview (main Features):                                   ////
  18 ////  UART core top level.                                        ////
  19 ////                                                              ////
  20 ////  Known problems (limits):                                    ////
  21 ////  Note that transmitter and receiver instances are inside     ////
  22 ////  the uart_regs.v file.                                       ////
  23 ////                                                              ////
  24 ////  To Do:                                                      ////
  25 ////  Nothing so far.                                             ////
  26 ////                                                              ////
  27 ////  Author(s):                                                  ////
  28 ////      - gorban@opencores.org                                  ////
  29 ////      - Jacob Gorban                                          ////
  30 ////                                                              ////
  31 ////  Created:        2001/05/12                                  ////
  32 ////  Last Updated:   2001/05/17                                  ////
  33 ////                  (See log for the revision history)          ////
  34 ////                                                              ////
  35 ////                                                              ////
  36 //////////////////////////////////////////////////////////////////////
  37 ////                                                              ////
  38 //// Copyright (C) 2000 Jacob Gorban, gorban@opencores.org        ////
  39 ////                                                              ////
  40 //// This source file may be used and distributed without         ////
  41 //// restriction provided that this copyright statement is not    ////
  42 //// removed from the file and that any derivative work contains  ////
  43 //// the original copyright notice and the associated disclaimer. ////
  44 ////                                                              ////
  45 //// This source file is free software; you can redistribute it   ////
  46 //// and/or modify it under the terms of the GNU Lesser General   ////
  47 //// Public License as published by the Free Software Foundation; ////
  48 //// either version 2.1 of the License, or (at your option) any   ////
  49 //// later version.                                               ////
  50 ////                                                              ////
  51 //// This source is distributed in the hope that it will be       ////
  52 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  53 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  54 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  55 //// details.                                                     ////
  56 ////                                                              ////
  57 //// You should have received a copy of the GNU Lesser General    ////
  58 //// Public License along with this source; if not, download it   ////
  59 //// from http://www.opencores.org/lgpl.shtml                     ////
  60 ////                                                              ////
  61 //////////////////////////////////////////////////////////////////////
  62 //
  63 // CVS Revision History
  64 //
  65 // $Log: uart_top.v,v $
  66 // Revision 1.4  2001/05/31 20:08:01  gorban
  67 // FIFO changes and other corrections.
  68 //
  69 // Revision 1.3  2001/05/21 19:12:02  gorban
  70 // Corrected some Linter messages.
  71 //
  72 // Revision 1.2  2001/05/17 18:34:18  gorban
  73 // First 'stable' release. Should be sythesizable now. Also added new header.
  74 //
  75 // Revision 1.0  2001-05-17 21:27:12+02  jacob
  76 // Initial revision
  77 //
  78 //
  79
  80 `include "timescale.v"
  81 `include "uart_defines.v"
  82
  83 module uart_top (
  84         clk,
  85
  86         // Wishbone signals
  87         wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,
  88         int_o, // interrupt request
  89
  90         // UART signals
  91         // serial input/output
  92         stx_pad_o, srx_pad_i,
  93
  94         // modem signals
  95         rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i
  96
  97         );
  98
  99 parameter                                                        uart_data_width = 8;
 100 parameter                                                        uart_addr_width = `UART_ADDR_WIDTH;
 101
 102 input                                                            clk;
 103
 104 // WISHBONE interface
 105 input                                                            wb_rst_i;
 106 input [uart_addr_width-1:0]      wb_addr_i;
 107 input [uart_data_width-1:0]      wb_dat_i;
 108 output [uart_data_width-1:0]     wb_dat_o;
 109 input                                                            wb_we_i;
 110 input                                                            wb_stb_i;
 111 input                                                            wb_cyc_i;
 112 output                                                           wb_ack_o;
 113 output                                                           int_o;
 114
 115 // UART signals
 116 input                                                            srx_pad_i;
 117 output                                                           stx_pad_o;
 118 output                                                           rts_pad_o;
 119 input                                                            cts_pad_i;
 120 output                                                           dtr_pad_o;
 121 input                                                            dsr_pad_i;
 122 input                                                            ri_pad_i;
 123 input                                                            dcd_pad_i;
 124
 125 wire                                                                     stx_pad_o;
 126 wire                                                                     rts_pad_o;
 127 wire                                                                     dtr_pad_o;
 128
 129 wire [uart_addr_width-1:0]       wb_addr_i;
 130 wire [uart_data_width-1:0]       wb_dat_i;
 131 wire [uart_data_width-1:0]       wb_dat_o;
 132
 133 wire                                                                     we_o;  // Write enable for registers
 134 wire                           re_o;    // Read enable for registers
 135 //
 136 // MODULE INSTANCES
 137 //
 138
 139 ////  WISHBONE interface module
 140 uart_wb         wb_interface(
 141                 .clk(           clk             ),
 142                 .wb_rst_i(      wb_rst_i        ),
 143                 .wb_we_i(       wb_we_i         ),
 144                 .wb_stb_i(      wb_stb_i        ),
 145                 .wb_cyc_i(      wb_cyc_i        ),
 146                 .wb_ack_o(      wb_ack_o        ),
 147                 .we_o(          we_o            ),
 148                 .re_o(re_o)
 149                 );
 150
 151 // Registers
 152 uart_regs       regs(
 153                 .clk(           clk             ),
 154                 .wb_rst_i(      wb_rst_i        ),
 155                 .wb_addr_i(     wb_addr_i       ),
 156                 .wb_dat_i(      wb_dat_i        ),
 157                 .wb_dat_o(      wb_dat_o        ),
 158                 .wb_we_i(       we_o            ),
 159     .wb_re_i(re_o),
 160                 .modem_inputs(  {cts_pad_i, dsr_pad_i,
 161                                  ri_pad_i,  dcd_pad_i}  ),
 162                 .stx_pad_o(             stx_pad_o               ),
 163                 .srx_pad_i(             srx_pad_i               ),
 164                 .enable(        enable          ),
 165                 .rts_pad_o(             rts_pad_o               ),
 166                 .dtr_pad_o(             dtr_pad_o               ),
 167                 .int_o(         int_o           )
 168                 );
 169
 170 endmodule