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   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  uart_sync_flops.v                                             ////
   4 ////                                                              ////
   5 ////                                                              ////
   6 ////  This file is part of the "UART 16550 compatible" project    ////
   7 ////  http://www.opencores.org/cores/uart16550/                   ////
   8 ////                                                              ////
   9 ////  Documentation related to this project:                      ////
  10 ////  - http://www.opencores.org/cores/uart16550/                 ////
  11 ////                                                              ////
  12 ////  Projects compatibility:                                     ////
  13 ////  - WISHBONE                                                  ////
  14 ////  RS232 Protocol                                              ////
  15 ////  16550D uart (mostly supported)                              ////
  16 ////                                                              ////
  17 ////  Overview (main Features):                                   ////
  18 ////  UART core receiver logic                                    ////
  19 ////                                                              ////
  20 ////  Known problems (limits):                                    ////
  21 ////  None known                                                  ////
  22 ////                                                              ////
  23 ////  To Do:                                                      ////
  24 ////  Thourough testing.                                          ////
  25 ////                                                              ////
  26 ////  Author(s):                                                  ////
  27 ////      - Andrej Erzen (andreje@flextronics.si)                 ////
  28 ////      - Tadej Markovic (tadejm@flextronics.si)                ////
  29 ////                                                              ////
  30 ////  Created:        2004/05/20                                  ////
  31 ////  Last Updated:   2004/05/20                                  ////
  32 ////                  (See log for the revision history)          ////
  33 ////                                                              ////
  34 ////                                                              ////
  35 //////////////////////////////////////////////////////////////////////
  36 ////                                                              ////
  37 //// Copyright (C) 2000, 2001 Authors                             ////
  38 ////                                                              ////
  39 //// This source file may be used and distributed without         ////
  40 //// restriction provided that this copyright statement is not    ////
  41 //// removed from the file and that any derivative work contains  ////
  42 //// the original copyright notice and the associated disclaimer. ////
  43 ////                                                              ////
  44 //// This source file is free software; you can redistribute it   ////
  45 //// and/or modify it under the terms of the GNU Lesser General   ////
  46 //// Public License as published by the Free Software Foundation; ////
  47 //// either version 2.1 of the License, or (at your option) any   ////
  48 //// later version.                                               ////
  49 ////                                                              ////
  50 //// This source is distributed in the hope that it will be       ////
  51 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  52 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  53 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  54 //// details.                                                     ////
  55 ////                                                              ////
  56 //// You should have received a copy of the GNU Lesser General    ////
  57 //// Public License along with this source; if not, download it   ////
  58 //// from http://www.opencores.org/lgpl.shtml                     ////
  59 ////                                                              ////
  60 //////////////////////////////////////////////////////////////////////
  61 //
  62 // CVS Revision History
  63 //
  64 // $Log: uart_sync_flops.v,v $
  65 // Revision 1.1  2004/05/21 11:43:25  tadejm
  66 // Added to synchronize RX input to Wishbone clock.
  67 //
  68 //
  69
  70
  71 `include "timescale.v"
  72
  73
  74 module uart_sync_flops
  75 (
  76   // internal signals
  77   rst_i,
  78   clk_i,
  79   stage1_rst_i,
  80   stage1_clk_en_i,
  81   async_dat_i,
  82   sync_dat_o
  83 );
  84
  85 parameter Tp            = 1;
  86 parameter width         = 1;
  87 parameter init_value    = 1'b0;
  88
  89 input                           rst_i;                  // reset input
  90 input                           clk_i;                  // clock input
  91 input                           stage1_rst_i;           // synchronous reset for stage 1 FF
  92 input                           stage1_clk_en_i;        // synchronous clock enable for stage 1 FF
  93 input   [width-1:0]             async_dat_i;            // asynchronous data input
  94 output  [width-1:0]             sync_dat_o;             // synchronous data output
  95
  96
  97 //
  98 // Interal signal declarations
  99 //
 100
 101 reg     [width-1:0]             sync_dat_o;
 102 reg     [width-1:0]             flop_0;
 103
 104
 105 // first stage
 106 always @ (posedge clk_i or posedge rst_i)
 107 begin
 108     if (rst_i)
 109         flop_0 <= #Tp {width{init_value}};
 110     else
 111         flop_0 <= #Tp async_dat_i;
 112 end
 113
 114 // second stage
 115 always @ (posedge clk_i or posedge rst_i)
 116 begin
 117     if (rst_i)
 118         sync_dat_o <= #Tp {width{init_value}};
 119     else if (stage1_rst_i)
 120         sync_dat_o <= #Tp {width{init_value}};
 121     else if (stage1_clk_en_i)
 122         sync_dat_o <= #Tp flop_0;
 123 end
 124
 125 endmodule