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   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  uart_debug_if.v                                             ////
   4 ////                                                              ////
   5 ////                                                              ////
   6 ////  This file is part of the "UART 16550 compatible" project    ////
   7 ////  http://www.opencores.org/cores/uart16550/                   ////
   8 ////                                                              ////
   9 ////  Documentation related to this project:                      ////
  10 ////  - http://www.opencores.org/cores/uart16550/                 ////
  11 ////                                                              ////
  12 ////  Projects compatibility:                                     ////
  13 ////  - WISHBONE                                                  ////
  14 ////  RS232 Protocol                                              ////
  15 ////  16550D uart (mostly supported)                              ////
  16 ////                                                              ////
  17 ////  Overview (main Features):                                   ////
  18 ////  UART core debug interface.                                  ////
  19 ////                                                              ////
  20 ////  Author(s):                                                  ////
  21 ////      - gorban@opencores.org                                  ////
  22 ////      - Jacob Gorban                                          ////
  23 ////                                                              ////
  24 ////  Created:        2001/12/02                                  ////
  25 ////                  (See log for the revision history)          ////
  26 ////                                                              ////
  27 //////////////////////////////////////////////////////////////////////
  28 ////                                                              ////
  29 //// Copyright (C) 2000, 2001 Authors                             ////
  30 ////                                                              ////
  31 //// This source file may be used and distributed without         ////
  32 //// restriction provided that this copyright statement is not    ////
  33 //// removed from the file and that any derivative work contains  ////
  34 //// the original copyright notice and the associated disclaimer. ////
  35 ////                                                              ////
  36 //// This source file is free software; you can redistribute it   ////
  37 //// and/or modify it under the terms of the GNU Lesser General   ////
  38 //// Public License as published by the Free Software Foundation; ////
  39 //// either version 2.1 of the License, or (at your option) any   ////
  40 //// later version.                                               ////
  41 ////                                                              ////
  42 //// This source is distributed in the hope that it will be       ////
  43 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  44 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  45 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  46 //// details.                                                     ////
  47 ////                                                              ////
  48 //// You should have received a copy of the GNU Lesser General    ////
  49 //// Public License along with this source; if not, download it   ////
  50 //// from http://www.opencores.org/lgpl.shtml                     ////
  51 ////                                                              ////
  52 //////////////////////////////////////////////////////////////////////
  53 //
  54 // CVS Revision History
  55 //
  56 // $Log: uart_debug_if.v,v $
  57 // Revision 1.5  2002/07/29 21:16:18  gorban
  58 // The uart_defines.v file is included again in sources.
  59 //
  60 // Revision 1.4  2002/07/22 23:02:23  gorban
  61 // Bug Fixes:
  62 //  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
  63 //   Problem reported by Kenny.Tung.
  64 //  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
  65 //
  66 // Improvements:
  67 //  * Made FIFO's as general inferrable memory where possible.
  68 //  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
  69 //  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
  70 //
  71 //  * Added optional baudrate output (baud_o).
  72 //  This is identical to BAUDOUT* signal on 16550 chip.
  73 //  It outputs 16xbit_clock_rate - the divided clock.
  74 //  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
  75 //
  76 // Revision 1.3  2001/12/19 08:40:03  mohor
  77 // Warnings fixed (unused signals removed).
  78 //
  79 // Revision 1.2  2001/12/12 22:17:30  gorban
  80 // some synthesis bugs fixed
  81 //
  82 // Revision 1.1  2001/12/04 21:14:16  gorban
  83 // committed the debug interface file
  84 //
  85
  86 // synopsys translate_off
  87 `include "timescale.v"
  88 // synopsys translate_on
  89
  90 `include "uart_defines.v"
  91
  92 module uart_debug_if (/*AUTOARG*/
  93 // Outputs
  94 wb_dat32_o,
  95 // Inputs
  96 wb_adr_i, ier, iir, fcr, mcr, lcr, msr,
  97 lsr, rf_count, tf_count, tstate, rstate
  98 ) ;
  99
 100 input [`UART_ADDR_WIDTH-1:0]            wb_adr_i;
 101 output [31:0]                                                   wb_dat32_o;
 102 input [3:0]                                                     ier;
 103 input [3:0]                                                     iir;
 104 input [1:0]                                                     fcr;  /// bits 7 and 6 of fcr. Other bits are ignored
 105 input [4:0]                                                     mcr;
 106 input [7:0]                                                     lcr;
 107 input [7:0]                                                     msr;
 108 input [7:0]                                                     lsr;
 109 input [`UART_FIFO_COUNTER_W-1:0] rf_count;
 110 input [`UART_FIFO_COUNTER_W-1:0] tf_count;
 111 input [2:0]                                                     tstate;
 112 input [3:0]                                                     rstate;
 113
 114
 115 wire [`UART_ADDR_WIDTH-1:0]             wb_adr_i;
 116 reg [31:0]                                                              wb_dat32_o;
 117
 118 always @(/*AUTOSENSE*/fcr or ier or iir or lcr or lsr or mcr or msr
 119                         or rf_count or rstate or tf_count or tstate or wb_adr_i)
 120         case (wb_adr_i)
 121                                       // 8 + 8 + 4 + 4 + 8
 122                 5'b01000: wb_dat32_o = {msr,lcr,iir,ier,lsr};
 123                                // 5 + 2 + 5 + 4 + 5 + 3
 124                 5'b01100: wb_dat32_o = {8'b0, fcr,mcr, rf_count, rstate, tf_count, tstate};
 125                 default: wb_dat32_o = 0;
 126         endcase // case(wb_adr_i)
 127
 128 endmodule // uart_debug_if
 129