1 //////////////////////////////////////////////////////////////////////
3 //// uart_testbench.v ////
5 //// This file is part of the "uart16550" project ////
6 //// http://www.opencores.org/projects/uart16550/ ////
9 //// - tadej@opencores.org (Tadej Markovic) ////
11 //// All additional information is avaliable in the README.txt ////
15 //////////////////////////////////////////////////////////////////////
17 //// Copyright (C) 2000 - 2004 authors ////
19 //// This source file may be used and distributed without ////
20 //// restriction provided that this copyright statement is not ////
21 //// removed from the file and that any derivative work contains ////
22 //// the original copyright notice and the associated disclaimer. ////
24 //// This source file is free software; you can redistribute it ////
25 //// and/or modify it under the terms of the GNU Lesser General ////
26 //// Public License as published by the Free Software Foundation; ////
27 //// either version 2.1 of the License, or (at your option) any ////
28 //// later version. ////
30 //// This source is distributed in the hope that it will be ////
31 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
32 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
33 //// PURPOSE. See the GNU Lesser General Public License for more ////
36 //// You should have received a copy of the GNU Lesser General ////
37 //// Public License along with this source; if not, download it ////
38 //// from http://www.opencores.org/lgpl.shtml ////
40 //////////////////////////////////////////////////////////////////////
42 // CVS Revision History
44 // $Log: uart_testbench.v,v $
45 // Revision 1.1 2004/03/27 03:55:17 tadejm
46 // Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.
52 `include "uart_defines.v"
53 `include "uart_testbench_defines.v"
54 `include "wb_model_defines.v"
55 `include "timescale.v"
60 parameter max_wait_cnt = 20000;
68 // UART Wishbone Slave signals
70 wire [`UART_ADDR_WIDTH-1:0] wbs_adr_i;
71 wire [`UART_DATA_WIDTH-1:0] wbs_dat_i;
72 wire [`UART_DATA_WIDTH-1:0] wbs_dat_o;
80 wire wbs_rty_o = 1'b0;
81 wire wbs_err_o = 1'b0;
86 // UART Serial Data I/O signals
89 // UART Modem I/O signals
96 `ifdef UART_HAS_BAUDRATE_OUTPUT
104 reg wb_clk; // divided device clock with period T_wb_clk_period
105 // WB clock enable signal
106 reg wb_clk_en = 1'b1;
107 // WB clock period variable
108 real T_wb_clk_period = 20;
112 event reset_released;
115 // Error detection event
116 event error_detected;
118 // UART register monitor
119 //#########################
121 // Line Status Register
122 // Reading LSR register
124 // Bit 0 - Data Ready
125 reg lsr_reg_bit0_change_allowed;
126 // Bit 1 - Overrun Error
127 reg lsr_reg_bit1_change_allowed;
128 // Bit 2 - Parity Error
129 reg lsr_reg_bit2_change_allowed;
130 reg [4:0] rx_fifo_par_rd_pointer;
132 // Bit 3 - Framing Error
133 reg lsr_reg_bit3_change_allowed;
134 reg [4:0] rx_fifo_frm_rd_pointer;
136 // Bit 4 - Break Interrupt
137 reg lsr_reg_bit4_change_allowed;
138 reg [4:0] rx_fifo_brk_rd_pointer;
140 // Bit 5 - Transmitter Holding Register Empty
141 reg lsr_reg_bit5_change_allowed;
142 // Bit 6 - Transmitter Empty
143 reg lsr_reg_bit6_change_allowed;
144 // Bit 7 - Error in RX FIFO
145 reg lsr_reg_bit7_change_allowed;
147 // UART transmitter monitor
148 //#########################
151 reg [7:0] tx_shift_reg;
152 reg tx_shift_reg_empty;
153 reg tx_start_bit_edge;
154 reg [7:0] tx_fifo [0:31];
155 reg [4:0] tx_fifo_wr_pointer;
156 reg [4:0] tx_fifo_rd_pointer;
157 reg [4:0] tx_fifo_status;
159 // UART receiver monitor
160 //######################
163 reg [7:0] rx_shift_reg;
164 reg rx_shift_reg_full;
167 reg rx_framing_glitch;
169 reg rx_overrun_err_occured;
170 reg [7:0] rx_fifo_data [0:31];
171 reg [31:0] rx_fifo_par;
172 reg [31:0] rx_fifo_frm;
173 reg [31:0] rx_fifo_brk;
174 reg [4:0] rx_fifo_wr_pointer;
175 reg [4:0] rx_fifo_rd_pointer;
176 reg [4:0] rx_fifo_status;
179 // UART register tracker
180 //######################
193 event ier_reg_changed;
194 event iir_reg_changed;
195 event fcr_reg_changed;
196 event lcr_reg_changed;
197 event mcr_reg_changed;
198 event lsr_reg_changed;
199 event msr_reg_changed;
200 event dll_reg_changed;
201 event dlm_reg_changed;
203 reg [`UART_ADDR_WIDTH-1:0] reg_adr;
204 reg [`UART_DATA_WIDTH-1:0] reg_dat;
207 event tx_reg_written;
213 uart_top #(`UART_DATA_WIDTH, `UART_ADDR_WIDTH) i_uart_top
216 .wb_rst_i (wb_reset),
218 // WB slave signals - 2 address locations for two registers!
219 .wb_cyc_i (wbs_cyc_i),
220 .wb_stb_i (wbs_stb_i),
222 .wb_sel_i (wbs_sel_i),
223 .wb_adr_i (wbs_adr_i),
224 .wb_dat_i (wbs_dat_i),
225 .wb_dat_o (wbs_dat_o),
226 .wb_ack_o (wbs_ack_o),
228 .stx_pad_o (stx_pad_o),
229 .srx_pad_i (srx_pad_i),
231 .rts_pad_o (rts_pad_o),
232 .cts_pad_i (cts_pad_i),
233 .dtr_pad_o (dtr_pad_o),
234 .dsr_pad_i (dsr_pad_i),
235 .ri_pad_i (ri_pad_i),
236 .dcd_pad_i (dcd_pad_i)
237 `ifdef UART_HAS_BAUDRATE_OUTPUT
243 uart_device i_uart_device
257 wb_master_model #(`UART_DATA_WIDTH, `UART_ADDR_WIDTH, 4) i_wb_master_model
259 .wb_rst_i (wb_reset),
261 .wbm_cyc_o (wbs_cyc_i),
264 .wbm_stb_o (wbs_stb_i),
265 .wbm_we_o (wbs_we_i),
266 .wbm_adr_o (wbs_adr_i),
267 .wbm_sel_o (wbs_sel_i),
268 .wbm_dat_o (wbs_dat_i),
269 .wbm_dat_i (wbs_dat_o),
270 .wbm_ack_i (wbs_ack_o),
271 .wbm_err_i (wbs_err_o), // inactive (1'b0)
272 .wbm_rty_i (wbs_rty_o) // inactive (1'b0)
278 // Initial system values
284 // WB clock generation (DEVICE clock is generated in uart_device.v)
285 //#################################################################
287 // DEVICE's clock generation:
289 // // rx_clk rising edge
290 // always@(posedge rx_clk)
292 // #(T_clk_period / 2) rx_clk = 1'b0;
293 // // rx_clk falling edge
294 // always@(negedge rx_clk)
296 // #(T_clk_period / 2) rx_clk = 1'b1;
298 // DEVICE's transmit clocks generation:
300 // // tx_clk rising edge
301 // always@(posedge tx_clk)
303 // #((T_clk_period / 2) * 16 * T_divisor) tx_clk = 1'b0;
304 // // tx_clk falling edge
305 // always@(negedge tx_clk)
307 // #((T_clk_period / 2) * 16 * T_divisor) tx_clk = 1'b1;
311 always@(posedge wb_clk)
313 #(T_wb_clk_period / 2) wb_clk = 1'b0;
314 always@(negedge wb_clk)
316 #(T_wb_clk_period / 2) wb_clk = 1'b1;
319 // SYSTEM signals tracker
320 //#######################
323 always@(posedge wb_reset)
325 always@(negedge wb_reset)
329 always@(posedge wb_int_o)
331 always@(negedge wb_int_o)
335 // UART register tracker
336 //######################
340 // RBR (R/ | ADR 0 | DLAB 0)
341 // [7:0] -RX---- "rxdata" Receiver Buffer Register
343 // THR ( /W | ADR 0 | DLAB 0)
344 // [7:0] ----TX- "txdata" Transmitter Holding Register
346 // IER (R/W | ADR 1 | DLAB 0)
347 // [0] -RX---- "1" Received Data Available & Receive Fifo Timeout
348 // [1] ----TX- "1" Transmitter Holding Register Empty
349 // [2] -RX---- "1" Receiver Line Status
350 // [3] -MODEM- "1" Modem Status
353 // [0] ------- "0" Interrupt is Pending (decreasing priority level in following 3 bits)
354 // [3:1] -RX---- "011" Receiver Line Status - Overrun, Parity, Framing error or Break int. ---> READ LSR
355 // [3:1] -RX---- "010" Received Data Available - Fifo Trigger Level Reached ------------------> READ RBR (Fifo lower than trig.)
356 // [3:1] -RX---- "110" Timeout Indication - Fifo not empty & no Fifo action for 4 char times -> READ RBR
357 // [3:1] ----TX- "001" Transmitter Holding Register Empty - THR Empty ------------------------> READ IIR | WRITE THR
358 // [3:1] -MODEM- "000" Modem Status - CTS, DSR, DCD changed or RI changed from '0' to '1' ----> READ MSR
361 // [1] -RX---- "1" Clear only Receiver Fifo (not shift register)
362 // [2] ----TX- "1" Clear only Transmitter Fifo (not shift register)
363 // [7:6] -RX---- "00" 1 BYTE Receiver Fifo Interrupt trigger level
364 // [7:6] -RX---- "01" 4 BYTEs Receiver Fifo Interrupt trigger level
365 // [7:6] -RX---- "10" 8 BYTEs Receiver Fifo Interrupt trigger level
366 // [7:6] -RX---- "11" 14 BYTEs Receiver Fifo Interrupt trigger level
369 // [1:0] -RX-TX- "00" 5 bits in each character
370 // [1:0] -RX-TX- "01" 6 bits in each character
371 // [1:0] -RX-TX- "10" 7 bits in each character
372 // [1:0] -RX-TX- "11" 8 bits in each character
373 // [2] -RX-TX- "0" 1 stop bit
374 // [2] -RX-TX- "1" 1.5 stop bits (when 5 bits of char.) or 2 stop bits (when 6, 7 or 8 bits of char.)
375 // [3] -RX-TX- "1" Parity bit enabled
376 // [5:4] -RX-TX- "00" NO Stick Parity & ODD Parity bit - ODD num. of '1's is transmitted
377 // [5:4] -RX-TX- "01" NO Stick Parity & EVEN Parity bit - EVEN num. of '1's is transmitted
378 // [5:4] -RX-TX- "10" Stick Parity bit - Stick '1' as Parity bit
379 // [5:4] -RX-TX- "11" Stick Parity bit - Stick '0' as Parity bit
380 // [6] ----TX- "1" Break Control - Output is forced to '0'
381 // [7] ------- "1" DLAB - for access to DLL and DLM
384 // [0] -MODEM- "1" Force DTR to '0' - in LoopBack connected to DSR input
385 // [1] -MODEM- "1" Force RTS to '0' - in LoopBack connected to CTS input
386 // [2] -MODEM- "1" Force N.C.1 to '0' - in LoopBack connected to RI input
387 // [3] -MODEM- "1" Force N.C.2 to '0' - in LoopBack connected to DCD input
388 // [4] -MODEM- "1" LoopBack mode
391 // [0] -RX---- "1" Data Ready - At least 1 char. received and is in Fifo----------> READ RBR (Fifo empty)
392 // [1] -RX---- "1" Overrun Error - Fifo full & 1 char. received in shift reg. ----> READ LSR
393 // [2] -RX---- "1" Parity Error - top Fifo char. has invalid parity bit ----------> READ LSR
394 // [3] -RX---- "1" Framing Error - top Fifo char. has invalid stop bit -----------> READ LSR
395 // [4] -RX---- "1" Break Int. - top Fifo char. bits are '0' and it's ctrl. bits --> READ LSR
396 // [5] ----TX- "1" Transmitter Holding Register Empty - transmitter Fifo empty ---> WRITE THR
397 // [6] ----TX- "1" Transmitter EMpTy - transmitter Fifo empty & shift reg. empty -> WRITE THR
398 // [7] -RX---- "1" At least 1 Parity Error, Framing Error or Break Int. in Fifo --> READ LSR & No More Errors in Fifo
401 // [0] -MODEM- "1" Delta CTS indicator - CTS has changed it's state --------------> READ MSR
402 // [1] -MODEM- "1" Delta DSR indicator - DSR has changed it's state --------------> READ MSR
403 // [2] -MODEM- "1" Trailing Edge of RI - RI has changed from '0' to '1' ----------> READ MSR
404 // [3] -MODEM- "1" Delta DCD indicator - DCD has changed it's state --------------> READ MSR
405 // [4] -MODEM- "x" Complement of CTS input | in LoopBack equal to RTS = MCR[1]
406 // [5] -MODEM- "x" Complement of DSR input | in LoopBack equal to DTR = MCR[0]
407 // [6] -MODEM- "x" Complement of RI input | in LoopBack equal to N.C.1 = MCR[2]
408 // [7] -MODEM- "x" Complement of DCD input | in LoopBack equal to N.C.2 = MCR[3]
410 // DLL (R/W | ADR 0 | DLAB 1)
411 // [7:0] ------- "dl[ 7:0]" LSB of DL Reg. written 2. - dl == '0' disables outputs / dl = 1/(T_wb_clk_period*16*BaudRate)
413 // DLM (R/W | ADR 1 | DLAB 1)
414 // [7:0] ------- "dl[15:8]" MSB of DL Reg. written 1. - dl == '0' disables outputs / dl = 1/(T_wb_clk_period*16*BaudRate)
417 // Transparent UART registers
418 assign ier_reg[7:0] = {4'h0, testbench.i_uart_top.regs.ier };
419 assign iir_reg[7:0] = {4'hC, testbench.i_uart_top.regs.iir };
420 assign fcr_reg[7:0] = { testbench.i_uart_top.regs.fcr, 6'h0};
421 assign lcr_reg[7:0] = { testbench.i_uart_top.regs.lcr }; // lcr_reg[7] == DLAB !!!
422 assign mcr_reg[7:0] = {3'h0, testbench.i_uart_top.regs.mcr };
423 assign lsr_reg[7:0] = { testbench.i_uart_top.regs.lsr };
424 assign msr_reg[7:0] = { testbench.i_uart_top.regs.msr };
425 assign dll_reg[7:0] = { testbench.i_uart_top.regs.dl[ 7:0] };
426 assign dlm_reg[7:0] = { testbench.i_uart_top.regs.dl[15:8] };
428 // Tracking changes of registers
466 // Tracking read/write access to registers
467 always@(wbs_cyc_i or wbs_stb_i or wbs_we_i or wbs_sel_i or wbs_adr_i or
468 wbs_dat_i /*or wbs_ack_o*/ /*or posedge wb_clk*/)
470 if (wbs_cyc_i && wbs_stb_i)
472 if (wbs_we_i /*&& wbs_ack_o*/) // WRITE
474 // LOG's example of detecting of register write:
477 // `UART_REG_TR: if (lcr_reg[7]) // lcr_reg[7] == DLAB !!!
478 // -> dll_reg_written;
480 // -> thr_reg_written;
481 // `UART_REG_IE: if (lcr_reg[7]) // lcr_reg[7] == DLAB !!!
482 // -> dlm_reg_written;
484 // -> ier_reg_written;
485 // `UART_REG_FC: -> fcr_reg_written;
486 // `UART_REG_LC: -> lcr_reg_written;
487 // `UART_REG_MC: -> mcr_reg_written;
488 // default: -> erroneous_write_location;
494 reg_dlab = lcr_reg[7];
496 if (~reg_dlab && (reg_adr == `UART_REG_TR)) // write to FIFO
501 always@(wbs_cyc_i or wbs_stb_i or wbs_we_i or wbs_sel_i or wbs_adr_i or
502 wbs_dat_o or wbs_ack_o /*or posedge wb_clk*/)
504 if (wbs_cyc_i && wbs_stb_i)
506 if (~wbs_we_i && wbs_ack_o) // READ
508 // LOG's example of detecting of register read:
511 // `UART_REG_RB: if (lcr_reg[7]) // lcr_reg[7] == DLAB !!!
515 // `UART_REG_IE: if (lcr_reg[7]) // lcr_reg[7] == DLAB !!!
519 // `UART_REG_II: -> iir_reg_read;
520 // `UART_REG_LC: -> lcr_reg_read;
521 // `UART_REG_LS: -> lsr_reg_read;
522 // `UART_REG_MS: -> msr_reg_read;
523 // default: -> erroneous_read_location;
529 reg_dlab = lcr_reg[7];
531 if (~reg_dlab && (reg_adr == `UART_REG_RB))
538 // UART register monitor
539 //#######################
541 // Line Status Register
542 // Reading LSR register
549 if (reg_adr == `UART_REG_LS)
552 repeat (1) @(posedge wb_clk);
557 // Bit 0 - Data Ready
560 lsr_reg_bit0_change_allowed = 0;
564 begin: rx_fifo_status_changing
567 if (rx_fifo_status == 0)
569 wait (rx_fifo_status > 0);
570 lsr_reg_bit0_change_allowed = 1'b1;
571 repeat (1) @(posedge wb_clk);
573 lsr_reg_bit0_change_allowed = 0;
576 `BENCH_ERROR("Bit 0 of LSR register not '1'!");
582 wait (rx_fifo_status == 0);
583 lsr_reg_bit0_change_allowed = 1'b1;
584 repeat (1) @(posedge wb_clk);
586 lsr_reg_bit0_change_allowed = 0;
589 `BENCH_ERROR("Bit 0 of LSR register not '0'!");
595 begin: lsr_reg_bit0_changing
598 wait (~lsr_reg_bit0_change_allowed);
600 @(lsr_reg[0] or lsr_reg_bit0_change_allowed);
601 if (~lsr_reg_bit0_change_allowed)
603 `BENCH_ERROR("Bit 0 of LSR register should not change!");
611 // Bit 1 - Overrun Error
614 lsr_reg_bit1_change_allowed = 0;
618 begin: rx_overrun_err_occured_changing
621 if (~rx_overrun_err_occured)
623 wait (rx_overrun_err_occured);
624 lsr_reg_bit1_change_allowed = 1'b1;
625 repeat (1) @(posedge wb_clk);
627 lsr_reg_bit1_change_allowed = 0;
630 `BENCH_ERROR("Bit 1 of LSR register not '1'!");
637 lsr_reg_bit1_change_allowed = 1'b1;
638 repeat (1) @(posedge wb_clk);
640 lsr_reg_bit1_change_allowed = 0;
641 rx_overrun_err_occured = 0;
644 `BENCH_ERROR("Bit 1 of LSR register not '0'!");
650 begin: lsr_reg_bit1_changing
653 wait (~lsr_reg_bit1_change_allowed);
655 @(lsr_reg[1] or lsr_reg_bit1_change_allowed);
656 if (~lsr_reg_bit1_change_allowed)
658 `BENCH_ERROR("Bit 1 of LSR register should not change!");
666 // Bit 2 - Parity Error
669 lsr_reg_bit2_change_allowed = 0;
670 rx_fifo_par_rd_pointer = 0;
674 begin: rx_parity_err_changing
677 if (~rx_fifo_par[rx_fifo_par_rd_pointer])
680 lsr_reg_bit2_change_allowed = 1'b1;
681 repeat (1) @(posedge wb_clk);
683 lsr_reg_bit2_change_allowed = 0;
684 rx_fifo_par_rd_pointer = rx_fifo_par_rd_pointer + 1'b1;
686 if (~lsr_reg[2] && rx_fifo_par[rx_fifo_par_rd_pointer])
688 `BENCH_ERROR("Bit 2 of LSR register not '1'!");
691 else if (lsr_reg[2] && ~rx_fifo_par[rx_fifo_par_rd_pointer])
693 `BENCH_ERROR("Bit 2 of LSR register not '0'!");
700 lsr_reg_bit2_change_allowed = 1'b1;
701 repeat (1) @(posedge wb_clk);
703 lsr_reg_bit2_change_allowed = 0;
704 if (rx_fifo_par_rd_pointer < rx_fifo_rd_pointer)
706 for (i2 = rx_fifo_par_rd_pointer; i2 <= rx_fifo_rd_pointer; i2 = i2 + 1)
708 rx_fifo_par_rd_pointer = rx_fifo_rd_pointer;
710 else if (rx_fifo_par_rd_pointer > rx_fifo_rd_pointer)
712 for (i2 = rx_fifo_par_rd_pointer; i2 <= 31; i2 = i2 + 1)
714 for (i2 = 0; i2 <= rx_fifo_rd_pointer; i2 = i2 + 1)
716 rx_fifo_par_rd_pointer = rx_fifo_rd_pointer;
721 rx_fifo_par_rd_pointer = rx_fifo_rd_pointer;
724 if (~lsr_reg[2] && rx_fifo_par[rx_fifo_par_rd_pointer])
726 `BENCH_ERROR("Bit 2 of LSR register not '1'!");
729 else if (lsr_reg[2] && ~rx_fifo_par[rx_fifo_par_rd_pointer])
731 `BENCH_ERROR("Bit 2 of LSR register not '0'!");
737 begin: lsr_reg_bit2_changing
740 wait (~lsr_reg_bit2_change_allowed);
742 @(lsr_reg[2] or lsr_reg_bit2_change_allowed);
743 if (~lsr_reg_bit2_change_allowed)
745 `BENCH_ERROR("Bit 2 of LSR register should not change!");
753 // Bit 3 - Framing Error
756 lsr_reg_bit3_change_allowed = 0;
757 rx_fifo_frm_rd_pointer = 0;
761 begin: rx_framing_err_changing
764 if (~rx_fifo_frm[rx_fifo_frm_rd_pointer])
767 lsr_reg_bit3_change_allowed = 1'b1;
768 repeat (1) @(posedge wb_clk);
770 lsr_reg_bit3_change_allowed = 0;
771 rx_fifo_frm_rd_pointer = rx_fifo_frm_rd_pointer + 1'b1;
773 if (~lsr_reg[3] && rx_fifo_frm[rx_fifo_frm_rd_pointer])
775 `BENCH_ERROR("Bit 3 of LSR register not '1'!");
778 else if (lsr_reg[3] && ~rx_fifo_frm[rx_fifo_frm_rd_pointer])
780 `BENCH_ERROR("Bit 3 of LSR register not '0'!");
787 lsr_reg_bit3_change_allowed = 1'b1;
788 repeat (1) @(posedge wb_clk);
790 lsr_reg_bit3_change_allowed = 0;
791 if (rx_fifo_frm_rd_pointer < rx_fifo_rd_pointer)
793 for (i3 = rx_fifo_frm_rd_pointer; i3 <= rx_fifo_rd_pointer; i3 = i3 + 1)
795 rx_fifo_frm_rd_pointer = rx_fifo_rd_pointer;
797 else if (rx_fifo_frm_rd_pointer > rx_fifo_rd_pointer)
799 for (i3 = rx_fifo_frm_rd_pointer; i3 <= 31; i3 = i3 + 1)
801 for (i3 = 0; i3 <= rx_fifo_rd_pointer; i3 = i3 + 1)
803 rx_fifo_frm_rd_pointer = rx_fifo_rd_pointer;
808 rx_fifo_frm_rd_pointer = rx_fifo_rd_pointer;
811 if (~lsr_reg[3] && rx_fifo_frm[rx_fifo_frm_rd_pointer])
813 `BENCH_ERROR("Bit 3 of LSR register not '1'!");
816 else if (lsr_reg[3] && ~rx_fifo_frm[rx_fifo_frm_rd_pointer])
818 `BENCH_ERROR("Bit 3 of LSR register not '0'!");
824 begin: lsr_reg_bit3_changing
827 wait (~lsr_reg_bit3_change_allowed);
829 @(lsr_reg[3] or lsr_reg_bit3_change_allowed);
830 if (~lsr_reg_bit3_change_allowed)
832 `BENCH_ERROR("Bit 3 of LSR register should not change!");
840 // Bit 4 - Break Interrupt
843 lsr_reg_bit4_change_allowed = 0;
844 rx_fifo_brk_rd_pointer = 0;
848 begin: rx_break_int_changing
851 if (~rx_fifo_brk[rx_fifo_brk_rd_pointer])
854 lsr_reg_bit4_change_allowed = 1'b1;
855 repeat (1) @(posedge wb_clk);
857 lsr_reg_bit4_change_allowed = 0;
858 rx_fifo_brk_rd_pointer = rx_fifo_brk_rd_pointer + 1'b1;
860 if (~lsr_reg[4] && rx_fifo_brk[rx_fifo_brk_rd_pointer])
862 `BENCH_ERROR("Bit 4 of LSR register not '1'!");
865 else if (lsr_reg[4] && ~rx_fifo_brk[rx_fifo_brk_rd_pointer])
867 `BENCH_ERROR("Bit 4 of LSR register not '0'!");
874 lsr_reg_bit4_change_allowed = 1'b1;
875 repeat (1) @(posedge wb_clk);
877 lsr_reg_bit4_change_allowed = 0;
878 if (rx_fifo_brk_rd_pointer < rx_fifo_rd_pointer)
880 for (i4 = rx_fifo_brk_rd_pointer; i4 <= rx_fifo_rd_pointer; i4 = i4 + 1)
882 rx_fifo_brk_rd_pointer = rx_fifo_rd_pointer;
884 else if (rx_fifo_brk_rd_pointer > rx_fifo_rd_pointer)
886 for (i4 = rx_fifo_brk_rd_pointer; i4 <= 31; i4 = i4 + 1)
888 for (i4 = 0; i4 <= rx_fifo_rd_pointer; i4 = i4 + 1)
890 rx_fifo_brk_rd_pointer = rx_fifo_rd_pointer;
895 rx_fifo_brk_rd_pointer = rx_fifo_rd_pointer;
898 if (~lsr_reg[4] && rx_fifo_brk[rx_fifo_brk_rd_pointer])
900 `BENCH_ERROR("Bit 4 of LSR register not '1'!");
903 else if (lsr_reg[4] && ~rx_fifo_brk[rx_fifo_brk_rd_pointer])
905 `BENCH_ERROR("Bit 4 of LSR register not '0'!");
911 begin: lsr_reg_bit4_changing
914 wait (~lsr_reg_bit4_change_allowed);
916 @(lsr_reg[4] or lsr_reg_bit4_change_allowed);
917 if (~lsr_reg_bit4_change_allowed)
919 `BENCH_ERROR("Bit 4 of LSR register should not change!");
927 // Bit 5 - Transmitter Holding Register Empty
930 lsr_reg_bit5_change_allowed = 0;
934 begin: tx_fifo_status_changing
937 if (tx_fifo_status == 0)
939 // @(tx_reg_written);
940 wait (tx_fifo_status > 0);
941 lsr_reg_bit5_change_allowed = 1'b1;
942 repeat (3) @(posedge wb_clk);
944 lsr_reg_bit5_change_allowed = 0;
947 `BENCH_ERROR("Bit 5 of LSR register not '0'!");
953 wait (tx_fifo_status == 0);
954 lsr_reg_bit5_change_allowed = 1'b1;
955 repeat (3) @(posedge wb_clk);
957 lsr_reg_bit5_change_allowed = 0;
960 `BENCH_ERROR("Bit 5 of LSR register not '1'!");
966 begin: lsr_reg_bit5_changing
969 wait (~lsr_reg_bit5_change_allowed);
971 @(lsr_reg[5] or lsr_reg_bit5_change_allowed);
972 if (~lsr_reg_bit5_change_allowed)
974 `BENCH_ERROR("Bit 5 of LSR register should not change!");
982 // Bit 6 - Transmitter Empty
985 lsr_reg_bit6_change_allowed = 0;
989 begin: tx_fifo_status_and_shift_reg_changing
992 if ((tx_fifo_status == 0) && tx_shift_reg_empty)
994 // @(tx_reg_written);
995 wait (tx_fifo_status > 0);
996 lsr_reg_bit6_change_allowed = 1'b1;
997 repeat (3) @(posedge wb_clk);
999 lsr_reg_bit6_change_allowed = 0;
1002 `BENCH_ERROR("Bit 6 of LSR register not '0'!");
1008 wait ((tx_fifo_status == 0) && tx_shift_reg_empty);
1009 lsr_reg_bit6_change_allowed = 1'b1;
1010 repeat (3) @(posedge wb_clk);
1012 lsr_reg_bit6_change_allowed = 0;
1015 `BENCH_ERROR("Bit 6 of LSR register not '1'!");
1021 begin: lsr_reg_bit6_changing
1024 wait (~lsr_reg_bit6_change_allowed);
1026 @(lsr_reg[6] or lsr_reg_bit6_change_allowed);
1027 if (~lsr_reg_bit6_change_allowed)
1029 `BENCH_ERROR("Bit 6 of LSR register should not change!");
1037 // Bit 7 - Error in RX FIFO
1040 lsr_reg_bit7_change_allowed = 0;
1044 begin: error_changing
1047 if ((rx_fifo_par == 0) && (rx_fifo_frm == 0) && (rx_fifo_brk == 0))
1049 wait (rx_parity_err || rx_framing_err || rx_framing_glitch || rx_break_int);
1050 lsr_reg_bit7_change_allowed = 1'b1;
1051 repeat (3) @(posedge wb_clk);
1053 lsr_reg_bit7_change_allowed = 0;
1057 `BENCH_ERROR("Bit 7 of LSR register not '1'!");
1063 wait (lsr_reg_read && (rx_fifo_par == 0) && (rx_fifo_frm == 0) && (rx_fifo_brk == 0));
1064 lsr_reg_bit7_change_allowed = 1'b1;
1065 repeat (2) @(posedge wb_clk);
1067 lsr_reg_bit7_change_allowed = 0;
1071 `BENCH_ERROR("Bit 7 of LSR register not '0'!");
1077 begin: lsr_reg_bit7_changing
1080 wait (~lsr_reg_bit7_change_allowed);
1082 @(lsr_reg[7] or lsr_reg_bit7_change_allowed);
1083 if (~lsr_reg_bit7_change_allowed)
1085 `BENCH_ERROR("Bit 7 of LSR register should not change!");
1095 // UART transmitter monitor
1096 //#########################
1099 always@(tx_fifo_wr_pointer or tx_fifo_rd_pointer)
1101 if (tx_fifo_wr_pointer >= tx_fifo_rd_pointer)
1102 tx_fifo_status = tx_fifo_wr_pointer - tx_fifo_rd_pointer;
1104 tx_fifo_status = (5'h1F - tx_fifo_rd_pointer) + tx_fifo_wr_pointer;
1106 // TX FIFO and TX data
1109 tx_fifo_wr_pointer = 0;
1110 tx_fifo_rd_pointer = 0;
1111 tx_shift_reg_empty = 1;
1113 tx_start_bit_edge = 1;
1115 begin:write_tx_shift_reg_read_tx_fifo
1118 wait ((tx_fifo_status !== 0) && tx_shift_reg_empty && tx_start_bit_edge && ~stx_pad_o);
1119 tx_start_bit_edge = 0;
1120 tx_shift_reg = tx_fifo[tx_fifo_rd_pointer];
1121 tx_shift_reg_empty = 0;
1122 @(testbench.i_uart_device.device_received_last_bit);
1123 repeat (16393) @(posedge wb_clk);
1124 tx_fifo_rd_pointer = tx_fifo_rd_pointer + 1'b1;
1126 if (tx_fifo_status == 0)
1128 `BENCH_MSG("TX FIFO is empty!");
1135 @(tx_reg_written); // write to FIFO
1136 repeat (1) @(posedge wb_clk); // delay when writing into registers
1137 if (tx_fifo_status <= 5'h0F)
1139 tx_fifo[tx_fifo_wr_pointer] = reg_dat;
1140 tx_fifo_wr_pointer = tx_fifo_wr_pointer + 1'b1;
1142 else // FIFO overflow
1144 `BENCH_WARNING("TX FIFO overflow!");
1152 tx_fifo_wr_pointer = 0;
1153 tx_fifo_rd_pointer = 0;
1155 if (tx_fifo_status == 0)
1157 `BENCH_MSG("TX FIFO is empty!");
1161 begin:read_tx_shift_reg
1164 @(testbench.i_uart_device.device_received_packet);
1166 if (tx_shift_reg != testbench.i_uart_device.rx_data)
1168 `BENCH_ERROR("TX data has ERROR!");
1172 `BENCH_MSG("TX data correct!");
1173 if (testbench.i_uart_device.rx_parity_error)
1175 `BENCH_ERROR("TX data has parity ERROR!");
1179 `BENCH_MSG("TX data parity correct!");
1180 if (testbench.i_uart_device.rx_framing_error)
1182 `BENCH_ERROR("TX data has framing ERROR!");
1186 `BENCH_MSG("TX data framing correct!");
1187 // Set TX FIFO read pointer
1188 tx_start_bit_edge = 1;
1189 repeat (7) @(wb_clk);
1190 if (tx_shift_reg_empty == 0)
1192 tx_shift_reg_empty = 1'b1;
1196 `BENCH_ERROR("TX shift register empty while transmiting data!");
1205 // UART receiver monitor
1206 //######################
1209 always@(rx_fifo_wr_pointer or rx_fifo_rd_pointer)
1211 if (rx_fifo_wr_pointer >= rx_fifo_rd_pointer)
1212 rx_fifo_status = rx_fifo_wr_pointer - rx_fifo_rd_pointer;
1214 rx_fifo_status = (5'h1F - rx_fifo_rd_pointer) + rx_fifo_wr_pointer;
1216 // RX FIFO and RX data
1221 rx_framing_glitch = 0;
1223 rx_overrun_err_occured = 0;
1227 rx_shift_reg_full = 0;
1228 rx_fifo_wr_pointer = 0;
1229 rx_fifo_rd_pointer = 0;
1232 begin:write_rx_shift_reg
1235 @(testbench.i_uart_device.device_sent_packet);
1236 repeat (1) @(posedge wb_clk);
1237 rx_shift_reg = testbench.i_uart_device.sent_data;
1238 rx_parity_err = testbench.i_uart_device.tx_parity_enabled &&
1239 (testbench.i_uart_device.tx_parity_wrong ||
1240 ( // sample point is BIT_NUM * 2 - 1 => 3, 5, 7...
1241 ((testbench.i_uart_device.tx_glitch_num == (3 * 8 * testbench.i_uart_device.T_divisor)) ||
1242 (testbench.i_uart_device.tx_glitch_num == (5 * 8 * testbench.i_uart_device.T_divisor)) ||
1243 (testbench.i_uart_device.tx_glitch_num == (7 * 8 * testbench.i_uart_device.T_divisor)) ||
1244 (testbench.i_uart_device.tx_glitch_num == (9 * 8 * testbench.i_uart_device.T_divisor)) ||
1245 (testbench.i_uart_device.tx_glitch_num == (11 * 8 * testbench.i_uart_device.T_divisor)) ||
1246 (testbench.i_uart_device.tx_glitch_num == (13 * 8 * testbench.i_uart_device.T_divisor)) ||
1247 (testbench.i_uart_device.tx_glitch_num == (15 * 8 * testbench.i_uart_device.T_divisor)) ||
1248 (testbench.i_uart_device.tx_glitch_num == (17 * 8 * testbench.i_uart_device.T_divisor)) ||
1249 (testbench.i_uart_device.tx_glitch_num == (19 * 8 * testbench.i_uart_device.T_divisor)) ||
1250 (testbench.i_uart_device.tx_glitch_num == (21 * 8 * testbench.i_uart_device.T_divisor)) ||
1251 (testbench.i_uart_device.tx_glitch_num == (23 * 8 * testbench.i_uart_device.T_divisor))) &&
1252 (testbench.i_uart_device.tx_glitch_num[23:0] < ((testbench.i_uart_device.tx_length + 2'h1) *
1253 16 * testbench.i_uart_device.T_divisor))
1255 rx_framing_err = testbench.i_uart_device.tx_framing_wrong;
1256 rx_framing_glitch = (testbench.i_uart_device.tx_glitch_num == ((((testbench.i_uart_device.tx_length + 2'h2 +
1257 testbench.i_uart_device.tx_parity_enabled) *
1258 2) - 1'b1) * 8 * testbench.i_uart_device.T_divisor));
1259 rx_break_int = testbench.i_uart_device.tx_break_enable &&
1260 (testbench.i_uart_device.tx_break_num[15:0] >= ((testbench.i_uart_device.tx_length + 2'h2 +
1261 testbench.i_uart_device.tx_parity_enabled) *
1262 16 * testbench.i_uart_device.T_divisor));
1263 -> testbench.i_uart_device.sent_packet_received;
1264 if (rx_fifo_status > 5'h0F)
1265 rx_overrun_err_occured = 1'b1;
1266 rx_shift_reg_full = 1'b1;
1269 begin:write_rx_fifo_read_rx_shift_reg
1272 wait (rx_shift_reg_full);
1273 if (rx_fifo_status <= 5'h0F)
1275 rx_fifo_data[rx_fifo_wr_pointer] = testbench.i_uart_device.sent_data;
1276 rx_fifo_par[rx_fifo_wr_pointer] = rx_parity_err;
1277 rx_fifo_frm[rx_fifo_wr_pointer] = rx_framing_err || rx_framing_glitch;
1278 rx_fifo_brk[rx_fifo_wr_pointer] = rx_break_int;
1279 rx_fifo_wr_pointer = rx_fifo_wr_pointer + 1'b1;
1281 else // FIFO overflow
1283 `BENCH_WARNING("RX FIFO overflow!");
1285 repeat (1) @(posedge wb_clk);
1286 rx_shift_reg_full = 0;
1293 rx_fifo_wr_pointer = 0;
1294 rx_fifo_rd_pointer = 0;
1299 if (rx_fifo_status == 0)
1301 `BENCH_MSG("RX FIFO is empty!");
1310 if (rx_fifo_status > 0)
1312 rx_fifo_read = 1'b1;
1314 if (rx_fifo_data[rx_fifo_rd_pointer] != reg_dat)
1316 `BENCH_ERROR("RX data has ERROR!");
1321 `BENCH_MSG("RX data correct!");
1323 // Set RX FIFO read pointer
1324 repeat (1) @(posedge wb_clk);
1326 rx_fifo_rd_pointer = rx_fifo_rd_pointer + 1'b1;
1330 `BENCH_WARNING("Reading RX FIFO while RX FIFO is empty!");
1334 if ((~rx_fifo_frm[rx_fifo_rd_pointer] && lsr_reg[3]) ||
1335 (rx_fifo_frm[rx_fifo_rd_pointer] && ~lsr_reg[3]))
1337 `BENCH_ERROR("RX data has wrong framing ERROR!");
1341 `BENCH_MSG("RX data has correct framing error!");
1342 // Set RX FIFO read pointer
1343 repeat (1) @(posedge wb_clk);
1345 if (rx_fifo_status > 0)
1347 // rx_fifo_par[rx_fifo_rd_pointer] = 1'b0;
1348 // rx_fifo_frm[rx_fifo_rd_pointer] = 1'b0;
1349 // rx_fifo_brk[rx_fifo_rd_pointer] = 1'b0;
1350 rx_fifo_rd_pointer = rx_fifo_rd_pointer + 1'b1;
1358 // UART interrupt monitor
1359 //#######################