1 //////////////////////////////////////////////////////////////////////
5 //// This file is part of the SPI IP core project ////
6 //// http://www.opencores.org/projects/spi/ ////
9 //// - Simon Srot (simons@opencores.org) ////
11 //// All additional information is avaliable in the Readme.txt ////
14 //////////////////////////////////////////////////////////////////////
16 //// Copyright (C) 2002 Authors ////
18 //// This source file may be used and distributed without ////
19 //// restriction provided that this copyright statement is not ////
20 //// removed from the file and that any derivative work contains ////
21 //// the original copyright notice and the associated disclaimer. ////
23 //// This source file is free software; you can redistribute it ////
24 //// and/or modify it under the terms of the GNU Lesser General ////
25 //// Public License as published by the Free Software Foundation; ////
26 //// either version 2.1 of the License, or (at your option) any ////
27 //// later version. ////
29 //// This source is distributed in the hope that it will be ////
30 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
31 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
32 //// PURPOSE. See the GNU Lesser General Public License for more ////
35 //// You should have received a copy of the GNU Lesser General ////
36 //// Public License along with this source; if not, download it ////
37 //// from http://www.opencores.org/lgpl.shtml ////
39 //////////////////////////////////////////////////////////////////////
42 // Number of bits used for devider register. If used in system with
43 // low frequency of system clock this can be reduced.
44 // Use SPI_DIVIDER_LEN for fine tuning theexact number.
46 //`define SPI_DIVIDER_LEN_8
47 `define SPI_DIVIDER_LEN_16
48 //`define SPI_DIVIDER_LEN_24
49 //`define SPI_DIVIDER_LEN_32
51 `ifdef SPI_DIVIDER_LEN_8
52 `define SPI_DIVIDER_LEN 8 // Can be set from 1 to 8
54 `ifdef SPI_DIVIDER_LEN_16
55 `define SPI_DIVIDER_LEN 16 // Can be set from 9 to 16
57 `ifdef SPI_DIVIDER_LEN_24
58 `define SPI_DIVIDER_LEN 24 // Can be set from 17 to 24
60 `ifdef SPI_DIVIDER_LEN_32
61 `define SPI_DIVIDER_LEN 32 // Can be set from 25 to 32
65 // Maximum nuber of bits that can be send/received at once.
66 // Use SPI_MAX_CHAR for fine tuning the exact number, when using
67 // SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8.
69 `define SPI_MAX_CHAR_128
70 //`define SPI_MAX_CHAR_64
71 //`define SPI_MAX_CHAR_32
72 //`define SPI_MAX_CHAR_24
73 //`define SPI_MAX_CHAR_16
74 //`define SPI_MAX_CHAR_8
76 `ifdef SPI_MAX_CHAR_128
77 `define SPI_MAX_CHAR 128 // Can only be set to 128
78 `define SPI_CHAR_LEN_BITS 7
80 `ifdef SPI_MAX_CHAR_64
81 `define SPI_MAX_CHAR 64 // Can only be set to 64
82 `define SPI_CHAR_LEN_BITS 6
84 `ifdef SPI_MAX_CHAR_32
85 `define SPI_MAX_CHAR 32 // Can be set from 25 to 32
86 `define SPI_CHAR_LEN_BITS 5
88 `ifdef SPI_MAX_CHAR_24
89 `define SPI_MAX_CHAR 24 // Can be set from 17 to 24
90 `define SPI_CHAR_LEN_BITS 5
92 `ifdef SPI_MAX_CHAR_16
93 `define SPI_MAX_CHAR 16 // Can be set from 9 to 16
94 `define SPI_CHAR_LEN_BITS 4
97 `define SPI_MAX_CHAR 8 // Can be set from 1 to 8
98 `define SPI_CHAR_LEN_BITS 3
102 // Number of device select signals. Use SPI_SS_NB for fine tuning the
106 //`define SPI_SS_NB_16
107 //`define SPI_SS_NB_24
108 //`define SPI_SS_NB_32
111 `define SPI_SS_NB 8 // Can be set from 1 to 8
114 `define SPI_SS_NB 16 // Can be set from 9 to 16
117 `define SPI_SS_NB 24 // Can be set from 17 to 24
120 `define SPI_SS_NB 32 // Can be set from 25 to 32
124 // Bits of WISHBONE address used for partial decoding of SPI registers.
126 `define SPI_OFS_BITS 4:2
144 // Number of bits in ctrl register
146 `define SPI_CTRL_BIT_NB 14
149 // Control register bit position
151 `define SPI_CTRL_ASS 13
152 `define SPI_CTRL_IE 12
153 `define SPI_CTRL_LSB 11
154 `define SPI_CTRL_TX_NEGEDGE 10
155 `define SPI_CTRL_RX_NEGEDGE 9
156 `define SPI_CTRL_GO 8
157 `define SPI_CTRL_RES_1 7
158 `define SPI_CTRL_CHAR_LEN 6:0