git.gag.com Git - debian/gnuradio/blob - usrp2/fpga/opencores/sd_interface/RTL/spiCtrl.v

   1 \r
   2 //////////////////////////////////////////////////////////////////////\r
   3 ////                                                              ////\r
   4 //// spiCtrl.v                                                 ////\r
   5 ////                                                              ////\r
   6 //// This file is part of the spiMaster opencores effort.\r
   7 //// <http://www.opencores.org/cores//>                           ////\r
   8 ////                                                              ////\r
   9 //// Module Description:                                          ////\r
  10 ////  parameterized dual clock domain fifo. \r
  11 ////  fifo depth is restricted to 2^ADDR_WIDTH\r
  12 ////  No protection against over runs and under runs.\r
  13 //// \r
  14 ////                                                              ////\r
  15 //// To Do:                                                       ////\r
  16 //// \r
  17 ////                                                              ////\r
  18 //// Author(s):                                                   ////\r
  19 //// - Steve Fielding, sfielding@base2designs.com                 ////\r
  20 ////                                                              ////\r
  21 //////////////////////////////////////////////////////////////////////\r
  22 ////                                                              ////\r
  23 //// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////\r
  24 ////                                                              ////\r
  25 //// This source file may be used and distributed without         ////\r
  26 //// restriction provided that this copyright statement is not    ////\r
  27 //// removed from the file and that any derivative work contains  ////\r
  28 //// the original copyright notice and the associated disclaimer. ////\r
  29 ////                                                              ////\r
  30 //// This source file is free software; you can redistribute it   ////\r
  31 //// and/or modify it under the terms of the GNU Lesser General   ////\r
  32 //// Public License as published by the Free Software Foundation; ////\r
  33 //// either version 2.1 of the License, or (at your option) any   ////\r
  34 //// later version.                                               ////\r
  35 ////                                                              ////\r
  36 //// This source is distributed in the hope that it will be       ////\r
  37 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\r
  38 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\r
  39 //// PURPOSE. See the GNU Lesser General Public License for more  ////\r
  40 //// details.                                                     ////\r
  41 ////                                                              ////\r
  42 //// You should have received a copy of the GNU Lesser General    ////\r
  43 //// Public License along with this source; if not, download it   ////\r
  44 //// from <http://www.opencores.org/lgpl.shtml>                   ////\r
  45 ////                                                              ////\r
  46 //////////////////////////////////////////////////////////////////////\r
  47 //\r
  48 `include "timescale.v"\r
  49 `include "spiMaster_defines.v"\r
  50 \r
  51 module spiCtrl (clk, readWriteSDBlockRdy, readWriteSDBlockReq, rst, rxDataRdy, rxDataRdyClr, SDInitRdy, SDInitReq, spiCS_n, spiTransCtrl, spiTransSts, spiTransType, txDataWen);\r
  52 input   clk;\r
  53 input   readWriteSDBlockRdy;\r
  54 input   rst;\r
  55 input   rxDataRdy;\r
  56 input   SDInitRdy;\r
  57 input   spiTransCtrl;\r
  58 input   [1:0]spiTransType;\r
  59 output  [1:0]readWriteSDBlockReq;\r
  60 output  rxDataRdyClr;\r
  61 output  SDInitReq;\r
  62 output  spiCS_n;\r
  63 output  spiTransSts;\r
  64 output  txDataWen;\r
  65 \r
  66 wire    clk;\r
  67 wire    readWriteSDBlockRdy;\r
  68 reg     [1:0]readWriteSDBlockReq, next_readWriteSDBlockReq;\r
  69 wire    rst;\r
  70 wire    rxDataRdy;\r
  71 reg     rxDataRdyClr, next_rxDataRdyClr;\r
  72 wire    SDInitRdy;\r
  73 reg     SDInitReq, next_SDInitReq;\r
  74 reg     spiCS_n, next_spiCS_n;\r
  75 wire    spiTransCtrl;\r
  76 reg     spiTransSts, next_spiTransSts;\r
  77 wire    [1:0]spiTransType;\r
  78 reg     txDataWen, next_txDataWen;\r
  79 \r
  80 // BINARY ENCODED state machine: spiCtrlSt\r
  81 // State codes definitions:\r
  82 `define ST_S_CTRL 3'b000\r
  83 `define WT_S_CTRL_REQ 3'b001\r
  84 `define WT_FIN1 3'b010\r
  85 `define DIR_ACC 3'b011\r
  86 `define INIT 3'b100\r
  87 `define WT_FIN2 3'b101\r
  88 `define RW 3'b110\r
  89 `define WT_FIN3 3'b111\r
  90 \r
  91 reg [2:0]CurrState_spiCtrlSt, NextState_spiCtrlSt;\r
  92 \r
  93 // Diagram actions (continuous assignments allowed only: assign ...)\r
  94 // diagram ACTION\r
  95 \r
  96 \r
  97 // Machine: spiCtrlSt\r
  98 \r
  99 // NextState logic (combinatorial)\r
 100 always @ (spiTransCtrl or rxDataRdy or spiTransType or SDInitRdy or readWriteSDBlockRdy or readWriteSDBlockReq or txDataWen or SDInitReq or rxDataRdyClr or spiTransSts or spiCS_n or CurrState_spiCtrlSt)\r
 101 begin\r
 102   NextState_spiCtrlSt <= CurrState_spiCtrlSt;\r
 103   // Set default values for outputs and signals\r
 104   next_readWriteSDBlockReq <= readWriteSDBlockReq;\r
 105   next_txDataWen <= txDataWen;\r
 106   next_SDInitReq <= SDInitReq;\r
 107   next_rxDataRdyClr <= rxDataRdyClr;\r
 108   next_spiTransSts <= spiTransSts;\r
 109   next_spiCS_n <= spiCS_n;\r
 110   case (CurrState_spiCtrlSt)  // synopsys parallel_case full_case\r
 111     `ST_S_CTRL:\r
 112     begin\r
 113       next_readWriteSDBlockReq <= `NO_BLOCK_REQ;\r
 114       next_txDataWen <= 1'b0;\r
 115       next_SDInitReq <= 1'b0;\r
 116       next_rxDataRdyClr <= 1'b0;\r
 117       next_spiTransSts <= `TRANS_NOT_BUSY;\r
 118       next_spiCS_n <= 1'b1;\r
 119       NextState_spiCtrlSt <= `WT_S_CTRL_REQ;\r
 120     end\r
 121     `WT_S_CTRL_REQ:\r
 122     begin\r
 123       next_rxDataRdyClr <= 1'b0;\r
 124       next_spiTransSts <= `TRANS_NOT_BUSY;\r
 125       if ((spiTransCtrl == `TRANS_START) && (spiTransType == `INIT_SD))\r
 126       begin\r
 127         NextState_spiCtrlSt <= `INIT;\r
 128         next_spiTransSts <= `TRANS_BUSY;\r
 129         next_SDInitReq <= 1'b1;\r
 130       end\r
 131       else if ((spiTransCtrl == `TRANS_START) && (spiTransType == `RW_WRITE_SD_BLOCK))\r
 132       begin\r
 133         NextState_spiCtrlSt <= `RW;\r
 134         next_spiTransSts <= `TRANS_BUSY;\r
 135         next_readWriteSDBlockReq <= `WRITE_SD_BLOCK;\r
 136       end\r
 137       else if ((spiTransCtrl == `TRANS_START) && (spiTransType == `RW_READ_SD_BLOCK))\r
 138       begin\r
 139         NextState_spiCtrlSt <= `RW;\r
 140         next_spiTransSts <= `TRANS_BUSY;\r
 141         next_readWriteSDBlockReq <= `READ_SD_BLOCK;\r
 142       end\r
 143       else if ((spiTransCtrl == `TRANS_START) && (spiTransType == `DIRECT_ACCESS))\r
 144       begin\r
 145         NextState_spiCtrlSt <= `DIR_ACC;\r
 146         next_spiTransSts <= `TRANS_BUSY;\r
 147         next_txDataWen <= 1'b1;\r
 148         next_spiCS_n <= 1'b0;\r
 149       end\r
 150     end\r
 151     `WT_FIN1:\r
 152     begin\r
 153       if (rxDataRdy == 1'b1)\r
 154       begin\r
 155         NextState_spiCtrlSt <= `WT_S_CTRL_REQ;\r
 156         next_rxDataRdyClr <= 1'b1;\r
 157         next_spiCS_n <= 1'b1;\r
 158       end\r
 159     end\r
 160     `DIR_ACC:\r
 161     begin\r
 162       next_txDataWen <= 1'b0;\r
 163       NextState_spiCtrlSt <= `WT_FIN1;\r
 164     end\r
 165     `INIT:\r
 166     begin\r
 167       next_SDInitReq <= 1'b0;\r
 168       NextState_spiCtrlSt <= `WT_FIN2;\r
 169     end\r
 170     `WT_FIN2:\r
 171     begin\r
 172       if (SDInitRdy == 1'b1)\r
 173       begin\r
 174         NextState_spiCtrlSt <= `WT_S_CTRL_REQ;\r
 175       end\r
 176     end\r
 177     `RW:\r
 178     begin\r
 179       next_readWriteSDBlockReq <= `NO_BLOCK_REQ;\r
 180       NextState_spiCtrlSt <= `WT_FIN3;\r
 181     end\r
 182     `WT_FIN3:\r
 183     begin\r
 184       if (readWriteSDBlockRdy == 1'b1)\r
 185       begin\r
 186         NextState_spiCtrlSt <= `WT_S_CTRL_REQ;\r
 187       end\r
 188     end\r
 189   endcase\r
 190 end\r
 191 \r
 192 // Current State Logic (sequential)\r
 193 always @ (posedge clk)\r
 194 begin\r
 195   if (rst == 1'b1)\r
 196     CurrState_spiCtrlSt <= `ST_S_CTRL;\r
 197   else\r
 198     CurrState_spiCtrlSt <= NextState_spiCtrlSt;\r
 199 end\r
 200 \r
 201 // Registered outputs logic\r
 202 always @ (posedge clk)\r
 203 begin\r
 204   if (rst == 1'b1)\r
 205   begin\r
 206     readWriteSDBlockReq <= `NO_BLOCK_REQ;\r
 207     txDataWen <= 1'b0;\r
 208     SDInitReq <= 1'b0;\r
 209     rxDataRdyClr <= 1'b0;\r
 210     spiTransSts <= `TRANS_NOT_BUSY;\r
 211     spiCS_n <= 1'b1;\r
 212   end\r
 213   else \r
 214   begin\r
 215     readWriteSDBlockReq <= next_readWriteSDBlockReq;\r
 216     txDataWen <= next_txDataWen;\r
 217     SDInitReq <= next_SDInitReq;\r
 218     rxDataRdyClr <= next_rxDataRdyClr;\r
 219     spiTransSts <= next_spiTransSts;\r
 220     spiCS_n <= next_spiCS_n;\r
 221   end\r
 222 end\r
 223 \r
 224 endmodule