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   1 /*
   2 /////////////////////////////////////////////////////////////////////
   3 ////                                                             ////
   4 ////  Include file for OpenCores I2C Master core                 ////
   5 ////                                                             ////
   6 ////  File    : oc_i2c_master.h                                  ////
   7 ////  Function: c-include file                                   ////
   8 ////                                                             ////
   9 ////  Authors: Richard Herveille (richard@asics.ws)              ////
  10 ////           Filip Miletic                                     ////
  11 ////                                                             ////
  12 ////           www.opencores.org                                 ////
  13 ////                                                             ////
  14 /////////////////////////////////////////////////////////////////////
  15 ////                                                             ////
  16 //// Copyright (C) 2001 Richard Herveille                        ////
  17 ////                    Filip Miletic                            ////
  18 ////                                                             ////
  19 //// This source file may be used and distributed without        ////
  20 //// restriction provided that this copyright statement is not   ////
  21 //// removed from the file and that any derivative work contains ////
  22 //// the original copyright notice and the associated disclaimer.////
  23 ////                                                             ////
  24 ////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
  25 //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
  26 //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
  27 //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
  28 //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
  29 //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
  30 //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
  31 //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
  32 //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
  33 //// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
  34 //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
  35 //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
  36 //// POSSIBILITY OF SUCH DAMAGE.                                 ////
  37 ////                                                             ////
  38 /////////////////////////////////////////////////////////////////////
  39 */
  40
  41 /*
  42  * Definitions for the Opencores i2c master core
  43  */
  44
  45 /* --- Definitions for i2c master's registers --- */
  46
  47 /* ----- Read-write access                                            */
  48
  49 #define OC_I2C_PRER_LO 0x00     /* Low byte clock prescaler register  */
  50 #define OC_I2C_PRER_HI 0x01     /* High byte clock prescaler register */
  51 #define OC_I2C_CTR     0x02     /* Control register                   */
  52
  53 /* ----- Write-only registers                                         */
  54
  55 #define OC_I2C_TXR     0x03     /* Transmit byte register             */
  56 #define OC_I2C_CR      0x04     /* Command register                   */
  57
  58 /* ----- Read-only registers                                          */
  59
  60 #define OC_I2C_RXR     0x03     /* Receive byte register              */
  61 #define OC_I2C_SR      0x04     /* Status register                    */
  62
  63 /* ----- Bits definition                                              */
  64
  65 /* ----- Control register                                             */
  66
  67 #define OC_I2C_EN (1<<7)        /* Core enable bit:                   */
  68                                 /*      1 - core is enabled           */
  69                                 /*      0 - core is disabled          */
  70 #define OC_I2C_IEN (1<<6)       /* Interrupt enable bit               */
  71                                 /*      1 - Interrupt enabled         */
  72                                 /*      0 - Interrupt disabled        */
  73                                 /* Other bits in CR are reserved      */
  74
  75 /* ----- Command register bits                                        */
  76
  77 #define OC_I2C_STA (1<<7)       /* Generate (repeated) start condition*/
  78 #define OC_I2C_STO (1<<6)       /* Generate stop condition            */
  79 #define OC_I2C_RD  (1<<5)       /* Read from slave                    */
  80 #define OC_I2C_WR  (1<<4)       /* Write to slave                     */
  81 #define OC_I2C_ACK (1<<3)       /* Acknowledge from slave             */
  82                                 /*      1 - ACK                       */
  83                                 /*      0 - NACK                      */
  84 #define OC_I2C_IACK (1<<0)      /* Interrupt acknowledge              */
  85
  86 /* ----- Status register bits                                         */
  87
  88 #define OC_I2C_RXACK (1<<7)     /* ACK received from slave            */
  89                                 /*      1 - ACK                       */
  90                                 /*      0 - NACK                      */
  91 #define OC_I2C_BUSY  (1<<6)     /* Busy bit                           */
  92 #define OC_I2C_TIP   (1<<1)     /* Transfer in progress               */
  93 #define OC_I2C_IF    (1<<0)     /* Interrupt flag                     */
  94
  95 /* bit testing and setting macros                                     */
  96
  97 #define OC_ISSET(reg,bitmask)       ((reg)&(bitmask))
  98 #define OC_ISCLEAR(reg,bitmask)     (!(OC_ISSET(reg,bitmask)))
  99 #define OC_BITSET(reg,bitmask)      ((reg)|(bitmask))
 100 #define OC_BITCLEAR(reg,bitmask)    ((reg)|(~(bitmask)))
 101 #define OC_BITTOGGLE(reg,bitmask)   ((reg)^(bitmask))
 102 #define OC_REGMOVE(reg,value)       ((reg)=(value))