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   1 ///////////////////////////////////////////////////////////////////////
   2 ////                                                               ////
   3 ////  WISHBONE rev.B2 Wishbone Master model                        ////
   4 ////                                                               ////
   5 ////                                                               ////
   6 ////  Author: Richard Herveille                                    ////
   7 ////          richard@asics.ws                                     ////
   8 ////          www.asics.ws                                         ////
   9 ////                                                               ////
  10 ////  Downloaded from: http://www.opencores.org/projects/mem_ctrl  ////
  11 ////                                                               ////
  12 ///////////////////////////////////////////////////////////////////////
  13 ////                                                               ////
  14 //// Copyright (C) 2001 Richard Herveille                          ////
  15 ////                    richard@asics.ws                           ////
  16 ////                                                               ////
  17 //// This source file may be used and distributed without          ////
  18 //// restriction provided that this copyright statement is not     ////
  19 //// removed from the file and that any derivative work contains   ////
  20 //// the original copyright notice and the associated disclaimer.  ////
  21 ////                                                               ////
  22 ////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY       ////
  23 //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED     ////
  24 //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS     ////
  25 //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR        ////
  26 //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,           ////
  27 //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES      ////
  28 //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE     ////
  29 //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR          ////
  30 //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    ////
  31 //// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT    ////
  32 //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT    ////
  33 //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE           ////
  34 //// POSSIBILITY OF SUCH DAMAGE.                                   ////
  35 ////                                                               ////
  36 ///////////////////////////////////////////////////////////////////////
  37
  38 //  CVS Log
  39 //
  40 //  $Id: wb_master_model.v,v 1.4 2004/02/28 15:40:42 rherveille Exp $
  41 //
  42 //  $Date: 2004/02/28 15:40:42 $
  43 //  $Revision: 1.4 $
  44 //  $Author: rherveille $
  45 //  $Locker:  $
  46 //  $State: Exp $
  47 //
  48 // Change History:
  49 //
  50 `include "timescale.v"
  51
  52 module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
  53
  54 parameter dwidth = 32;
  55 parameter awidth = 32;
  56
  57 input                  clk, rst;
  58 output [awidth   -1:0]  adr;
  59 input  [dwidth   -1:0]  din;
  60 output [dwidth   -1:0]  dout;
  61 output                 cyc, stb;
  62 output                          we;
  63 output [dwidth/8 -1:0] sel;
  64 input                           ack, err, rty;
  65
  66 ////////////////////////////////////////////////////////////////////
  67 //
  68 // Local Wires
  69 //
  70
  71 reg     [awidth   -1:0] adr;
  72 reg     [dwidth   -1:0] dout;
  73 reg                            cyc, stb;
  74 reg                            we;
  75 reg [dwidth/8 -1:0] sel;
  76
  77 reg [dwidth   -1:0] q;
  78
  79 ////////////////////////////////////////////////////////////////////
  80 //
  81 // Memory Logic
  82 //
  83
  84 initial
  85         begin
  86                 //adr = 32'hxxxx_xxxx;
  87                 //adr = 0;
  88                 adr  = {awidth{1'bx}};
  89                 dout = {dwidth{1'bx}};
  90                 cyc  = 1'b0;
  91                 stb  = 1'bx;
  92                 we   = 1'hx;
  93                 sel  = {dwidth/8{1'bx}};
  94                 #1;
  95                 $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
  96         end
  97
  98 ////////////////////////////////////////////////////////////////////
  99 //
 100 // Wishbone write cycle
 101 //
 102
 103 task wb_write;
 104         input   delay;
 105         integer delay;
 106
 107         input   [awidth -1:0]   a;
 108         input   [dwidth -1:0]   d;
 109
 110         begin
 111
 112                 // wait initial delay
 113                 repeat(delay) @(posedge clk);
 114
 115                 // assert wishbone signal
 116                 #1;
 117                 adr  = a;
 118                 dout = d;
 119                 cyc  = 1'b1;
 120                 stb  = 1'b1;
 121                 we   = 1'b1;
 122                 sel  = {dwidth/8{1'b1}};
 123                 @(posedge clk);
 124
 125                 // wait for acknowledge from slave
 126                 while(~ack)     @(posedge clk);
 127
 128                 // negate wishbone signals
 129                 #1;
 130                 cyc  = 1'b0;
 131                 stb  = 1'bx;
 132                 adr  = {awidth{1'bx}};
 133                 dout = {dwidth{1'bx}};
 134                 we   = 1'hx;
 135                 sel  = {dwidth/8{1'bx}};
 136
 137         end
 138 endtask
 139
 140 ////////////////////////////////////////////////////////////////////
 141 //
 142 // Wishbone read cycle
 143 //
 144
 145 task wb_read;
 146         input   delay;
 147         integer delay;
 148
 149         input    [awidth -1:0]  a;
 150         output  [dwidth -1:0]   d;
 151
 152         begin
 153
 154                 // wait initial delay
 155                 repeat(delay) @(posedge clk);
 156
 157                 // assert wishbone signals
 158                 #1;
 159                 adr  = a;
 160                 dout = {dwidth{1'bx}};
 161                 cyc  = 1'b1;
 162                 stb  = 1'b1;
 163                 we   = 1'b0;
 164                 sel  = {dwidth/8{1'b1}};
 165                 @(posedge clk);
 166
 167                 // wait for acknowledge from slave
 168                 while(~ack)     @(posedge clk);
 169
 170                 // negate wishbone signals
 171                 #1;
 172                 cyc  = 1'b0;
 173                 stb  = 1'bx;
 174                 adr  = {awidth{1'bx}};
 175                 dout = {dwidth{1'bx}};
 176                 we   = 1'hx;
 177                 sel  = {dwidth/8{1'bx}};
 178                 d    = din;
 179
 180         end
 181 endtask
 182
 183 ////////////////////////////////////////////////////////////////////
 184 //
 185 // Wishbone compare cycle (read data from location and compare with expected data)
 186 //
 187
 188 task wb_cmp;
 189         input   delay;
 190         integer delay;
 191
 192         input [awidth -1:0]     a;
 193         input   [dwidth -1:0]   d_exp;
 194
 195         begin
 196                 wb_read (delay, a, q);
 197
 198                 if (d_exp !== q)
 199                         $display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time);
 200         end
 201 endtask
 202
 203 endmodule
 204
 205