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   1 module duram(
   2 data_a,
   3 data_b,
   4 wren_a,
   5 wren_b,
   6 address_a,
   7 address_b,
   8 clock_a,
   9 clock_b,
  10 q_a,
  11 q_b);
  12
  13 parameter DATA_WIDTH    = 36;
  14 parameter ADDR_WIDTH    = 9;
  15 parameter BLK_RAM_TYPE  = "AUTO";
  16 parameter ADDR_DEPTH    = 2**ADDR_WIDTH;
  17
  18
  19
  20 input   [DATA_WIDTH -1:0]   data_a;
  21 input                       wren_a;
  22 input   [ADDR_WIDTH -1:0]   address_a;
  23 input                       clock_a;
  24 output  [DATA_WIDTH -1:0]   q_a;
  25 input   [DATA_WIDTH -1:0]   data_b;
  26 input                       wren_b;
  27 input   [ADDR_WIDTH -1:0]   address_b;
  28 input                       clock_b;
  29 output  [DATA_WIDTH -1:0]   q_b;
  30
  31 wire    [35:0]  do_b;
  32 wire    [35:0]  din_a;
  33
  34 assign  din_a   =data_a;
  35 assign  q_b     =do_b;
  36
  37
  38 RAMB16_S36_S36 U_RAMB16_S36_S36 (
  39 .DOA         (                          ),
  40 .DOB         (do_b[31:0]                ),
  41 .DOPA        (                          ),
  42 .DOPB        (do_b[35:32]               ),
  43 .ADDRA       (address_a                 ),
  44 .ADDRB       (address_b                 ),
  45 .CLKA        (clock_a                   ),
  46 .CLKB        (clock_b                   ),
  47 .DIA         (din_a[31:0]               ),
  48 .DIB         (                          ),
  49 .DIPA        (din_a[35:32]              ),
  50 .DIPB        (                          ),
  51 .ENA         (1'b1                      ),
  52 .ENB         (1'b1                      ),
  53 .SSRA        (1'b0                      ),
  54 .SSRB        (1'b0                      ),
  55 .WEA         (wren_a                    ),
  56 .WEB         (1'b0                      ));
  57
  58 endmodule
  59
  60