remove debugging code
[debian/gnuradio] / usrp2 / fpga / opencores / ethernet_tri_mode / rtl / verilog / RMON.v
1 //////////////////////////////////////////////////////////////////////
2 ////                                                              ////
3 ////  RMON.v                                                      ////
4 ////                                                              ////
5 ////  This file is part of the Ethernet IP core project           ////
6 ////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
7 ////                                                              ////
8 ////  Author(s):                                                  ////
9 ////      - Jon Gao (gaojon@yahoo.com)                            ////
10 ////                                                              ////
11 ////                                                              ////
12 //////////////////////////////////////////////////////////////////////
13 ////                                                              ////
14 //// Copyright (C) 2001 Authors                                   ////
15 ////                                                              ////
16 //// This source file may be used and distributed without         ////
17 //// restriction provided that this copyright statement is not    ////
18 //// removed from the file and that any derivative work contains  ////
19 //// the original copyright notice and the associated disclaimer. ////
20 ////                                                              ////
21 //// This source file is free software; you can redistribute it   ////
22 //// and/or modify it under the terms of the GNU Lesser General   ////
23 //// Public License as published by the Free Software Foundation; ////
24 //// either version 2.1 of the License, or (at your option) any   ////
25 //// later version.                                               ////
26 ////                                                              ////
27 //// This source is distributed in the hope that it will be       ////
28 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
29 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
30 //// PURPOSE.  See the GNU Lesser General Public License for more ////
31 //// details.                                                     ////
32 ////                                                              ////
33 //// You should have received a copy of the GNU Lesser General    ////
34 //// Public License along with this source; if not, download it   ////
35 //// from http://www.opencores.org/lgpl.shtml                     ////
36 ////                                                              ////
37 //////////////////////////////////////////////////////////////////////
38 //                                                                    
39 // CVS Revision History                                               
40 //                                                                    
41 // $Log: RMON.v,v $
42 // Revision 1.4  2006/06/25 04:58:56  maverickist
43 // no message
44 //
45 // Revision 1.3  2006/01/19 14:07:53  maverickist
46 // verification is complete.
47 //
48 // Revision 1.2  2005/12/16 06:44:16  Administrator
49 // replaced tab with space.
50 // passed 9.6k length frame test.
51 //
52 // Revision 1.1.1.1  2005/12/13 01:51:44  Administrator
53 // no message
54 // 
55
56 module RMON 
57   (Clk                 ,
58    Reset               ,
59    //Tx_RMON            
60    Tx_pkt_type_rmon    ,
61    Tx_pkt_length_rmon  ,
62    Tx_apply_rmon       ,
63    Tx_pkt_err_type_rmon,
64    //Tx_RMON            
65    Rx_pkt_type_rmon    ,
66    Rx_pkt_length_rmon  ,
67    Rx_apply_rmon       ,
68    Rx_pkt_err_type_rmon,
69    //CPU                
70    CPU_rd_addr         ,
71    CPU_rd_apply        ,
72    CPU_rd_grant        ,
73    CPU_rd_dout         
74    );
75    
76    input               Clk                 ;
77    input               Reset               ;
78    //Tx_RMON
79    input [2:0]         Tx_pkt_type_rmon    ;
80    input [15:0]        Tx_pkt_length_rmon  ;
81    input               Tx_apply_rmon       ;
82    input [2:0]         Tx_pkt_err_type_rmon;
83    //Tx_RMON
84    input [2:0]         Rx_pkt_type_rmon    ;
85    input [15:0]        Rx_pkt_length_rmon  ;
86    input               Rx_apply_rmon       ;
87    input [2:0]         Rx_pkt_err_type_rmon;
88    //CPU
89    input [5:0]         CPU_rd_addr         ;
90    input               CPU_rd_apply        ;
91    output              CPU_rd_grant        ;
92    output [31:0]       CPU_rd_dout         ;
93    
94    // ******************************************************************************  
95    //interface signals
96    // ******************************************************************************  
97    wire                Reg_apply_0     ;
98    wire [4:0]          Reg_addr_0      ;
99    wire [15:0]         Reg_data_0      ;
100    wire                Reg_next_0      ;
101    wire                Reg_apply_1     ;
102    wire [4:0]          Reg_addr_1      ;
103    wire [15:0]         Reg_data_1      ;
104    wire                Reg_next_1      ;
105    wire [5:0]          Addra           ;
106    wire [31:0]         Dina            ;
107    wire [31:0]         Douta           ;
108    wire                Wea             ;
109    
110    // ******************************************************************************  
111    
112    RMON_addr_gen 
113      U_0_Rx_RMON_addr_gen(.Clk                    (Clk                        ),
114                           .Reset                  (Reset                      ),
115                           //RMON                 (//RMON                     ),
116                           // .Pkt_type_rmon          (Rx_pkt_type_rmon           ),
117                           .Pkt_length_rmon        (Rx_pkt_length_rmon         ),     
118                           .Apply_rmon             (Rx_apply_rmon              ),
119                           .Pkt_err_type_rmon      (Rx_pkt_err_type_rmon       ),
120                           //Rmon_ctrl            (//Rmon_ctrl                ),
121                           .Reg_apply              (Reg_apply_0                ),
122                           .Reg_addr               (Reg_addr_0                 ),
123                           .Reg_data               (Reg_data_0                 ),
124                           .Reg_next               (Reg_next_0                 ),
125                           //CPU                  (//CPU                       ),
126                           .Reg_drop_apply         (                           ));
127    
128    RMON_addr_gen 
129      U_0_Tx_RMON_addr_gen(.Clk                    (Clk                        ),
130                           .Reset                  (Reset                      ),
131                           //RMON                 (//RMON                     ),
132                           .Pkt_type_rmon          (Tx_pkt_type_rmon           ),              
133                           .Pkt_length_rmon        (Tx_pkt_length_rmon         ),                       
134                           .Apply_rmon             (Tx_apply_rmon              ),
135                           .Pkt_err_type_rmon      (Tx_pkt_err_type_rmon       ),
136                           //Rmon_ctrl            (//Rmon_ctrl                ),                         
137                           .Reg_apply              (Reg_apply_1                ),                  
138                           .Reg_addr               (Reg_addr_1                 ),                   
139                           .Reg_data               (Reg_data_1                 ),                  
140                           .Reg_next               (Reg_next_1                 ),                 
141                           //CPU                  (//CPU                       ),                     
142                           .Reg_drop_apply         (                           ));
143    
144    RMON_ctrl 
145      U_RMON_ctrl(.Clk                    (Clk                        ),        
146                  .Reset                  (Reset                      ), 
147                  //RMON_CTRL            (//RMON_CTRL                ),  
148                  .Reg_apply_0            (Reg_apply_0                ),         
149                  .Reg_addr_0             (Reg_addr_0                 ), 
150                  .Reg_data_0             (Reg_data_0                 ), 
151                  .Reg_next_0             (Reg_next_0                 ), 
152                  .Reg_apply_1            (Reg_apply_1                ),         
153                  .Reg_addr_1             (Reg_addr_1                 ), 
154                  .Reg_data_1             (Reg_data_1                 ), 
155                  .Reg_next_1             (Reg_next_1                 ), 
156                  //dual-port ram        (//dual-port ram            ),  
157                  .Addra                  (Addra                      ), 
158                  .Dina                   (Dina                       ), 
159                  .Douta                  (Douta                      ), 
160                  .Wea                    (Wea                        ),       
161                  //CPU                  (//CPU                      ),    
162                  .CPU_rd_addr            (CPU_rd_addr                ),     
163                  .CPU_rd_apply           (CPU_rd_apply               ), 
164                  .CPU_rd_grant           (CPU_rd_grant               ), 
165                  .CPU_rd_dout            (CPU_rd_dout                ) 
166                  );
167
168    RMON_dpram 
169      U_Rx_RMON_dpram(.Reset                  (Reset                      ),       
170                      .Clk                    (Clk                        ), 
171                      //port-a for Rmon       (//port-a for Rmon          ),
172                      .Addra                  (Addra                      ),
173                      .Dina                   (Dina                       ),
174                      .Douta                  (                           ),
175                      .Wea                    (Wea                        ),
176                      //port-b for CPU        (//port-b for CPU           ),
177                      .Addrb                  (Addra                      ),
178                      .Doutb                  (Douta                      ));
179    
180 endmodule // RMON