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   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  RMON_addr_gen.v                                             ////
   4 ////                                                              ////
   5 ////  This file is part of the Ethernet IP core project           ////
   6 ////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Jon Gao (gaojon@yahoo.com)                            ////
  10 ////                                                              ////
  11 ////                                                              ////
  12 //////////////////////////////////////////////////////////////////////
  13 ////                                                              ////
  14 //// Copyright (C) 2001 Authors                                   ////
  15 ////                                                              ////
  16 //// This source file may be used and distributed without         ////
  17 //// restriction provided that this copyright statement is not    ////
  18 //// removed from the file and that any derivative work contains  ////
  19 //// the original copyright notice and the associated disclaimer. ////
  20 ////                                                              ////
  21 //// This source file is free software; you can redistribute it   ////
  22 //// and/or modify it under the terms of the GNU Lesser General   ////
  23 //// Public License as published by the Free Software Foundation; ////
  24 //// either version 2.1 of the License, or (at your option) any   ////
  25 //// later version.                                               ////
  26 ////                                                              ////
  27 //// This source is distributed in the hope that it will be       ////
  28 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  29 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  30 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  31 //// details.                                                     ////
  32 ////                                                              ////
  33 //// You should have received a copy of the GNU Lesser General    ////
  34 //// Public License along with this source; if not, download it   ////
  35 //// from http://www.opencores.org/lgpl.shtml                     ////
  36 ////                                                              ////
  37 //////////////////////////////////////////////////////////////////////
  38 //
  39 // CVS Revision History
  40 //
  41 // $Log: RMON_addr_gen.v,v $
  42 // Revision 1.4  2006/06/25 04:58:57  maverickist
  43 // no message
  44 //
  45 // Revision 1.3  2006/01/19 14:07:55  maverickist
  46 // verification is complete.
  47 //
  48 // Revision 1.2  2005/12/16 06:44:19  Administrator
  49 // replaced tab with space.
  50 // passed 9.6k length frame test.
  51 //
  52 // Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
  53 // no message
  54 //
  55 module RMON_addr_gen(
  56 Clk                 ,
  57 Reset               ,
  58 //RMON
  59 Pkt_type_rmon       ,
  60 Pkt_length_rmon     ,
  61 Apply_rmon          ,//pluse signal looks like eop
  62 Pkt_err_type_rmon   ,
  63 //
  64 Reg_apply           ,
  65 Reg_addr            ,
  66 Reg_data            ,
  67 Reg_next            ,
  68 //CPU
  69 Reg_drop_apply
  70 );
  71 input           Clk                 ;
  72 input           Reset               ;
  73                 //RMON
  74 input   [2:0]   Pkt_type_rmon       ;
  75 input   [15:0]  Pkt_length_rmon     ;
  76 input           Apply_rmon          ;//pluse signal looks like eop
  77 input   [2:0]   Pkt_err_type_rmon   ;
  78                 //RMON_ctrl
  79 output          Reg_apply           ;
  80 output  [4:0]   Reg_addr            ;
  81 output  [15:0]  Reg_data            ;
  82 input           Reg_next            ;
  83                 //CPU
  84 output          Reg_drop_apply      ;
  85
  86 //******************************************************************************
  87 //internal signals
  88 //******************************************************************************
  89 parameter       StateIdle       =4'd0;
  90 parameter       StatePktLength  =4'd1;
  91 parameter       StatePktNumber  =4'd2;
  92 parameter       StatePktType    =4'd3;
  93 parameter       StatePktRange   =4'd4;
  94
  95 reg [3:0]       CurrentState /* synthesys syn_keep=1 */;
  96 reg [3:0]       NextState;
  97
  98 reg [2:0]       PktTypeReg      ;
  99 reg [15:0]      PktLengthReg    ;
 100 reg [2:0]       PktErrTypeReg   ;
 101
 102 reg             Reg_apply       ;
 103 reg [4:0]       Reg_addr            ;
 104 reg [15:0]      Reg_data            ;
 105 reg             Reg_drop_apply  ;
 106 //******************************************************************************
 107 //register boundery signals
 108
 109 //******************************************************************************
 110 reg             Apply_rmon_dl1;
 111 reg             Apply_rmon_dl2;
 112 reg             Apply_rmon_pulse;
 113 reg [2:0]       Pkt_type_rmon_dl1       ;
 114 reg [15:0]      Pkt_length_rmon_dl1     ;
 115 reg [2:0]       Pkt_err_type_rmon_dl1   ;
 116
 117 always @(posedge Clk or posedge Reset)
 118     if (Reset)
 119         begin
 120         Pkt_type_rmon_dl1       <=0;
 121         Pkt_length_rmon_dl1     <=0;
 122         Pkt_err_type_rmon_dl1   <=0;
 123         end
 124     else
 125         begin
 126         Pkt_type_rmon_dl1       <=Pkt_type_rmon     ;
 127         Pkt_length_rmon_dl1     <=Pkt_length_rmon   ;
 128         Pkt_err_type_rmon_dl1   <=Pkt_err_type_rmon ;
 129         end
 130
 131 always @(posedge Clk or posedge Reset)
 132     if (Reset)
 133         begin
 134         Apply_rmon_dl1  <=0;
 135         Apply_rmon_dl2  <=0;
 136         end
 137     else
 138         begin
 139         Apply_rmon_dl1  <=Apply_rmon;
 140         Apply_rmon_dl2  <=Apply_rmon_dl1;
 141         end
 142
 143 always @(Apply_rmon_dl1 or Apply_rmon_dl2)
 144     if (Apply_rmon_dl1&!Apply_rmon_dl2)
 145         Apply_rmon_pulse    =1;
 146     else
 147         Apply_rmon_pulse    =0;
 148
 149
 150
 151 always @(posedge Clk or posedge Reset)
 152     if (Reset)
 153         begin
 154         PktTypeReg          <=0;
 155         PktLengthReg        <=0;
 156         PktErrTypeReg       <=0;
 157         end
 158     else if (Apply_rmon_pulse&&CurrentState==StateIdle)
 159         begin
 160         PktTypeReg          <=Pkt_type_rmon_dl1     ;
 161         PktLengthReg        <=Pkt_length_rmon_dl1   ;
 162         PktErrTypeReg       <=Pkt_err_type_rmon_dl1 ;
 163         end
 164
 165
 166 //******************************************************************************
 167 //State Machine
 168 //******************************************************************************
 169 always @(posedge Clk or posedge Reset)
 170     if (Reset)
 171         CurrentState    <=StateIdle;
 172     else
 173         CurrentState    <=NextState;
 174
 175 always @(CurrentState or Apply_rmon_pulse or Reg_next)
 176     case (CurrentState)
 177         StateIdle:
 178             if (Apply_rmon_pulse)
 179                 NextState   =StatePktLength;
 180             else
 181                 NextState   =StateIdle;
 182         StatePktLength:
 183             if (Reg_next)
 184                 NextState   =StatePktNumber;
 185             else
 186                 NextState   =CurrentState;
 187         StatePktNumber:
 188             if (Reg_next)
 189                 NextState   =StatePktType;
 190             else
 191                 NextState   =CurrentState;
 192         StatePktType:
 193             if (Reg_next)
 194                 NextState   =StatePktRange;
 195             else
 196                 NextState   =CurrentState;
 197         StatePktRange:
 198             if (Reg_next)
 199                 NextState   =StateIdle;
 200             else
 201                 NextState   =CurrentState;
 202         default:
 203                 NextState   =StateIdle;
 204     endcase
 205
 206 //******************************************************************************
 207 //gen output signals
 208 //******************************************************************************
 209 //Reg_apply
 210 always @ (CurrentState)
 211     if (CurrentState==StatePktLength||CurrentState==StatePktNumber||
 212         CurrentState==StatePktType||CurrentState==StatePktRange)
 213         Reg_apply   =1;
 214     else
 215         Reg_apply   =0;
 216
 217 //Reg_addr
 218 always @ (posedge Clk or posedge Reset)
 219     if (Reset)
 220         Reg_addr    <=0;
 221     else case (CurrentState)
 222             StatePktLength:
 223                 Reg_addr    <=5'd00;
 224             StatePktNumber:
 225                 Reg_addr    <=5'd01;
 226             StatePktType:
 227                 case(PktTypeReg)
 228                     3'b011:
 229                         Reg_addr    <=5'd02;    //broadcast
 230                     3'b001:
 231                         Reg_addr    <=5'd03;    //multicast
 232                     3'b100:
 233                         Reg_addr    <=5'd16;    //pause frame
 234                     default:
 235                         Reg_addr    <=5'd04;    //unicast
 236                 endcase
 237             StatePktRange:
 238                 case(PktErrTypeReg)
 239                     3'b001:
 240                         Reg_addr    <=5'd05;
 241                     3'b010:
 242                         Reg_addr    <=5'd06;
 243                     3'b011:
 244                         Reg_addr    <=5'd07;
 245                     3'b100:
 246                         if (PktLengthReg<64)
 247                             Reg_addr    <=5'd08;
 248                         else if (PktLengthReg==64)
 249                             Reg_addr    <=5'd09;
 250                         else if (PktLengthReg<128)
 251                             Reg_addr    <=5'd10;
 252                         else if (PktLengthReg<256)
 253                             Reg_addr    <=5'd11;
 254                         else if (PktLengthReg<512)
 255                             Reg_addr    <=5'd12;
 256                         else if (PktLengthReg<1024)
 257                             Reg_addr    <=5'd13;
 258                         else if (PktLengthReg<1519)
 259                             Reg_addr    <=5'd14;
 260                         else
 261                             Reg_addr    <=5'd15;
 262                     default:
 263                         Reg_addr    <=5'd05;
 264                 endcase
 265             default:
 266                     Reg_addr    <=5'd05;
 267         endcase
 268
 269 //Reg_data
 270 always @ (CurrentState or PktLengthReg)
 271     case (CurrentState)
 272         StatePktLength:
 273             Reg_data    =PktLengthReg;
 274         StatePktNumber:
 275             Reg_data    =1;
 276         StatePktType:
 277             Reg_data =1;
 278         StatePktRange:
 279             Reg_data =1;
 280         default:
 281             Reg_data =0;
 282     endcase
 283
 284 //Reg_drop_apply
 285 always @ (posedge Clk or posedge Reset)
 286     if (Reset)
 287         Reg_drop_apply  <=0;
 288     else if (CurrentState!=StateIdle&&Apply_rmon_pulse)
 289         Reg_drop_apply  <=1;
 290     else
 291         Reg_drop_apply  <=0;
 292
 293
 294 endmodule
 295