git.gag.com Git - debian/gnuradio/blob - usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/Phy_int.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  Phy_int.v                                                   ////
   4 ////                                                              ////
   5 ////  This file is part of the Ethernet IP core project           ////
   6 ////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Jon Gao (gaojon@yahoo.com)                            ////
  10 ////                                                              ////
  11 ////                                                              ////
  12 //////////////////////////////////////////////////////////////////////
  13 ////                                                              ////
  14 //// Copyright (C) 2001 Authors                                   ////
  15 ////                                                              ////
  16 //// This source file may be used and distributed without         ////
  17 //// restriction provided that this copyright statement is not    ////
  18 //// removed from the file and that any derivative work contains  ////
  19 //// the original copyright notice and the associated disclaimer. ////
  20 ////                                                              ////
  21 //// This source file is free software; you can redistribute it   ////
  22 //// and/or modify it under the terms of the GNU Lesser General   ////
  23 //// Public License as published by the Free Software Foundation; ////
  24 //// either version 2.1 of the License, or (at your option) any   ////
  25 //// later version.                                               ////
  26 ////                                                              ////
  27 //// This source is distributed in the hope that it will be       ////
  28 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  29 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  30 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  31 //// details.                                                     ////
  32 ////                                                              ////
  33 //// You should have received a copy of the GNU Lesser General    ////
  34 //// Public License along with this source; if not, download it   ////
  35 //// from http://www.opencores.org/lgpl.shtml                     ////
  36 ////                                                              ////
  37 //////////////////////////////////////////////////////////////////////
  38 //
  39 // CVS Revision History
  40 //
  41 // $Log: Phy_int.v,v $
  42 // Revision 1.3  2006/01/19 14:07:53  maverickist
  43 // verification is complete.
  44 //
  45 // Revision 1.3  2005/12/16 06:44:14  Administrator
  46 // replaced tab with space.
  47 // passed 9.6k length frame test.
  48 //
  49 // Revision 1.2  2005/12/13 12:15:36  Administrator
  50 // no message
  51 //
  52 // Revision 1.1.1.1  2005/12/13 01:51:44  Administrator
  53 // no message
  54 //
  55
  56 module Phy_int (
  57 Reset               ,
  58 MAC_rx_clk          ,
  59 MAC_tx_clk          ,
  60 //Rx interface      ,
  61 MCrs_dv             ,
  62 MRxD                ,
  63 MRxErr              ,
  64 //Tx interface      ,
  65 MTxD                ,
  66 MTxEn               ,
  67 MCRS                ,
  68 //Phy interface     ,
  69 Tx_er               ,
  70 Tx_en               ,
  71 Txd                 ,
  72 Rx_er               ,
  73 Rx_dv               ,
  74 Rxd                 ,
  75 Crs                 ,
  76 Col                 ,
  77 //host interface    ,
  78 Line_loop_en        ,
  79 Speed
  80
  81 );
  82 input           Reset               ;
  83 input           MAC_rx_clk          ;
  84 input           MAC_tx_clk          ;
  85                 //Rx interface
  86 output          MCrs_dv             ;
  87 output  [7:0]   MRxD                ;
  88 output          MRxErr              ;
  89                 //Tx interface
  90 input   [7:0]   MTxD                ;
  91 input           MTxEn               ;
  92 output          MCRS                ;
  93                 //Phy interface
  94 output          Tx_er               ;
  95 output          Tx_en               ;
  96 output  [7:0]   Txd                 ;
  97 input           Rx_er               ;
  98 input           Rx_dv               ;
  99 input   [7:0]   Rxd                 ;
 100 input           Crs                 ;
 101 input           Col                 ;
 102                 //host interface
 103 input           Line_loop_en        ;
 104 input   [2:0]   Speed               ;
 105 //******************************************************************************
 106 //internal signals
 107 //******************************************************************************
 108 reg     [7:0]   MTxD_dl1            ;
 109 reg             MTxEn_dl1           ;
 110 reg             Tx_odd_data_ptr     ;
 111 reg             Rx_odd_data_ptr     ;
 112 reg             Tx_en               ;
 113 reg     [7:0]   Txd                 ;
 114 reg             MCrs_dv             ;
 115 reg     [7:0]   MRxD                ;
 116 reg             Rx_er_dl1           ;
 117 reg             Rx_dv_dl1           ;
 118 reg             Rx_dv_dl2           ;
 119 reg     [7:0]   Rxd_dl1             ;
 120 reg     [7:0]   Rxd_dl2             ;
 121 reg             Crs_dl1             ;
 122 reg             Col_dl1             ;
 123 //******************************************************************************
 124 //Tx control
 125 //******************************************************************************
 126 //reg boundery signals
 127 always @ (posedge MAC_tx_clk or posedge Reset)
 128     if (Reset)
 129         begin
 130         MTxD_dl1            <=0;
 131         MTxEn_dl1           <=0;
 132         end
 133     else
 134         begin
 135         MTxD_dl1            <=MTxD  ;
 136         MTxEn_dl1           <=MTxEn ;
 137         end
 138
 139 always @ (posedge MAC_tx_clk or posedge Reset)
 140     if (Reset)
 141         Tx_odd_data_ptr     <=0;
 142     else if (!MTxD_dl1)
 143         Tx_odd_data_ptr     <=0;
 144     else
 145         Tx_odd_data_ptr     <=!Tx_odd_data_ptr;
 146
 147
 148 always @ (posedge MAC_tx_clk or posedge Reset)
 149     if (Reset)
 150         Txd                 <=0;
 151     else if(Speed[2]&&MTxEn_dl1)
 152         Txd                 <=MTxD_dl1;
 153     else if(MTxEn_dl1&&!Tx_odd_data_ptr)
 154         Txd                 <={4'b0,MTxD_dl1[3:0]};
 155     else if(MTxEn_dl1&&Tx_odd_data_ptr)
 156         Txd                 <={4'b0,MTxD_dl1[7:4]};
 157     else
 158         Txd                 <=0;
 159
 160 always @ (posedge MAC_tx_clk or posedge Reset)
 161     if (Reset)
 162         Tx_en               <=0;
 163     else if(MTxEn_dl1)
 164         Tx_en               <=1;
 165     else
 166         Tx_en               <=0;
 167
 168 assign Tx_er=0;
 169
 170 //******************************************************************************
 171 //Rx control
 172 //******************************************************************************
 173 //reg boundery signals
 174 always @ (posedge MAC_rx_clk or posedge Reset)
 175     if (Reset)
 176         begin
 177         Rx_er_dl1           <=0;
 178         Rx_dv_dl1           <=0;
 179         Rx_dv_dl2           <=0 ;
 180         Rxd_dl1             <=0;
 181         Rxd_dl2             <=0;
 182         Crs_dl1             <=0;
 183         Col_dl1             <=0;
 184         end
 185     else
 186         begin
 187         Rx_er_dl1           <=Rx_er     ;
 188         Rx_dv_dl1           <=Rx_dv     ;
 189         Rx_dv_dl2           <=Rx_dv_dl1 ;
 190         Rxd_dl1             <=Rxd       ;
 191         Rxd_dl2             <=Rxd_dl1   ;
 192         Crs_dl1             <=Crs       ;
 193         Col_dl1             <=Col       ;
 194         end
 195
 196 assign MRxErr   =Rx_er_dl1      ;
 197 assign MCRS     =Crs_dl1        ;
 198
 199 always @ (posedge MAC_rx_clk or posedge Reset)
 200     if (Reset)
 201         MCrs_dv         <=0;
 202     else if(Line_loop_en)
 203         MCrs_dv         <=Tx_en;
 204     else if(Rx_dv_dl2)
 205         MCrs_dv         <=1;
 206     else
 207         MCrs_dv         <=0;
 208
 209 always @ (posedge MAC_rx_clk or posedge Reset)
 210     if (Reset)
 211         Rx_odd_data_ptr     <=0;
 212     else if (!Rx_dv_dl1)
 213         Rx_odd_data_ptr     <=0;
 214     else
 215         Rx_odd_data_ptr     <=!Rx_odd_data_ptr;
 216
 217 always @ (posedge MAC_rx_clk or posedge Reset)
 218     if (Reset)
 219         MRxD            <=0;
 220     else if(Line_loop_en)
 221         MRxD            <=Txd;
 222     else if(Speed[2]&&Rx_dv_dl2)
 223         MRxD            <=Rxd_dl2;
 224     else if(Rx_dv_dl1&&Rx_odd_data_ptr)
 225         MRxD            <={Rxd_dl1[3:0],Rxd_dl2[3:0]};
 226
 227 endmodule