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   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  MAC_tx_ctrl.v                                               ////
   4 ////                                                              ////
   5 ////  This file is part of the Ethernet IP core project           ////
   6 ////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Jon Gao (gaojon@yahoo.com)                            ////
  10 ////                                                              ////
  11 ////                                                              ////
  12 //////////////////////////////////////////////////////////////////////
  13 ////                                                              ////
  14 //// Copyright (C) 2001 Authors                                   ////
  15 ////                                                              ////
  16 //// This source file may be used and distributed without         ////
  17 //// restriction provided that this copyright statement is not    ////
  18 //// removed from the file and that any derivative work contains  ////
  19 //// the original copyright notice and the associated disclaimer. ////
  20 ////                                                              ////
  21 //// This source file is free software; you can redistribute it   ////
  22 //// and/or modify it under the terms of the GNU Lesser General   ////
  23 //// Public License as published by the Free Software Foundation; ////
  24 //// either version 2.1 of the License, or (at your option) any   ////
  25 //// later version.                                               ////
  26 ////                                                              ////
  27 //// This source is distributed in the hope that it will be       ////
  28 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  29 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  30 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  31 //// details.                                                     ////
  32 ////                                                              ////
  33 //// You should have received a copy of the GNU Lesser General    ////
  34 //// Public License along with this source; if not, download it   ////
  35 //// from http://www.opencores.org/lgpl.shtml                     ////
  36 ////                                                              ////
  37 //////////////////////////////////////////////////////////////////////
  38 //
  39 // CVS Revision History
  40 //
  41 // $Log: MAC_tx_Ctrl.v,v $
  42 // Revision 1.4  2006/06/25 04:58:56  maverickist
  43 // no message
  44 //
  45 // Revision 1.3  2006/01/19 14:07:54  maverickist
  46 // verification is complete.
  47 //
  48 // Revision 1.3  2005/12/16 06:44:17  Administrator
  49 // replaced tab with space.
  50 // passed 9.6k length frame test.
  51 //
  52 // Revision 1.2  2005/12/13 12:15:38  Administrator
  53 // no message
  54 //
  55 // Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
  56 // no message
  57 //
  58
  59 module MAC_tx_ctrl (
  60 Reset               ,
  61 Clk                 ,
  62 //CRC_gen Interface
  63 CRC_init            ,
  64 Frame_data          ,
  65 Data_en             ,
  66 CRC_rd              ,
  67 CRC_end             ,
  68 CRC_out             ,
  69 //Ramdon_gen interfac
  70 Random_init         ,
  71 RetryCnt            ,
  72 Random_time_meet    ,
  73 //flow control
  74 pause_apply         ,
  75 pause_quanta_sub    ,
  76 xoff_gen            ,
  77 xoff_gen_complete   ,
  78 xon_gen             ,
  79 xon_gen_complete    ,
  80 //MAC_tx_FF
  81 Fifo_data           ,
  82 Fifo_rd             ,
  83 Fifo_eop            ,
  84 Fifo_da             ,
  85 Fifo_rd_finish      ,
  86 Fifo_rd_retry       ,
  87 Fifo_ra             ,
  88 Fifo_data_err_empty ,
  89 Fifo_data_err_full  ,
  90 //RMII
  91 TxD                 ,
  92 TxEn                ,
  93 CRS                 ,
  94 //MAC_tx_addr_add
  95 MAC_tx_addr_rd      ,
  96 MAC_tx_addr_data    ,
  97 MAC_tx_addr_init    ,
  98 //RMON
  99 Tx_pkt_type_rmon    ,
 100 Tx_pkt_length_rmon  ,
 101 Tx_apply_rmon       ,
 102 Tx_pkt_err_type_rmon,
 103 //CPU
 104 pause_frame_send_en ,
 105 pause_quanta_set    ,
 106 MAC_tx_add_en       ,
 107 FullDuplex          ,
 108 MaxRetry            ,
 109 IFGset
 110 );
 111
 112 input           Reset               ;
 113 input           Clk                 ;
 114                 //CRC_gen Interface
 115 output          CRC_init            ;
 116 output  [7:0]   Frame_data          ;
 117 output          Data_en             ;
 118 output          CRC_rd              ;
 119 input           CRC_end             ;
 120 input   [7:0]   CRC_out             ;
 121                 //Ramdon_gen interface
 122 output          Random_init         ;
 123 output  [3:0]   RetryCnt            ;
 124 input           Random_time_meet    ;//levle hight indicate random time passed away
 125                 //flow control
 126 input           pause_apply         ;
 127 output          pause_quanta_sub    ;
 128 input           xoff_gen            ;
 129 output          xoff_gen_complete   ;
 130 input           xon_gen             ;
 131 output          xon_gen_complete    ;
 132                 //MAC_rx_FF
 133 input   [7:0]   Fifo_data           ;
 134 output          Fifo_rd             ;
 135 input           Fifo_eop            ;
 136 input           Fifo_da             ;
 137 output          Fifo_rd_finish      ;
 138 output          Fifo_rd_retry       ;
 139 input           Fifo_ra             ;
 140 input           Fifo_data_err_empty ;
 141 input           Fifo_data_err_full  ;
 142                 //RMII
 143 output  [7:0]   TxD                 ;
 144 output          TxEn                ;
 145 input           CRS                 ;
 146                 //MAC_tx_addr_add
 147 output          MAC_tx_addr_init    ;
 148 output          MAC_tx_addr_rd      ;
 149 input   [7:0]   MAC_tx_addr_data    ;
 150                 //RMON
 151 output  [2:0]   Tx_pkt_type_rmon    ;
 152 output  [15:0]  Tx_pkt_length_rmon  ;
 153 output          Tx_apply_rmon       ;
 154 output  [2:0]   Tx_pkt_err_type_rmon;
 155                 //CPU
 156 input           pause_frame_send_en ;
 157 input   [15:0]  pause_quanta_set    ;
 158 input           MAC_tx_add_en       ;
 159 input           FullDuplex          ;
 160 input   [3:0]   MaxRetry            ;
 161 input   [5:0]   IFGset              ;
 162 //******************************************************************************
 163 //internal signals
 164 //******************************************************************************
 165 parameter       StateIdle           =4'd00;
 166 parameter       StatePreamble       =4'd01;
 167 parameter       StateSFD            =4'd02;
 168 parameter       StateData           =4'd03;
 169 parameter       StatePause          =4'd04;
 170 parameter       StatePAD            =4'd05;
 171 parameter       StateFCS            =4'd06;
 172 parameter       StateIFG            =4'd07;
 173 parameter       StateJam            =4'd08;
 174 parameter       StateBackOff        =4'd09;
 175 parameter       StateJamDrop        =4'd10;
 176 parameter       StateFFEmptyDrop    =4'd11;
 177 parameter       StateSwitchNext     =4'd12;
 178 parameter       StateDefer          =4'd13;
 179 parameter       StateSendPauseFrame =4'd14;
 180
 181 reg [3:0]       Current_state   /*synthesis syn_keep=1 */;
 182 reg [3:0]       Next_state;
 183 reg [5:0]       IFG_counter;
 184 reg [4:0]       Preamble_counter;//
 185 reg [7:0]       TxD_tmp             ;
 186 reg             TxEn_tmp            ;
 187 reg [15:0]      Tx_pkt_length_rmon  ;
 188 reg             Tx_apply_rmon       ;
 189 reg             Tx_apply_rmon_tmp   ;
 190 reg             Tx_apply_rmon_tmp_pl1;
 191 reg [2:0]       Tx_pkt_err_type_rmon;
 192 reg [3:0]       RetryCnt            ;
 193 reg             Random_init         ;
 194 reg             Fifo_rd_finish      ;
 195 reg             Fifo_rd_retry       ;
 196 reg [7:0]       TxD                 ;
 197 reg             TxEn                ;
 198 reg             CRC_init            ;
 199 reg             Data_en             ;
 200 reg             CRC_rd              ;
 201 reg             Fifo_rd             ;
 202 reg             MAC_tx_addr_rd      ;
 203 reg             MAC_header_slot     ;
 204 reg             MAC_header_slot_tmp ;
 205 reg [2:0]       Tx_pkt_type_rmon    ;
 206 wire            Collision           ;
 207 reg             MAC_tx_addr_init    ;
 208 reg             Src_MAC_ptr         ;
 209 reg [7:0]       IPLengthCounter     ;//for pad append
 210 reg [1:0]       PADCounter          ;
 211 reg [7:0]       JamCounter          ;
 212 reg             PktDrpEvenPtr       ;
 213 reg [7:0]       pause_counter       ;
 214 reg             pause_quanta_sub    ;
 215 reg             pause_frame_send_en_dl1 ;
 216 reg [15:0]      pause_quanta_set_dl1    ;
 217 reg             xoff_gen_complete   ;
 218 reg             xon_gen_complete    ;
 219 //******************************************************************************
 220 //boundery signal processing
 221 //******************************************************************************
 222 always @(posedge Clk or posedge Reset)
 223     if (Reset)
 224         begin
 225         pause_frame_send_en_dl1         <=0;
 226         pause_quanta_set_dl1            <=0;
 227         end
 228     else
 229         begin
 230         pause_frame_send_en_dl1         <=pause_frame_send_en   ;
 231         pause_quanta_set_dl1            <=pause_quanta_set      ;
 232         end
 233 //******************************************************************************
 234 //state machine
 235 //******************************************************************************
 236 assign Collision=TxEn&CRS;
 237
 238 always @(posedge Clk or posedge Reset)
 239     if (Reset)
 240         pause_counter   <=0;
 241     else if (Current_state!=StatePause)
 242         pause_counter   <=0;
 243     else
 244         pause_counter   <=pause_counter+1;
 245
 246 always @(posedge Clk or posedge Reset)
 247     if (Reset)
 248         IPLengthCounter     <=0;
 249     else if (Current_state==StateDefer)
 250         IPLengthCounter     <=0;
 251     else if (IPLengthCounter!=8'hff&&(Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD))
 252         IPLengthCounter     <=IPLengthCounter+1;
 253
 254 always @(posedge Clk or posedge Reset)
 255     if (Reset)
 256         PADCounter      <=0;
 257     else if (Current_state!=StatePAD)
 258         PADCounter      <=0;
 259     else
 260         PADCounter      <=PADCounter+1;
 261
 262 always @(posedge Clk or posedge Reset)
 263     if (Reset)
 264         Current_state       <=StateDefer;
 265     else
 266         Current_state       <=Next_state;
 267
 268 always @ (*)
 269         case (Current_state)
 270             StateDefer:
 271                 if ((FullDuplex)||(!FullDuplex&&!CRS))
 272                     Next_state=StateIFG;
 273                 else
 274                     Next_state=Current_state;
 275             StateIFG:
 276                 if (!FullDuplex&&CRS)
 277                     Next_state=StateDefer;
 278                 else if ((FullDuplex&&IFG_counter==IFGset-4)||(!FullDuplex&&!CRS&&IFG_counter==IFGset-4))//remove some additional time
 279                     Next_state=StateIdle;
 280                 else
 281                     Next_state=Current_state;
 282             StateIdle:
 283                 if (!FullDuplex&&CRS)
 284                     Next_state=StateDefer;
 285                 else if (pause_apply)
 286                     Next_state=StatePause;
 287                 else if ((FullDuplex&&Fifo_ra)||(!FullDuplex&&!CRS&&Fifo_ra)||(pause_frame_send_en_dl1&&(xoff_gen||xon_gen)))
 288                     Next_state=StatePreamble;
 289                 else
 290                     Next_state=Current_state;
 291             StatePause:
 292                 if (pause_counter==512/8)
 293                     Next_state=StateDefer;
 294                 else
 295                     Next_state=Current_state;
 296             StatePreamble:
 297                 if (!FullDuplex&&Collision)
 298                     Next_state=StateJam;
 299                 else if ((FullDuplex&&Preamble_counter==6)||(!FullDuplex&&!Collision&&Preamble_counter==6))
 300                     Next_state=StateSFD;
 301                 else
 302                     Next_state=Current_state;
 303             StateSFD:
 304                 if (!FullDuplex&&Collision)
 305                     Next_state=StateJam;
 306                 else if (pause_frame_send_en_dl1&&(xoff_gen||xon_gen))
 307                     Next_state=StateSendPauseFrame;
 308                 else
 309                     Next_state=StateData;
 310             StateSendPauseFrame:
 311                 if (IPLengthCounter==17)
 312                     Next_state=StatePAD;
 313                 else
 314                     Next_state=Current_state;
 315             StateData:
 316                 if (!FullDuplex&&Collision)
 317                     Next_state=StateJam;
 318                 else if (Fifo_data_err_empty)
 319                     Next_state=StateFFEmptyDrop;
 320                 else if (Fifo_eop&&IPLengthCounter>=59)//IP+MAC+TYPE=60 ,start from 0
 321                     Next_state=StateFCS;
 322                 else if (Fifo_eop)
 323                     Next_state=StatePAD;
 324                 else
 325                     Next_state=StateData;
 326             StatePAD:
 327                 if (!FullDuplex&&Collision)
 328                     Next_state=StateJam;
 329                 else if (IPLengthCounter>=59)
 330                     Next_state=StateFCS;
 331                 else
 332                     Next_state=Current_state;
 333             StateJam:
 334                 if (RetryCnt<=MaxRetry&&JamCounter==16)
 335                     Next_state=StateBackOff;
 336                 else if (RetryCnt>MaxRetry)
 337                     Next_state=StateJamDrop;
 338                 else
 339                     Next_state=Current_state;
 340             StateBackOff:
 341                 if (Random_time_meet)
 342                     Next_state  =StateDefer;
 343                 else
 344                     Next_state  =Current_state;
 345             StateFCS:
 346                 if (!FullDuplex&&Collision)
 347                     Next_state  =StateJam;
 348                 else if (CRC_end)
 349                     Next_state  =StateSwitchNext;
 350                 else
 351                     Next_state  =Current_state;
 352             StateFFEmptyDrop:
 353                 if (Fifo_eop)
 354                     Next_state  =StateSwitchNext;
 355                 else
 356                     Next_state  =Current_state;
 357             StateJamDrop:
 358                 if (Fifo_eop)
 359                     Next_state  =StateSwitchNext;
 360                 else
 361                     Next_state  =Current_state;
 362             StateSwitchNext:
 363                     Next_state  =StateDefer;
 364             default:
 365                 Next_state  =StateDefer;
 366         endcase
 367
 368
 369
 370 always @ (posedge Clk or posedge Reset)
 371     if (Reset)
 372         JamCounter      <=0;
 373     else if (Current_state!=StateJam)
 374         JamCounter      <=0;
 375     else if (Current_state==StateJam)
 376         JamCounter      <=JamCounter+1;
 377
 378
 379 always @ (posedge Clk or posedge Reset)
 380     if (Reset)
 381         RetryCnt        <=0;
 382     else if (Current_state==StateSwitchNext)
 383         RetryCnt        <=0;
 384     else if (Current_state==StateJam&&Next_state==StateBackOff)
 385         RetryCnt        <=RetryCnt + 1;
 386
 387 always @ (posedge Clk or posedge Reset)
 388     if (Reset)
 389         IFG_counter     <=0;
 390     else if (Current_state!=StateIFG)
 391         IFG_counter     <=0;
 392     else
 393         IFG_counter     <=IFG_counter + 1;
 394
 395 always @ (posedge Clk or posedge Reset)
 396     if (Reset)
 397         Preamble_counter    <=0;
 398     else if (Current_state!=StatePreamble)
 399         Preamble_counter    <=0;
 400     else
 401         Preamble_counter    <=Preamble_counter+ 1;
 402
 403 always @ (posedge Clk or posedge Reset)
 404     if (Reset)
 405         PktDrpEvenPtr       <=0;
 406     else if(Current_state==StateJamDrop||Current_state==StateFFEmptyDrop)
 407         PktDrpEvenPtr       <=~PktDrpEvenPtr;
 408 //******************************************************************************
 409 //generate output signals
 410 //******************************************************************************
 411 //CRC related
 412 always @(Current_state)
 413     if (Current_state==StateSFD)
 414         CRC_init    =1;
 415     else
 416         CRC_init    =0;
 417
 418 assign Frame_data=TxD_tmp;
 419
 420 always @(Current_state)
 421     if (Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD)
 422         Data_en     =1;
 423     else
 424         Data_en     =0;
 425
 426 always @(Current_state)
 427     if (Current_state==StateFCS)
 428         CRC_rd      =1;
 429     else
 430         CRC_rd      =0;
 431
 432 //Ramdon_gen interface
 433 always @(Current_state or Next_state)
 434     if (Current_state==StateJam&&Next_state==StateBackOff)
 435         Random_init =1;
 436     else
 437         Random_init =0;
 438
 439 //MAC_rx_FF
 440 //data have one cycle delay after fifo read signals
 441 always @ (*)
 442     if (Current_state==StateData ||
 443         Current_state==StateSFD&&!(pause_frame_send_en_dl1&&(xoff_gen||xon_gen))  ||
 444         Current_state==StateJamDrop&&PktDrpEvenPtr||
 445         Current_state==StateFFEmptyDrop&&PktDrpEvenPtr )
 446         Fifo_rd     =1;
 447     else
 448         Fifo_rd     =0;
 449
 450 always @ (Current_state)
 451     if (Current_state==StateSwitchNext)
 452         Fifo_rd_finish  =1;
 453     else
 454         Fifo_rd_finish  =0;
 455
 456 always @ (Current_state)
 457     if (Current_state==StateJam)
 458         Fifo_rd_retry   =1;
 459     else
 460         Fifo_rd_retry   =0;
 461 //RMII
 462 always @(Current_state)
 463     if (Current_state==StatePreamble||Current_state==StateSFD||
 464         Current_state==StateData||Current_state==StateSendPauseFrame||
 465         Current_state==StateFCS||Current_state==StatePAD||Current_state==StateJam)
 466         TxEn_tmp    =1;
 467     else
 468         TxEn_tmp    =0;
 469
 470 //gen txd data
 471 always @(*)
 472     case (Current_state)
 473         StatePreamble:
 474             TxD_tmp =8'h55;
 475         StateSFD:
 476             TxD_tmp =8'hd5;
 477         StateData:
 478             if (Src_MAC_ptr&&MAC_tx_add_en)
 479                 TxD_tmp =MAC_tx_addr_data;
 480             else
 481                 TxD_tmp =Fifo_data;
 482         StateSendPauseFrame:
 483             if (Src_MAC_ptr&&MAC_tx_add_en)
 484                 TxD_tmp =MAC_tx_addr_data;
 485             else
 486                 case (IPLengthCounter)
 487                     7'd0:   TxD_tmp =8'h01;
 488                     7'd1:   TxD_tmp =8'h80;
 489                     7'd2:   TxD_tmp =8'hc2;
 490                     7'd3:   TxD_tmp =8'h00;
 491                     7'd4:   TxD_tmp =8'h00;
 492                     7'd5:   TxD_tmp =8'h01;
 493                     7'd12:  TxD_tmp =8'h88;//type
 494                     7'd13:  TxD_tmp =8'h08;//
 495                     7'd14:  TxD_tmp =8'h00;//opcode
 496                     7'd15:  TxD_tmp =8'h01;
 497                     7'd16:  TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[15:8];
 498                     7'd17:  TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[7:0];
 499 //                    7'd60:  TxD_tmp =8'h26;
 500 //                    7'd61:  TxD_tmp =8'h6b;
 501 //                    7'd62:  TxD_tmp =8'hae;
 502 //                    7'd63:  TxD_tmp =8'h0a;
 503                     default:TxD_tmp =0;
 504                 endcase
 505
 506         StatePAD:
 507                 TxD_tmp =8'h00;
 508         StateJam:
 509                 TxD_tmp =8'h01; //jam sequence
 510         StateFCS:
 511             TxD_tmp =CRC_out;
 512         default:
 513             TxD_tmp =2'b0;
 514     endcase
 515 always @ (posedge Clk or posedge Reset)
 516     if (Reset)
 517         begin
 518         TxD     <=0;
 519         TxEn    <=0;
 520         end
 521     else
 522         begin
 523         TxD     <=TxD_tmp;
 524         TxEn    <=TxEn_tmp;
 525         end
 526 //RMON
 527
 528
 529 always @ (posedge Clk or posedge Reset)
 530     if (Reset)
 531         Tx_pkt_length_rmon      <=0;
 532     else if (Current_state==StateSFD)
 533         Tx_pkt_length_rmon      <=0;
 534     else if (Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD||Current_state==StateFCS)
 535         Tx_pkt_length_rmon      <=Tx_pkt_length_rmon+1;
 536
 537 always @ (posedge Clk or posedge Reset)
 538     if (Reset)
 539         Tx_apply_rmon_tmp       <=0;
 540     else if ((Fifo_eop&&Current_state==StateJamDrop)||
 541              (Fifo_eop&&Current_state==StateFFEmptyDrop)||
 542              CRC_end)
 543         Tx_apply_rmon_tmp       <=1;
 544     else
 545         Tx_apply_rmon_tmp       <=0;
 546
 547 always @ (posedge Clk or posedge Reset)
 548     if (Reset)
 549         Tx_apply_rmon_tmp_pl1   <=0;
 550     else
 551         Tx_apply_rmon_tmp_pl1   <=Tx_apply_rmon_tmp;
 552
 553 always @ (posedge Clk or posedge Reset)
 554     if (Reset)
 555         Tx_apply_rmon       <=0;
 556     else if ((Fifo_eop&&Current_state==StateJamDrop)||
 557              (Fifo_eop&&Current_state==StateFFEmptyDrop)||
 558              CRC_end)
 559         Tx_apply_rmon       <=1;
 560     else if (Tx_apply_rmon_tmp_pl1)
 561         Tx_apply_rmon       <=0;
 562
 563 always @ (posedge Clk or posedge Reset)
 564     if (Reset)
 565         Tx_pkt_err_type_rmon    <=0;
 566     else if(Fifo_eop&&Current_state==StateJamDrop)
 567         Tx_pkt_err_type_rmon    <=3'b001;//
 568     else if(Fifo_eop&&Current_state==StateFFEmptyDrop)
 569         Tx_pkt_err_type_rmon    <=3'b010;//underflow
 570     else if(Fifo_eop&&Fifo_data_err_full)
 571         Tx_pkt_err_type_rmon    <=3'b011;//overflow
 572     else if(CRC_end)
 573         Tx_pkt_err_type_rmon    <=3'b100;//normal
 574
 575 always @ (posedge Clk or posedge Reset)
 576     if (Reset)
 577         MAC_header_slot_tmp <=0;
 578     else if(Current_state==StateSFD&&Next_state==StateData)
 579         MAC_header_slot_tmp <=1;
 580     else
 581         MAC_header_slot_tmp <=0;
 582
 583 always @ (posedge Clk or posedge Reset)
 584     if (Reset)
 585         MAC_header_slot     <=0;
 586     else
 587         MAC_header_slot     <=MAC_header_slot_tmp;
 588
 589 always @ (posedge Clk or posedge Reset)
 590     if (Reset)
 591         Tx_pkt_type_rmon    <=0;
 592     else if (Current_state==StateSendPauseFrame)
 593         Tx_pkt_type_rmon    <=3'b100;
 594     else if(MAC_header_slot)
 595         Tx_pkt_type_rmon    <={1'b0,TxD[7:6]};
 596
 597
 598 always @(Tx_pkt_length_rmon)
 599     if (Tx_pkt_length_rmon>=6&&Tx_pkt_length_rmon<=11)
 600         Src_MAC_ptr         =1;
 601     else
 602         Src_MAC_ptr         =0;
 603
 604 //MAC_tx_addr_add
 605 always @ (posedge Clk or posedge Reset)
 606     if (Reset)
 607         MAC_tx_addr_rd  <=0;
 608     else if ((Tx_pkt_length_rmon>=4&&Tx_pkt_length_rmon<=9)&&(MAC_tx_add_en||Current_state==StateSendPauseFrame))
 609         MAC_tx_addr_rd  <=1;
 610     else
 611         MAC_tx_addr_rd  <=0;
 612
 613 always @ (Tx_pkt_length_rmon or Fifo_rd)
 614     if ((Tx_pkt_length_rmon==3)&&Fifo_rd)
 615         MAC_tx_addr_init=1;
 616     else
 617         MAC_tx_addr_init=0;
 618
 619 //flow control
 620 always @ (posedge Clk or posedge Reset)
 621     if (Reset)
 622         pause_quanta_sub    <=0;
 623     else if(pause_counter==512/8)
 624         pause_quanta_sub    <=1;
 625     else
 626         pause_quanta_sub    <=0;
 627
 628
 629 always @ (posedge Clk or posedge Reset)
 630     if (Reset)
 631         xoff_gen_complete   <=0;
 632     else if(Current_state==StateDefer&&xoff_gen)
 633         xoff_gen_complete   <=1;
 634     else
 635         xoff_gen_complete   <=0;
 636
 637
 638 always @ (posedge Clk or posedge Reset)
 639     if (Reset)
 640         xon_gen_complete    <=0;
 641     else if(Current_state==StateDefer&&xon_gen)
 642         xon_gen_complete    <=1;
 643     else
 644         xon_gen_complete    <=0;
 645
 646 endmodule