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   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  MAC_top.v                                                   ////
   4 ////                                                              ////
   5 ////  This file is part of the Ethernet IP core project           ////
   6 ////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Jon Gao (gaojon@yahoo.com)                            ////
  10 ////                                                              ////
  11 ////                                                              ////
  12 //////////////////////////////////////////////////////////////////////
  13 ////                                                              ////
  14 //// Copyright (C) 2001 Authors                                   ////
  15 ////                                                              ////
  16 //// This source file may be used and distributed without         ////
  17 //// restriction provided that this copyright statement is not    ////
  18 //// removed from the file and that any derivative work contains  ////
  19 //// the original copyright notice and the associated disclaimer. ////
  20 ////                                                              ////
  21 //// This source file is free software; you can redistribute it   ////
  22 //// and/or modify it under the terms of the GNU Lesser General   ////
  23 //// Public License as published by the Free Software Foundation; ////
  24 //// either version 2.1 of the License, or (at your option) any   ////
  25 //// later version.                                               ////
  26 ////                                                              ////
  27 //// This source is distributed in the hope that it will be       ////
  28 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  29 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  30 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  31 //// details.                                                     ////
  32 ////                                                              ////
  33 //// You should have received a copy of the GNU Lesser General    ////
  34 //// Public License along with this source; if not, download it   ////
  35 //// from http://www.opencores.org/lgpl.shtml                     ////
  36 ////                                                              ////
  37 //////////////////////////////////////////////////////////////////////
  38 //
  39 // CVS Revision History
  40 //
  41 // $Log: MAC_top.v,v $
  42 // Revision 1.3  2006/01/19 14:07:52  maverickist
  43 // verification is complete.
  44 //
  45 // Revision 1.2  2005/12/16 06:44:13  Administrator
  46 // replaced tab with space.
  47 // passed 9.6k length frame test.
  48 //
  49 // Revision 1.1.1.1  2005/12/13 01:51:44  Administrator
  50 // no message
  51 //
  52
  53 module MAC_top(
  54                 //system signals
  55 input           Reset                   ,
  56 input           Clk_125M                ,
  57 input           Clk_user                ,
  58 input           Clk_reg                 ,
  59 output  [2:0]   Speed                   ,
  60                 //user interface
  61 output          Rx_mac_ra               ,
  62 input           Rx_mac_rd               ,
  63 output  [31:0]  Rx_mac_data             ,
  64 output  [1:0]   Rx_mac_BE               ,
  65 output          Rx_mac_pa               ,
  66 output          Rx_mac_sop              ,
  67 output          Rx_mac_eop              ,
  68                 //user interface
  69 output          Tx_mac_wa               ,
  70 input           Tx_mac_wr               ,
  71 input   [31:0]  Tx_mac_data             ,
  72 input   [1:0]   Tx_mac_BE               ,//big endian
  73 input           Tx_mac_sop              ,
  74 input           Tx_mac_eop              ,
  75                 //Phy interface
  76                 //Phy interface
  77 output          Gtx_clk                 ,//used only in GMII mode
  78 input           Rx_clk                  ,
  79 input           Tx_clk                  ,//used only in MII mode
  80 output          Tx_er                   ,
  81 output          Tx_en                   ,
  82 output  [7:0]   Txd                     ,
  83 input           Rx_er                   ,
  84 input           Rx_dv                   ,
  85 input   [7:0]   Rxd                     ,
  86 input           Crs                     ,
  87 input           Col                     ,
  88                 //host interface
  89 input           CSB                     ,
  90 input           WRB                     ,
  91 input   [15:0]  CD_in                   ,
  92 output  [15:0]  CD_out                  ,
  93 input   [7:0]   CA                      ,
  94                 //mdx
  95 inout           Mdio                    ,// MII Management Data In
  96 output          Mdc                      // MII Management Data Clock
  97
  98 );
  99 //******************************************************************************
 100 //internal signals
 101 //******************************************************************************
 102                 //RMON interface
 103 wire    [15:0]  Rx_pkt_length_rmon      ;
 104 wire            Rx_apply_rmon           ;
 105 wire    [2:0]   Rx_pkt_err_type_rmon    ;
 106 wire    [2:0]   Rx_pkt_type_rmon        ;
 107 wire    [2:0]   Tx_pkt_type_rmon        ;
 108 wire    [15:0]  Tx_pkt_length_rmon      ;
 109 wire            Tx_apply_rmon           ;
 110 wire    [2:0]   Tx_pkt_err_type_rmon    ;
 111                 //PHY interface
 112 wire            MCrs_dv                 ;
 113 wire    [7:0]   MRxD                    ;
 114 wire            MRxErr                  ;
 115                 //flow_control signals
 116 wire    [15:0]  pause_quanta            ;
 117 wire            pause_quanta_val        ;
 118                 //PHY interface
 119 wire    [7:0]   MTxD                    ;
 120 wire            MTxEn                   ;
 121 wire            MCRS                    ;
 122                 //interface clk signals
 123 wire            MAC_tx_clk              ;
 124 wire            MAC_rx_clk              ;
 125 wire            MAC_tx_clk_div          ;
 126 wire            MAC_rx_clk_div          ;
 127                 //reg signals
 128 wire    [4:0]   Tx_Hwmark                               ;
 129 wire    [4:0]   Tx_Lwmark                               ;
 130 wire                    pause_frame_send_en             ;
 131 wire    [15:0]  pause_quanta_set                ;
 132 wire                    MAC_tx_add_en                   ;
 133 wire                    FullDuplex                      ;
 134 wire    [3:0]   MaxRetry                        ;
 135 wire    [5:0]   IFGset                                  ;
 136 wire    [7:0]   MAC_tx_add_prom_data    ;
 137 wire    [2:0]   MAC_tx_add_prom_add             ;
 138 wire                    MAC_tx_add_prom_wr              ;
 139 wire                    tx_pause_en                             ;
 140 wire                    xoff_cpu                        ;
 141 wire                    xon_cpu                 ;
 142                                         //Rx host interface
 143 wire                    MAC_rx_add_chk_en               ;
 144 wire    [7:0]   MAC_rx_add_prom_data    ;
 145 wire    [2:0]   MAC_rx_add_prom_add             ;
 146 wire                    MAC_rx_add_prom_wr              ;
 147 wire                    broadcast_filter_en         ;
 148 wire    [15:0]  broadcast_MAX           ;
 149 wire                    RX_APPEND_CRC                   ;
 150 wire    [4:0]   Rx_Hwmark                           ;
 151 wire    [4:0]   Rx_Lwmark                           ;
 152 wire                    CRC_chk_en                              ;
 153 wire    [5:0]   RX_IFG_SET                              ;
 154 wire    [15:0]  RX_MAX_LENGTH                   ;
 155 wire    [6:0]   RX_MIN_LENGTH                   ;
 156                                         //RMON host interface
 157 wire    [5:0]   CPU_rd_addr                             ;
 158 wire                    CPU_rd_apply                    ;
 159 wire                    CPU_rd_grant                    ;
 160 wire    [31:0]  CPU_rd_dout                             ;
 161                                         //Phy int host interface
 162 wire                    Line_loop_en                    ;
 163                                         //MII to CPU
 164 wire    [7:0]   Divider                         ;
 165 wire    [15:0]  CtrlData                        ;
 166 wire    [4:0]   Rgad                            ;
 167 wire    [4:0]   Fiad                            ;
 168 wire            NoPre                           ;
 169 wire            WCtrlData                       ;
 170 wire            RStat                           ;
 171 wire            ScanStat                        ;
 172 wire            Busy                            ;
 173 wire            LinkFail                        ;
 174 wire            Nvalid                          ;
 175 wire    [15:0]  Prsd                            ;
 176 wire            WCtrlDataStart                  ;
 177 wire            RStatStart                      ;
 178 wire            UpdateMIIRX_DATAReg             ;
 179 wire    [15:0]  broadcast_bucket_depth              ;
 180 wire    [15:0]  broadcast_bucket_interval           ;
 181
 182 //******************************************************************************
 183 //internal signals
 184 //******************************************************************************
 185 MAC_rx U_MAC_rx(
 186 .Reset                      (Reset                      ),
 187 .Clk_user                   (Clk_user                   ),
 188 .Clk                        (MAC_rx_clk_div             ),
 189  //RMII interface           (//PHY interface            ),
 190 .MCrs_dv                    (MCrs_dv                    ),
 191 .MRxD                       (MRxD                       ),
 192 .MRxErr                     (MRxErr                     ),
 193  //flow_control signals     (//flow_control signals     ),
 194 .pause_quanta               (pause_quanta               ),
 195 .pause_quanta_val           (pause_quanta_val           ),
 196  //user interface           (//user interface           ),
 197 .Rx_mac_ra                  (Rx_mac_ra                  ),
 198 .Rx_mac_rd                  (Rx_mac_rd                  ),
 199 .Rx_mac_data                (Rx_mac_data                ),
 200 .Rx_mac_BE                  (Rx_mac_BE                  ),
 201 .Rx_mac_pa                  (Rx_mac_pa                  ),
 202 .Rx_mac_sop                 (Rx_mac_sop                 ),
 203 .Rx_mac_eop                 (Rx_mac_eop                 ),
 204  //CPU                      (//CPU                      ),
 205 .MAC_rx_add_chk_en          (MAC_rx_add_chk_en          ),
 206 .MAC_add_prom_data          (MAC_rx_add_prom_data       ),
 207 .MAC_add_prom_add           (MAC_rx_add_prom_add        ),
 208 .MAC_add_prom_wr            (MAC_rx_add_prom_wr         ),
 209 .broadcast_filter_en        (broadcast_filter_en        ),
 210 .broadcast_bucket_depth     (broadcast_bucket_depth     ),
 211 .broadcast_bucket_interval  (broadcast_bucket_interval  ),
 212 .RX_APPEND_CRC              (RX_APPEND_CRC              ),
 213 .Rx_Hwmark                  (Rx_Hwmark                  ),
 214 .Rx_Lwmark                  (Rx_Lwmark                  ),
 215 .CRC_chk_en                 (CRC_chk_en                 ),
 216 .RX_IFG_SET                 (RX_IFG_SET                 ),
 217 .RX_MAX_LENGTH              (RX_MAX_LENGTH              ),
 218 .RX_MIN_LENGTH              (RX_MIN_LENGTH              ),
 219  //RMON interface           (//RMON interface           ),
 220 .Rx_pkt_length_rmon         (Rx_pkt_length_rmon         ),
 221 .Rx_apply_rmon              (Rx_apply_rmon              ),
 222 .Rx_pkt_err_type_rmon       (Rx_pkt_err_type_rmon       ),
 223 .Rx_pkt_type_rmon           (Rx_pkt_type_rmon           )
 224 );
 225
 226 MAC_tx U_MAC_tx(
 227 .Reset                      (Reset                      ),
 228 .Clk                        (MAC_tx_clk_div             ),
 229 .Clk_user                   (Clk_user                   ),
 230  //PHY interface            (//PHY interface            ),
 231 .TxD                        (MTxD                       ),
 232 .TxEn                       (MTxEn                      ),
 233 .CRS                        (MCRS                       ),
 234  //RMON                     (//RMON                     ),
 235 .Tx_pkt_type_rmon           (Tx_pkt_type_rmon           ),
 236 .Tx_pkt_length_rmon         (Tx_pkt_length_rmon         ),
 237 .Tx_apply_rmon              (Tx_apply_rmon              ),
 238 .Tx_pkt_err_type_rmon       (Tx_pkt_err_type_rmon       ),
 239  //user interface           (//user interface           ),
 240 .Tx_mac_wa                  (Tx_mac_wa                  ),
 241 .Tx_mac_wr                  (Tx_mac_wr                  ),
 242 .Tx_mac_data                (Tx_mac_data                ),
 243 .Tx_mac_BE                  (Tx_mac_BE                  ),
 244 .Tx_mac_sop                 (Tx_mac_sop                 ),
 245 .Tx_mac_eop                 (Tx_mac_eop                 ),
 246  //host interface           (//host interface           ),
 247 .Tx_Hwmark                  (Tx_Hwmark                  ),
 248 .Tx_Lwmark                  (Tx_Lwmark                  ),
 249 .pause_frame_send_en        (pause_frame_send_en        ),
 250 .pause_quanta_set           (pause_quanta_set           ),
 251 .MAC_tx_add_en              (MAC_tx_add_en              ),
 252 .FullDuplex                 (FullDuplex                 ),
 253 .MaxRetry                   (MaxRetry                   ),
 254 .IFGset                     (IFGset                     ),
 255 .MAC_add_prom_data          (MAC_tx_add_prom_data       ),
 256 .MAC_add_prom_add           (MAC_tx_add_prom_add        ),
 257 .MAC_add_prom_wr            (MAC_tx_add_prom_wr         ),
 258 .tx_pause_en                (tx_pause_en                ),
 259 .xoff_cpu                   (xoff_cpu                   ),
 260 .xon_cpu                    (xon_cpu                    ),
 261  //MAC_rx_flow              (//MAC_rx_flow              ),
 262 .pause_quanta               (pause_quanta               ),
 263 .pause_quanta_val           (pause_quanta_val           )
 264 );
 265
 266 RMON U_RMON(
 267 .Clk                        (Clk_reg                    ),
 268 .Reset                      (Reset                      ),
 269  //Tx_RMON                  (//Tx_RMON                  ),
 270 .Tx_pkt_type_rmon           (Tx_pkt_type_rmon           ),
 271 .Tx_pkt_length_rmon         (Tx_pkt_length_rmon         ),
 272 .Tx_apply_rmon              (Tx_apply_rmon              ),
 273 .Tx_pkt_err_type_rmon       (Tx_pkt_err_type_rmon       ),
 274  //Tx_RMON                  (//Tx_RMON                  ),
 275 .Rx_pkt_type_rmon           (Rx_pkt_type_rmon           ),
 276 .Rx_pkt_length_rmon         (Rx_pkt_length_rmon         ),
 277 .Rx_apply_rmon              (Rx_apply_rmon              ),
 278 .Rx_pkt_err_type_rmon       (Rx_pkt_err_type_rmon       ),
 279  //CPU                      (//CPU                      ),
 280 .CPU_rd_addr                (CPU_rd_addr                ),
 281 .CPU_rd_apply               (CPU_rd_apply               ),
 282 .CPU_rd_grant               (CPU_rd_grant               ),
 283 .CPU_rd_dout                (CPU_rd_dout                )
 284 );
 285
 286 Phy_int U_Phy_int(
 287 .Reset                      (Reset                      ),
 288 .MAC_rx_clk                 (MAC_rx_clk                 ),
 289 .MAC_tx_clk                 (MAC_tx_clk                 ),
 290  //Rx interface             (//Rx interface             ),
 291 .MCrs_dv                    (MCrs_dv                    ),
 292 .MRxD                       (MRxD                       ),
 293 .MRxErr                     (MRxErr                     ),
 294  //Tx interface             (//Tx interface             ),
 295 .MTxD                       (MTxD                       ),
 296 .MTxEn                      (MTxEn                      ),
 297 .MCRS                       (MCRS                       ),
 298  //Phy interface            (//Phy interface            ),
 299 .Tx_er                      (Tx_er                      ),
 300 .Tx_en                      (Tx_en                      ),
 301 .Txd                        (Txd                        ),
 302 .Rx_er                      (Rx_er                      ),
 303 .Rx_dv                      (Rx_dv                      ),
 304 .Rxd                        (Rxd                        ),
 305 .Crs                        (Crs                        ),
 306 .Col                        (Col                        ),
 307  //host interface           (//host interface           ),
 308 .Line_loop_en               (Line_loop_en               ),
 309 .Speed                      (Speed                      )
 310 );
 311
 312 Clk_ctrl U_Clk_ctrl(
 313 .Reset                      (Reset                      ),
 314 .Clk_125M                   (Clk_125M                   ),
 315  //host interface           (//host interface           ),
 316 .Speed                      (Speed                      ),
 317  //Phy interface            (//Phy interface            ),
 318 .Gtx_clk                    (Gtx_clk                    ),
 319 .Rx_clk                     (Rx_clk                     ),
 320 .Tx_clk                     (Tx_clk                     ),
 321  //interface clk            (//interface clk            ),
 322 .MAC_tx_clk                 (MAC_tx_clk                 ),
 323 .MAC_rx_clk                 (MAC_rx_clk                 ),
 324 .MAC_tx_clk_div             (MAC_tx_clk_div             ),
 325 .MAC_rx_clk_div             (MAC_rx_clk_div             )
 326 );
 327
 328 eth_miim U_eth_miim(
 329 .Clk                        (Clk_reg                    ),
 330 .Reset                      (Reset                      ),
 331 .Divider                    (Divider                    ),
 332 .NoPre                      (NoPre                      ),
 333 .CtrlData                   (CtrlData                   ),
 334 .Rgad                       (Rgad                       ),
 335 .Fiad                       (Fiad                       ),
 336 .WCtrlData                  (WCtrlData                  ),
 337 .RStat                      (RStat                      ),
 338 .ScanStat                   (ScanStat                   ),
 339 .Mdio                       (Mdio                       ),
 340 .Mdc                        (Mdc                        ),
 341 .Busy                       (Busy                       ),
 342 .Prsd                       (Prsd                       ),
 343 .LinkFail                   (LinkFail                   ),
 344 .Nvalid                     (Nvalid                     ),
 345 .WCtrlDataStart             (WCtrlDataStart             ),
 346 .RStatStart                 (RStatStart                 ),
 347 .UpdateMIIRX_DATAReg        (UpdateMIIRX_DATAReg        ));
 348
 349 reg_int U_reg_int(
 350 .Reset                          (Reset                          ),
 351 .Clk_reg                        (Clk_reg                        ),
 352 .CSB                        (CSB                        ),
 353 .WRB                        (WRB                        ),
 354 .CD_in                      (CD_in                      ),
 355 .CD_out                     (CD_out                     ),
 356 .CA                         (CA                         ),
 357  //Tx host interface        (//Tx host interface        ),
 358 .Tx_Hwmark                                  (Tx_Hwmark                              ),
 359 .Tx_Lwmark                                  (Tx_Lwmark                              ),
 360 .pause_frame_send_en            (pause_frame_send_en            ),
 361 .pause_quanta_set                   (pause_quanta_set               ),
 362 .MAC_tx_add_en                      (MAC_tx_add_en                          ),
 363 .FullDuplex                     (FullDuplex                     ),
 364 .MaxRetry                           (MaxRetry                       ),
 365 .IFGset                                     (IFGset                                         ),
 366 .MAC_tx_add_prom_data       (MAC_tx_add_prom_data           ),
 367 .MAC_tx_add_prom_add            (MAC_tx_add_prom_add            ),
 368 .MAC_tx_add_prom_wr                 (MAC_tx_add_prom_wr             ),
 369 .tx_pause_en                            (tx_pause_en                            ),
 370 .xoff_cpu                           (xoff_cpu                       ),
 371 .xon_cpu                        (xon_cpu                        ),
 372  //Rx host interface        (//Rx host interface            ),
 373 .MAC_rx_add_chk_en                  (MAC_rx_add_chk_en              ),
 374 .MAC_rx_add_prom_data       (MAC_rx_add_prom_data           ),
 375 .MAC_rx_add_prom_add            (MAC_rx_add_prom_add            ),
 376 .MAC_rx_add_prom_wr                 (MAC_rx_add_prom_wr             ),
 377 .broadcast_filter_en        (broadcast_filter_en            ),
 378 .broadcast_bucket_depth     (broadcast_bucket_depth     ),
 379 .broadcast_bucket_interval  (broadcast_bucket_interval  ),
 380 .RX_APPEND_CRC                      (RX_APPEND_CRC                          ),
 381 .Rx_Hwmark                              (Rx_Hwmark                                      ),
 382 .Rx_Lwmark                  (Rx_Lwmark                  ),
 383 .CRC_chk_en                                 (CRC_chk_en                             ),
 384 .RX_IFG_SET                                 (RX_IFG_SET                             ),
 385 .RX_MAX_LENGTH                      (RX_MAX_LENGTH                          ),
 386 .RX_MIN_LENGTH                      (RX_MIN_LENGTH                          ),
 387  //RMON host interface      (//RMON host interface      ),
 388 .CPU_rd_addr                            (CPU_rd_addr                            ),
 389 .CPU_rd_apply                       (CPU_rd_apply                           ),
 390 .CPU_rd_grant                       (CPU_rd_grant                           ),
 391 .CPU_rd_dout                            (CPU_rd_dout                            ),
 392  //Phy int host interface   (//Phy int host interface   ),
 393 .Line_loop_en                       (Line_loop_en                           ),
 394 .Speed                                      (Speed                                          ),
 395  //MII to CPU               (//MII to CPU               ),
 396 .Divider                        (Divider                        ),
 397 .CtrlData                       (CtrlData                       ),
 398 .Rgad                           (Rgad                           ),
 399 .Fiad                           (Fiad                           ),
 400 .NoPre                          (NoPre                          ),
 401 .WCtrlData                      (WCtrlData                      ),
 402 .RStat                          (RStat                          ),
 403 .ScanStat                       (ScanStat                       ),
 404 .Busy                           (Busy                           ),
 405 .LinkFail                       (LinkFail                       ),
 406 .Nvalid                         (Nvalid                         ),
 407 .Prsd                           (Prsd                           ),
 408 .WCtrlDataStart                 (WCtrlDataStart                 ),
 409 .RStatStart                     (RStatStart                     ),
 410 .UpdateMIIRX_DATAReg            (UpdateMIIRX_DATAReg            )
 411 );
 412
 413 endmodule
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