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   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  MAC_rx_FF.v                                                 ////
   4 ////                                                              ////
   5 ////  This file is part of the Ethernet IP core project           ////
   6 ////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Jon Gao (gaojon@yahoo.com)                            ////
  10 ////                                                              ////
  11 ////                                                              ////
  12 //////////////////////////////////////////////////////////////////////
  13 ////                                                              ////
  14 //// Copyright (C) 2001 Authors                                   ////
  15 ////                                                              ////
  16 //// This source file may be used and distributed without         ////
  17 //// restriction provided that this copyright statement is not    ////
  18 //// removed from the file and that any derivative work contains  ////
  19 //// the original copyright notice and the associated disclaimer. ////
  20 ////                                                              ////
  21 //// This source file is free software; you can redistribute it   ////
  22 //// and/or modify it under the terms of the GNU Lesser General   ////
  23 //// Public License as published by the Free Software Foundation; ////
  24 //// either version 2.1 of the License, or (at your option) any   ////
  25 //// later version.                                               ////
  26 ////                                                              ////
  27 //// This source is distributed in the hope that it will be       ////
  28 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  29 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  30 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  31 //// details.                                                     ////
  32 ////                                                              ////
  33 //// You should have received a copy of the GNU Lesser General    ////
  34 //// Public License along with this source; if not, download it   ////
  35 //// from http://www.opencores.org/lgpl.shtml                     ////
  36 ////                                                              ////
  37 //////////////////////////////////////////////////////////////////////
  38 //
  39 // CVS Revision History
  40 //
  41 // $Log: MAC_rx_FF.v,v $
  42 // Revision 1.5  2006/06/25 04:58:56  maverickist
  43 // no message
  44 //
  45 // Revision 1.4  2006/05/28 05:09:20  maverickist
  46 // no message
  47 //
  48 // Revision 1.3  2006/01/19 14:07:54  maverickist
  49 // verification is complete.
  50 //
  51 // Revision 1.3  2005/12/16 06:44:16  Administrator
  52 // replaced tab with space.
  53 // passed 9.6k length frame test.
  54 //
  55 // Revision 1.2  2005/12/13 12:15:37  Administrator
  56 // no message
  57 //
  58 // Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
  59 // no message
  60 //
  61
  62 module MAC_rx_FF
  63   #(parameter MAC_RX_FF_DEPTH = 9)
  64     (Reset,Clk_MAC,Clk_SYS,
  65      //MAC_rx_ctrl interface
  66      Fifo_data,Fifo_data_en,Fifo_full,Fifo_data_err,Fifo_data_end,
  67      //CPU
  68      Rx_Hwmark,Rx_Lwmark,RX_APPEND_CRC,
  69      //user interface
  70      Rx_mac_ra,Rx_mac_rd,Rx_mac_data,Rx_mac_BE,Rx_mac_sop,Rx_mac_pa,Rx_mac_eop);
  71
  72    input Reset;
  73    input Clk_MAC     ;
  74    input Clk_SYS     ;
  75    //MAC_rx_ctrl interface
  76    input [7:0] Fifo_data       ;
  77    input       Fifo_data_en    ;
  78    output      Fifo_full       ;
  79    input       Fifo_data_err   ;
  80    input       Fifo_data_end   ;
  81    //CPU
  82    input       RX_APPEND_CRC       ;
  83    input [4:0] Rx_Hwmark           ;
  84    input [4:0] Rx_Lwmark           ;
  85    //user interface
  86    output      Rx_mac_ra   ;//
  87    input       Rx_mac_rd   ;
  88    output [31:0] Rx_mac_data ;
  89    output [1:0]  Rx_mac_BE   ;
  90    output        Rx_mac_pa   ;
  91    output        Rx_mac_sop  ;
  92    output        Rx_mac_eop  ;
  93
  94    // ******************************************************************************
  95    //internal signals
  96    // ******************************************************************************
  97    parameter     State_byte3     =4'd0;
  98    parameter     State_byte2     =4'd1;
  99    parameter     State_byte1     =4'd2;
 100    parameter     State_byte0     =4'd3;
 101    parameter     State_be0       =4'd4;
 102    parameter     State_be3       =4'd5;
 103    parameter     State_be2       =4'd6;
 104    parameter     State_be1       =4'd7;
 105    parameter     State_err_end   =4'd8;
 106    parameter     State_idle      =4'd9;
 107
 108    parameter     SYS_read        =3'd0;
 109    parameter     SYS_pause       =3'd1;
 110    parameter     SYS_wait_end    =3'd2;
 111    parameter     SYS_idle        =3'd3;
 112    parameter     FF_emtpy_err    =3'd4;
 113
 114    reg [MAC_RX_FF_DEPTH-1:0] Add_wr;
 115    reg [MAC_RX_FF_DEPTH-1:0] Add_wr_ungray;
 116    reg [MAC_RX_FF_DEPTH-1:0] Add_wr_gray;
 117    reg [MAC_RX_FF_DEPTH-1:0] Add_wr_gray_dl1;
 118    reg [MAC_RX_FF_DEPTH-1:0] Add_wr_reg;
 119
 120    reg [MAC_RX_FF_DEPTH-1:0] Add_rd;
 121    reg [MAC_RX_FF_DEPTH-1:0] Add_rd_gray;
 122    reg [MAC_RX_FF_DEPTH-1:0] Add_rd_gray_dl1;
 123    reg [MAC_RX_FF_DEPTH-1:0] Add_rd_ungray;
 124    reg [35:0]                Din;
 125    reg [35:0]                Din_tmp;
 126    reg [35:0]                Din_tmp_reg;
 127    wire [35:0]               Dout;
 128    reg                       Wr_en;
 129    reg                       Wr_en_tmp;
 130    reg                       Wr_en_ptr;
 131    wire [MAC_RX_FF_DEPTH-1:0] Add_wr_pluse;
 132    wire [MAC_RX_FF_DEPTH-1:0] Add_wr_pluse4;
 133    wire [MAC_RX_FF_DEPTH-1:0] Add_wr_pluse3;
 134    wire [MAC_RX_FF_DEPTH-1:0] Add_wr_pluse2;
 135    reg                        Full;
 136    reg                        Almost_full;
 137    reg                        Empty /* synthesis syn_keep=1 */;
 138    reg [3:0]                  Current_state /* synthesis syn_keep=1 */;
 139    reg [3:0]                  Next_state;
 140    reg [7:0]                  Fifo_data_byte0;
 141    reg [7:0]                  Fifo_data_byte1;
 142    reg [7:0]                  Fifo_data_byte2;
 143    reg [7:0]                  Fifo_data_byte3;
 144    reg                        Fifo_data_en_dl1;
 145    reg [7:0]                  Fifo_data_dl1;
 146    reg                        Rx_mac_sop_tmp  ;
 147    reg                        Rx_mac_sop  ;
 148    reg                        Rx_mac_ra   ;
 149    reg                        Rx_mac_pa   ;
 150
 151
 152
 153    reg [2:0]                  Current_state_SYS /* synthesis syn_keep=1 */;
 154    reg [2:0]                  Next_state_SYS ;
 155    reg [5:0]                  Packet_number_inFF /* synthesis syn_keep=1 */;
 156    reg                        Packet_number_sub ;
 157    wire                       Packet_number_add_edge;
 158    reg                        Packet_number_add_dl1;
 159    reg                        Packet_number_add_dl2;
 160    reg                        Packet_number_add ;
 161    reg                        Packet_number_add_tmp    ;
 162    reg                        Packet_number_add_tmp_dl1;
 163    reg                        Packet_number_add_tmp_dl2;
 164
 165    reg                        Rx_mac_sop_tmp_dl1;
 166    reg [35:0]                 Dout_dl1;
 167    reg [4:0]                  Fifo_data_count;
 168    reg                        Rx_mac_pa_tmp       ;
 169    reg                        Add_wr_jump_tmp     ;
 170    reg                        Add_wr_jump_tmp_pl1 ;
 171    reg                        Add_wr_jump         ;
 172    reg                        Add_wr_jump_rd_pl1  ;
 173    reg [4:0]                  Rx_Hwmark_pl        ;
 174    reg [4:0]                  Rx_Lwmark_pl        ;
 175    integer                    i                   ;
 176
 177    // ******************************************************************************
 178    //domain Clk_MAC,write data to dprom.a-port for write
 179    // ******************************************************************************
 180
 181    always @ (posedge Clk_MAC or posedge Reset)
 182      if (Reset)
 183        Current_state   <=State_idle;
 184      else
 185        Current_state   <=Next_state;
 186
 187    always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end)
 188      case (Current_state)
 189        State_idle:
 190          if (Fifo_data_en)
 191            Next_state  =State_byte3;
 192          else
 193            Next_state  =Current_state;
 194        State_byte3:
 195          if (Fifo_data_en)
 196            Next_state  =State_byte2;
 197          else if (Fifo_data_err)
 198            Next_state  =State_err_end;
 199          else if (Fifo_data_end)
 200            Next_state  =State_be1;
 201          else
 202            Next_state  =Current_state;
 203        State_byte2:
 204          if (Fifo_data_en)
 205            Next_state  =State_byte1;
 206          else if (Fifo_data_err)
 207            Next_state  =State_err_end;
 208          else if (Fifo_data_end)
 209            Next_state  =State_be2;
 210          else
 211            Next_state  =Current_state;
 212        State_byte1:
 213          if (Fifo_data_en)
 214            Next_state  =State_byte0;
 215          else if (Fifo_data_err)
 216            Next_state  =State_err_end;
 217          else if (Fifo_data_end)
 218            Next_state  =State_be3;
 219          else
 220            Next_state  =Current_state;
 221        State_byte0:
 222          if (Fifo_data_en)
 223            Next_state  =State_byte3;
 224          else if (Fifo_data_err)
 225            Next_state  =State_err_end;
 226          else if (Fifo_data_end)
 227            Next_state  =State_be0;
 228          else
 229            Next_state  =Current_state;
 230        State_be1:
 231          Next_state      =State_idle;
 232        State_be2:
 233          Next_state      =State_idle;
 234        State_be3:
 235          Next_state      =State_idle;
 236        State_be0:
 237          Next_state      =State_idle;
 238        State_err_end:
 239          Next_state      =State_idle;
 240        default:
 241          Next_state      =State_idle;
 242      endcase
 243
 244    always @ (posedge Clk_MAC or posedge Reset)
 245      if (Reset)
 246        Add_wr_reg      <=0;
 247      else if (Current_state==State_idle)
 248        Add_wr_reg      <=Add_wr;
 249
 250    always @ (posedge Reset or posedge Clk_MAC)
 251      if (Reset)
 252        Add_wr_gray         <=0;
 253      else
 254        begin
 255           Add_wr_gray[MAC_RX_FF_DEPTH-1]        <=Add_wr[MAC_RX_FF_DEPTH-1];
 256           for (i=MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
 257             Add_wr_gray[i]                      <=Add_wr[i+1]^Add_wr[i];
 258        end
 259
 260    always @ (posedge Clk_MAC or posedge Reset)
 261      if (Reset)
 262        Add_rd_gray_dl1         <=0;
 263      else
 264        Add_rd_gray_dl1         <=Add_rd_gray;
 265
 266    always @ (posedge Clk_MAC or posedge Reset)
 267      if (Reset)
 268        Add_rd_ungray       =0;
 269      else
 270        begin
 271           Add_rd_ungray[MAC_RX_FF_DEPTH-1]      =Add_rd_gray_dl1[MAC_RX_FF_DEPTH-1];
 272           for (i=MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
 273             Add_rd_ungray[i]    =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];
 274        end
 275    assign          Add_wr_pluse=Add_wr+1;
 276    assign          Add_wr_pluse4=Add_wr+4;
 277    assign          Add_wr_pluse3=Add_wr+3;
 278    assign          Add_wr_pluse2=Add_wr+2;
 279
 280
 281
 282    always @ (posedge Clk_MAC or posedge Reset)
 283      if (Reset)
 284        Full    <=0;
 285      else if (Add_wr_pluse==Add_rd_ungray)
 286        Full    <=1;
 287      else
 288        Full    <=0;
 289
 290    always @ (posedge Clk_MAC or posedge Reset)
 291      if (Reset)
 292        Almost_full      <=0;
 293      else if (Add_wr_pluse4==Add_rd_ungray||
 294               Add_wr_pluse3==Add_rd_ungray||
 295               Add_wr_pluse2==Add_rd_ungray||
 296               Add_wr_pluse==Add_rd_ungray
 297               )
 298        Almost_full      <=1;
 299      else
 300        Almost_full      <=0;
 301
 302    assign          Fifo_full =Almost_full;
 303
 304    always @ (posedge Clk_MAC or posedge Reset)
 305      if (Reset)
 306        Add_wr  <=0;
 307      else if (Current_state==State_err_end)
 308        Add_wr  <=Add_wr_reg;
 309      else if (Wr_en&&!Full)
 310        Add_wr  <=Add_wr +1;
 311
 312    always @ (posedge Clk_MAC or posedge Reset)
 313      if (Reset)
 314        Add_wr_jump_tmp <=0;
 315      else if (Current_state==State_err_end)
 316        Add_wr_jump_tmp <=1;
 317      else
 318        Add_wr_jump_tmp <=0;
 319
 320    always @ (posedge Clk_MAC or posedge Reset)
 321      if (Reset)
 322        Add_wr_jump_tmp_pl1 <=0;
 323      else
 324        Add_wr_jump_tmp_pl1 <=Add_wr_jump_tmp;
 325
 326    always @ (posedge Clk_MAC or posedge Reset)
 327      if (Reset)
 328        Add_wr_jump <=0;
 329      else if (Current_state==State_err_end)
 330        Add_wr_jump <=1;
 331      else if (Add_wr_jump_tmp_pl1)
 332        Add_wr_jump <=0;
 333
 334    //
 335    always @ (posedge Clk_MAC or posedge Reset)
 336      if (Reset)
 337        Fifo_data_en_dl1    <=0;
 338      else
 339        Fifo_data_en_dl1    <=Fifo_data_en;
 340
 341    always @ (posedge Clk_MAC or posedge Reset)
 342      if (Reset)
 343        Fifo_data_dl1   <=0;
 344      else
 345        Fifo_data_dl1   <=Fifo_data;
 346
 347    always @ (posedge Clk_MAC or posedge Reset)
 348      if (Reset)
 349        Fifo_data_byte3     <=0;
 350      else if (Current_state==State_byte3&&Fifo_data_en_dl1)
 351        Fifo_data_byte3     <=Fifo_data_dl1;
 352
 353    always @ (posedge Clk_MAC or posedge Reset)
 354      if (Reset)
 355        Fifo_data_byte2     <=0;
 356      else if (Current_state==State_byte2&&Fifo_data_en_dl1)
 357        Fifo_data_byte2     <=Fifo_data_dl1;
 358
 359    always @ (posedge Clk_MAC or posedge Reset)
 360      if (Reset)
 361        Fifo_data_byte1     <=0;
 362      else if (Current_state==State_byte1&&Fifo_data_en_dl1)
 363        Fifo_data_byte1     <=Fifo_data_dl1;
 364
 365    always @ (* )
 366      case (Current_state)
 367        State_be0:
 368          Din_tmp ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
 369        State_be1:
 370          Din_tmp ={4'b1001,Fifo_data_byte3,24'h0};
 371        State_be2:
 372          Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};
 373        State_be3:
 374          Din_tmp ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};
 375        default:
 376          Din_tmp ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
 377      endcase
 378
 379    always @ (*)
 380      if (Current_state==State_be0||Current_state==State_be1||
 381          Current_state==State_be2||Current_state==State_be3||
 382          (Current_state==State_byte0&&Fifo_data_en))
 383        Wr_en_tmp   =1;
 384      else
 385        Wr_en_tmp   =0;
 386
 387    always @ (posedge Clk_MAC or posedge Reset)
 388      if (Reset)
 389        Din_tmp_reg <=0;
 390      else if(Wr_en_tmp)
 391        Din_tmp_reg <=Din_tmp;
 392
 393    always @ (posedge Clk_MAC or posedge Reset)
 394      if (Reset)
 395        Wr_en_ptr   <=0;
 396      else if(Current_state==State_idle)
 397        Wr_en_ptr   <=0;
 398      else if(Wr_en_tmp)
 399        Wr_en_ptr   <=1;
 400
 401    //if not append FCS,delay one cycle write data and Wr_en signal to drop FCS
 402    always @ (posedge Clk_MAC or posedge Reset)
 403      if (Reset)
 404        begin
 405           Wr_en           <=0;
 406           Din             <=0;
 407        end
 408      else if(RX_APPEND_CRC)
 409        begin
 410           Wr_en           <=Wr_en_tmp;
 411           Din             <=Din_tmp;
 412        end
 413      else
 414        begin
 415           Wr_en           <=Wr_en_tmp&&Wr_en_ptr;
 416           Din             <={Din_tmp[35:32],Din_tmp_reg[31:0]};
 417        end
 418
 419    //this signal for read side to handle the packet number in fifo
 420    always @ (posedge Clk_MAC or posedge Reset)
 421      if (Reset)
 422        Packet_number_add_tmp   <=0;
 423      else if (Current_state==State_be0||Current_state==State_be1||
 424               Current_state==State_be2||Current_state==State_be3)
 425        Packet_number_add_tmp   <=1;
 426      else
 427        Packet_number_add_tmp   <=0;
 428
 429    always @ (posedge Clk_MAC or posedge Reset)
 430      if (Reset)
 431        begin
 432           Packet_number_add_tmp_dl1   <=0;
 433           Packet_number_add_tmp_dl2   <=0;
 434        end
 435      else
 436        begin
 437           Packet_number_add_tmp_dl1   <=Packet_number_add_tmp;
 438           Packet_number_add_tmp_dl2   <=Packet_number_add_tmp_dl1;
 439        end
 440
 441    //Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram.
 442    //expand to two cycles long almost=16 ns
 443    //if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles
 444    always @ (posedge Clk_MAC or posedge Reset)
 445      if (Reset)
 446        Packet_number_add   <=0;
 447      else if (Packet_number_add_tmp_dl1||Packet_number_add_tmp_dl2)
 448        Packet_number_add   <=1;
 449      else
 450        Packet_number_add   <=0;
 451
 452    // ******************************************************************************
 453    // domain Clk_SYS,read data from dprom.b-port for read
 454    // ******************************************************************************
 455
 456    always @ (posedge Clk_SYS or posedge Reset)
 457      if (Reset)
 458        Current_state_SYS   <=SYS_idle;
 459      else
 460        Current_state_SYS   <=Next_state_SYS;
 461
 462    always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)
 463      case (Current_state_SYS)
 464        SYS_idle:
 465          if (Rx_mac_rd&&Rx_mac_ra&&!Empty)
 466            Next_state_SYS  =SYS_read;
 467          else if(Rx_mac_rd&&Rx_mac_ra&&Empty)
 468            Next_state_SYS       =FF_emtpy_err;
 469          else
 470            Next_state_SYS  =Current_state_SYS;
 471        SYS_read:
 472          if (!Rx_mac_rd)
 473            Next_state_SYS  =SYS_pause;
 474          else if (Dout[35])
 475            Next_state_SYS  =SYS_wait_end;
 476          else if (Empty)
 477            Next_state_SYS  =FF_emtpy_err;
 478          else
 479            Next_state_SYS  =Current_state_SYS;
 480        SYS_pause:
 481          if (Rx_mac_rd)
 482            Next_state_SYS  =SYS_read;
 483          else
 484            Next_state_SYS  =Current_state_SYS;
 485        FF_emtpy_err:
 486          if (!Empty)
 487            Next_state_SYS  =SYS_read;
 488          else
 489            Next_state_SYS  =Current_state_SYS;
 490        SYS_wait_end:
 491          if (!Rx_mac_rd)
 492            Next_state_SYS  =SYS_idle;
 493          else
 494            Next_state_SYS  =Current_state_SYS;
 495        default:
 496          Next_state_SYS  =SYS_idle;
 497      endcase // case(Current_state_SYS)
 498
 499    //gen Rx_mac_ra
 500    always @ (posedge Clk_SYS or posedge Reset)
 501      if (Reset)
 502        begin
 503           Packet_number_add_dl1   <=0;
 504           Packet_number_add_dl2   <=0;
 505        end
 506      else
 507        begin
 508           Packet_number_add_dl1   <=Packet_number_add;
 509           Packet_number_add_dl2   <=Packet_number_add_dl1;
 510        end
 511    assign  Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2;
 512
 513    always @ (Current_state_SYS or Next_state_SYS)
 514      if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end)
 515        Packet_number_sub       =1;
 516      else
 517        Packet_number_sub       =0;
 518
 519    always @ (posedge Clk_SYS or posedge Reset)
 520      if (Reset)
 521        Packet_number_inFF      <=0;
 522      else if (Packet_number_add_edge&&!Packet_number_sub)
 523        Packet_number_inFF      <=Packet_number_inFF + 1;
 524      else if (!Packet_number_add_edge&&Packet_number_sub&&Packet_number_inFF!=0)
 525        Packet_number_inFF      <=Packet_number_inFF - 1;
 526
 527    always @ (posedge Clk_SYS or posedge Reset)
 528      if (Reset)
 529        Fifo_data_count     <=0;
 530      else
 531        Fifo_data_count     <=Add_wr_ungray[MAC_RX_FF_DEPTH-1:MAC_RX_FF_DEPTH-5]-Add_rd[MAC_RX_FF_DEPTH-1:MAC_RX_FF_DEPTH-5];
 532
 533    always @ (posedge Clk_SYS or posedge Reset)
 534      if (Reset)
 535        begin
 536           Rx_Hwmark_pl        <=0;
 537           Rx_Lwmark_pl        <=0;
 538        end
 539      else
 540        begin
 541           Rx_Hwmark_pl        <=Rx_Hwmark;
 542           Rx_Lwmark_pl        <=Rx_Lwmark;
 543        end
 544
 545    always @ (posedge Clk_SYS or posedge Reset)
 546      if (Reset)
 547        Rx_mac_ra   <=0;
 548      else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark_pl)
 549        Rx_mac_ra   <=0;
 550      else if (Packet_number_inFF>=1||Fifo_data_count>=Rx_Hwmark_pl)
 551        Rx_mac_ra   <=1;
 552
 553
 554    //control Add_rd signal;
 555    always @ (posedge Clk_SYS or posedge Reset)
 556      if (Reset)
 557        Add_rd      <=0;
 558      else if (Current_state_SYS==SYS_read&&!Dout[35])
 559        Add_rd      <=Add_rd + 1;
 560
 561    //
 562    always @ (posedge Reset or posedge Clk_SYS)
 563      if (Reset)
 564        Add_rd_gray         <=0;
 565      else
 566        begin
 567           Add_rd_gray[MAC_RX_FF_DEPTH-1]        <=Add_rd[MAC_RX_FF_DEPTH-1];
 568           for (i=MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
 569             Add_rd_gray[i]                      <=Add_rd[i+1]^Add_rd[i];
 570        end
 571    //
 572
 573    always @ (posedge Clk_SYS or posedge Reset)
 574      if (Reset)
 575        Add_wr_gray_dl1     <=0;
 576      else
 577        Add_wr_gray_dl1     <=Add_wr_gray;
 578
 579    always @ (posedge Clk_SYS or posedge Reset)
 580      if (Reset)
 581        Add_wr_jump_rd_pl1  <=0;
 582      else
 583        Add_wr_jump_rd_pl1  <=Add_wr_jump;
 584
 585    always @ (posedge Clk_SYS or posedge Reset)
 586      if (Reset)
 587        Add_wr_ungray       =0;
 588      else if (!Add_wr_jump_rd_pl1)
 589        begin
 590           Add_wr_ungray[MAC_RX_FF_DEPTH-1]      =Add_wr_gray_dl1[MAC_RX_FF_DEPTH-1];
 591           for (i=MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
 592             Add_wr_ungray[i]    =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];
 593        end
 594    //empty signal gen
 595    always @ (posedge Clk_SYS or posedge Reset)
 596      if (Reset)
 597        Empty   <=1;
 598      else if (Add_rd==Add_wr_ungray)
 599        Empty   <=1;
 600      else
 601        Empty   <=0;
 602
 603    always @ (posedge Clk_SYS or posedge Reset)
 604      if (Reset)
 605        Dout_dl1    <=0;
 606      else
 607        Dout_dl1    <=Dout;
 608
 609    assign  Rx_mac_data     =Dout_dl1[31:0];
 610    assign  Rx_mac_BE       =Dout_dl1[33:32];
 611    assign  Rx_mac_eop      =Dout_dl1[35];
 612
 613    //aligned to Addr_rd
 614    always @ (posedge Clk_SYS or posedge Reset)
 615      if (Reset)
 616        Rx_mac_pa_tmp   <=0;
 617      else if (Current_state_SYS==SYS_read&&!Dout[35])
 618        Rx_mac_pa_tmp   <=1;
 619      else
 620        Rx_mac_pa_tmp   <=0;
 621
 622    always @ (posedge Clk_SYS or posedge Reset)
 623      if (Reset)
 624        Rx_mac_pa   <=0;
 625      else
 626        Rx_mac_pa   <=Rx_mac_pa_tmp;
 627
 628    always @ (posedge Clk_SYS or posedge Reset)
 629      if (Reset)
 630        Rx_mac_sop_tmp      <=0;
 631      else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read)
 632        Rx_mac_sop_tmp      <=1;
 633      else
 634        Rx_mac_sop_tmp      <=0;
 635
 636    always @ (posedge Clk_SYS or posedge Reset)
 637      if (Reset)
 638        begin
 639           Rx_mac_sop_tmp_dl1  <=0;
 640           Rx_mac_sop          <=0;
 641        end
 642      else
 643        begin
 644           Rx_mac_sop_tmp_dl1  <=Rx_mac_sop_tmp;
 645           Rx_mac_sop          <=Rx_mac_sop_tmp_dl1;
 646        end
 647
 648    //******************************************************************************
 649
 650    duram #(36,MAC_RX_FF_DEPTH)
 651      U_duram(.data_a         (Din        ),
 652              .wren_a         (Wr_en      ),
 653              .address_a      (Add_wr     ),
 654              .address_b      (Add_rd     ),
 655              .clock_a        (Clk_MAC    ),
 656              .clock_b        (Clk_SYS    ),
 657              .q_b            (Dout       ));
 658
 659 endmodule // MAC_rx_FF