1 //////////////////////////////////////////////////////////////////////
5 //// This file is part of the Ethernet IP core project ////
6 //// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
9 //// - Jon Gao (gaojon@yahoo.com) ////
12 //////////////////////////////////////////////////////////////////////
14 //// Copyright (C) 2001 Authors ////
16 //// This source file may be used and distributed without ////
17 //// restriction provided that this copyright statement is not ////
18 //// removed from the file and that any derivative work contains ////
19 //// the original copyright notice and the associated disclaimer. ////
21 //// This source file is free software; you can redistribute it ////
22 //// and/or modify it under the terms of the GNU Lesser General ////
23 //// Public License as published by the Free Software Foundation; ////
24 //// either version 2.1 of the License, or (at your option) any ////
25 //// later version. ////
27 //// This source is distributed in the hope that it will be ////
28 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
29 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
30 //// PURPOSE. See the GNU Lesser General Public License for more ////
33 //// You should have received a copy of the GNU Lesser General ////
34 //// Public License along with this source; if not, download it ////
35 //// from http://www.opencores.org/lgpl.shtml ////
37 //////////////////////////////////////////////////////////////////////
39 // CVS Revision History
41 // $Log: MAC_rx_FF.v,v $
42 // Revision 1.5 2006/06/25 04:58:56 maverickist
45 // Revision 1.4 2006/05/28 05:09:20 maverickist
48 // Revision 1.3 2006/01/19 14:07:54 maverickist
49 // verification is complete.
51 // Revision 1.3 2005/12/16 06:44:16 Administrator
52 // replaced tab with space.
53 // passed 9.6k length frame test.
55 // Revision 1.2 2005/12/13 12:15:37 Administrator
58 // Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
63 #(parameter MAC_RX_FF_DEPTH = 9)
64 (Reset,Clk_MAC,Clk_SYS,
65 //MAC_rx_ctrl interface
66 Fifo_data,Fifo_data_en,Fifo_full,Fifo_data_err,Fifo_data_end,
68 Rx_Hwmark,Rx_Lwmark,RX_APPEND_CRC,
70 Rx_mac_ra,Rx_mac_rd,Rx_mac_data,Rx_mac_BE,Rx_mac_sop,Rx_mac_pa,Rx_mac_eop);
75 //MAC_rx_ctrl interface
76 input [7:0] Fifo_data ;
83 input [4:0] Rx_Hwmark ;
84 input [4:0] Rx_Lwmark ;
88 output [31:0] Rx_mac_data ;
89 output [1:0] Rx_mac_BE ;
94 // ******************************************************************************
96 // ******************************************************************************
97 parameter State_byte3 =4'd0;
98 parameter State_byte2 =4'd1;
99 parameter State_byte1 =4'd2;
100 parameter State_byte0 =4'd3;
101 parameter State_be0 =4'd4;
102 parameter State_be3 =4'd5;
103 parameter State_be2 =4'd6;
104 parameter State_be1 =4'd7;
105 parameter State_err_end =4'd8;
106 parameter State_idle =4'd9;
108 parameter SYS_read =3'd0;
109 parameter SYS_pause =3'd1;
110 parameter SYS_wait_end =3'd2;
111 parameter SYS_idle =3'd3;
112 parameter FF_emtpy_err =3'd4;
114 reg [MAC_RX_FF_DEPTH-1:0] Add_wr;
115 reg [MAC_RX_FF_DEPTH-1:0] Add_wr_ungray;
116 reg [MAC_RX_FF_DEPTH-1:0] Add_wr_gray;
117 reg [MAC_RX_FF_DEPTH-1:0] Add_wr_gray_dl1;
118 reg [MAC_RX_FF_DEPTH-1:0] Add_wr_reg;
120 reg [MAC_RX_FF_DEPTH-1:0] Add_rd;
121 reg [MAC_RX_FF_DEPTH-1:0] Add_rd_gray;
122 reg [MAC_RX_FF_DEPTH-1:0] Add_rd_gray_dl1;
123 reg [MAC_RX_FF_DEPTH-1:0] Add_rd_ungray;
126 reg [35:0] Din_tmp_reg;
131 wire [MAC_RX_FF_DEPTH-1:0] Add_wr_pluse;
132 wire [MAC_RX_FF_DEPTH-1:0] Add_wr_pluse4;
133 wire [MAC_RX_FF_DEPTH-1:0] Add_wr_pluse3;
134 wire [MAC_RX_FF_DEPTH-1:0] Add_wr_pluse2;
137 reg Empty /* synthesis syn_keep=1 */;
138 reg [3:0] Current_state /* synthesis syn_keep=1 */;
139 reg [3:0] Next_state;
140 reg [7:0] Fifo_data_byte0;
141 reg [7:0] Fifo_data_byte1;
142 reg [7:0] Fifo_data_byte2;
143 reg [7:0] Fifo_data_byte3;
144 reg Fifo_data_en_dl1;
145 reg [7:0] Fifo_data_dl1;
153 reg [2:0] Current_state_SYS /* synthesis syn_keep=1 */;
154 reg [2:0] Next_state_SYS ;
155 reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */;
156 reg Packet_number_sub ;
157 wire Packet_number_add_edge;
158 reg Packet_number_add_dl1;
159 reg Packet_number_add_dl2;
160 reg Packet_number_add ;
161 reg Packet_number_add_tmp ;
162 reg Packet_number_add_tmp_dl1;
163 reg Packet_number_add_tmp_dl2;
165 reg Rx_mac_sop_tmp_dl1;
167 reg [4:0] Fifo_data_count;
169 reg Add_wr_jump_tmp ;
170 reg Add_wr_jump_tmp_pl1 ;
172 reg Add_wr_jump_rd_pl1 ;
173 reg [4:0] Rx_Hwmark_pl ;
174 reg [4:0] Rx_Lwmark_pl ;
177 // ******************************************************************************
178 //domain Clk_MAC,write data to dprom.a-port for write
179 // ******************************************************************************
181 always @ (posedge Clk_MAC or posedge Reset)
183 Current_state <=State_idle;
185 Current_state <=Next_state;
187 always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end)
191 Next_state =State_byte3;
193 Next_state =Current_state;
196 Next_state =State_byte2;
197 else if (Fifo_data_err)
198 Next_state =State_err_end;
199 else if (Fifo_data_end)
200 Next_state =State_be1;
202 Next_state =Current_state;
205 Next_state =State_byte1;
206 else if (Fifo_data_err)
207 Next_state =State_err_end;
208 else if (Fifo_data_end)
209 Next_state =State_be2;
211 Next_state =Current_state;
214 Next_state =State_byte0;
215 else if (Fifo_data_err)
216 Next_state =State_err_end;
217 else if (Fifo_data_end)
218 Next_state =State_be3;
220 Next_state =Current_state;
223 Next_state =State_byte3;
224 else if (Fifo_data_err)
225 Next_state =State_err_end;
226 else if (Fifo_data_end)
227 Next_state =State_be0;
229 Next_state =Current_state;
231 Next_state =State_idle;
233 Next_state =State_idle;
235 Next_state =State_idle;
237 Next_state =State_idle;
239 Next_state =State_idle;
241 Next_state =State_idle;
244 always @ (posedge Clk_MAC or posedge Reset)
247 else if (Current_state==State_idle)
250 always @ (posedge Reset or posedge Clk_MAC)
255 Add_wr_gray[MAC_RX_FF_DEPTH-1] <=Add_wr[MAC_RX_FF_DEPTH-1];
256 for (i=MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
257 Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];
260 always @ (posedge Clk_MAC or posedge Reset)
264 Add_rd_gray_dl1 <=Add_rd_gray;
266 always @ (posedge Clk_MAC or posedge Reset)
271 Add_rd_ungray[MAC_RX_FF_DEPTH-1] =Add_rd_gray_dl1[MAC_RX_FF_DEPTH-1];
272 for (i=MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
273 Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];
275 assign Add_wr_pluse=Add_wr+1;
276 assign Add_wr_pluse4=Add_wr+4;
277 assign Add_wr_pluse3=Add_wr+3;
278 assign Add_wr_pluse2=Add_wr+2;
282 always @ (posedge Clk_MAC or posedge Reset)
285 else if (Add_wr_pluse==Add_rd_ungray)
290 always @ (posedge Clk_MAC or posedge Reset)
293 else if (Add_wr_pluse4==Add_rd_ungray||
294 Add_wr_pluse3==Add_rd_ungray||
295 Add_wr_pluse2==Add_rd_ungray||
296 Add_wr_pluse==Add_rd_ungray
302 assign Fifo_full =Almost_full;
304 always @ (posedge Clk_MAC or posedge Reset)
307 else if (Current_state==State_err_end)
309 else if (Wr_en&&!Full)
312 always @ (posedge Clk_MAC or posedge Reset)
315 else if (Current_state==State_err_end)
320 always @ (posedge Clk_MAC or posedge Reset)
322 Add_wr_jump_tmp_pl1 <=0;
324 Add_wr_jump_tmp_pl1 <=Add_wr_jump_tmp;
326 always @ (posedge Clk_MAC or posedge Reset)
329 else if (Current_state==State_err_end)
331 else if (Add_wr_jump_tmp_pl1)
335 always @ (posedge Clk_MAC or posedge Reset)
337 Fifo_data_en_dl1 <=0;
339 Fifo_data_en_dl1 <=Fifo_data_en;
341 always @ (posedge Clk_MAC or posedge Reset)
345 Fifo_data_dl1 <=Fifo_data;
347 always @ (posedge Clk_MAC or posedge Reset)
350 else if (Current_state==State_byte3&&Fifo_data_en_dl1)
351 Fifo_data_byte3 <=Fifo_data_dl1;
353 always @ (posedge Clk_MAC or posedge Reset)
356 else if (Current_state==State_byte2&&Fifo_data_en_dl1)
357 Fifo_data_byte2 <=Fifo_data_dl1;
359 always @ (posedge Clk_MAC or posedge Reset)
362 else if (Current_state==State_byte1&&Fifo_data_en_dl1)
363 Fifo_data_byte1 <=Fifo_data_dl1;
368 Din_tmp ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
370 Din_tmp ={4'b1001,Fifo_data_byte3,24'h0};
372 Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};
374 Din_tmp ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};
376 Din_tmp ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
380 if (Current_state==State_be0||Current_state==State_be1||
381 Current_state==State_be2||Current_state==State_be3||
382 (Current_state==State_byte0&&Fifo_data_en))
387 always @ (posedge Clk_MAC or posedge Reset)
391 Din_tmp_reg <=Din_tmp;
393 always @ (posedge Clk_MAC or posedge Reset)
396 else if(Current_state==State_idle)
401 //if not append FCS,delay one cycle write data and Wr_en signal to drop FCS
402 always @ (posedge Clk_MAC or posedge Reset)
408 else if(RX_APPEND_CRC)
415 Wr_en <=Wr_en_tmp&&Wr_en_ptr;
416 Din <={Din_tmp[35:32],Din_tmp_reg[31:0]};
419 //this signal for read side to handle the packet number in fifo
420 always @ (posedge Clk_MAC or posedge Reset)
422 Packet_number_add_tmp <=0;
423 else if (Current_state==State_be0||Current_state==State_be1||
424 Current_state==State_be2||Current_state==State_be3)
425 Packet_number_add_tmp <=1;
427 Packet_number_add_tmp <=0;
429 always @ (posedge Clk_MAC or posedge Reset)
432 Packet_number_add_tmp_dl1 <=0;
433 Packet_number_add_tmp_dl2 <=0;
437 Packet_number_add_tmp_dl1 <=Packet_number_add_tmp;
438 Packet_number_add_tmp_dl2 <=Packet_number_add_tmp_dl1;
441 //Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram.
442 //expand to two cycles long almost=16 ns
443 //if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles
444 always @ (posedge Clk_MAC or posedge Reset)
446 Packet_number_add <=0;
447 else if (Packet_number_add_tmp_dl1||Packet_number_add_tmp_dl2)
448 Packet_number_add <=1;
450 Packet_number_add <=0;
452 // ******************************************************************************
453 // domain Clk_SYS,read data from dprom.b-port for read
454 // ******************************************************************************
456 always @ (posedge Clk_SYS or posedge Reset)
458 Current_state_SYS <=SYS_idle;
460 Current_state_SYS <=Next_state_SYS;
462 always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)
463 case (Current_state_SYS)
465 if (Rx_mac_rd&&Rx_mac_ra&&!Empty)
466 Next_state_SYS =SYS_read;
467 else if(Rx_mac_rd&&Rx_mac_ra&&Empty)
468 Next_state_SYS =FF_emtpy_err;
470 Next_state_SYS =Current_state_SYS;
473 Next_state_SYS =SYS_pause;
475 Next_state_SYS =SYS_wait_end;
477 Next_state_SYS =FF_emtpy_err;
479 Next_state_SYS =Current_state_SYS;
482 Next_state_SYS =SYS_read;
484 Next_state_SYS =Current_state_SYS;
487 Next_state_SYS =SYS_read;
489 Next_state_SYS =Current_state_SYS;
492 Next_state_SYS =SYS_idle;
494 Next_state_SYS =Current_state_SYS;
496 Next_state_SYS =SYS_idle;
497 endcase // case(Current_state_SYS)
500 always @ (posedge Clk_SYS or posedge Reset)
503 Packet_number_add_dl1 <=0;
504 Packet_number_add_dl2 <=0;
508 Packet_number_add_dl1 <=Packet_number_add;
509 Packet_number_add_dl2 <=Packet_number_add_dl1;
511 assign Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2;
513 always @ (Current_state_SYS or Next_state_SYS)
514 if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end)
515 Packet_number_sub =1;
517 Packet_number_sub =0;
519 always @ (posedge Clk_SYS or posedge Reset)
521 Packet_number_inFF <=0;
522 else if (Packet_number_add_edge&&!Packet_number_sub)
523 Packet_number_inFF <=Packet_number_inFF + 1;
524 else if (!Packet_number_add_edge&&Packet_number_sub&&Packet_number_inFF!=0)
525 Packet_number_inFF <=Packet_number_inFF - 1;
527 always @ (posedge Clk_SYS or posedge Reset)
531 Fifo_data_count <=Add_wr_ungray[MAC_RX_FF_DEPTH-1:MAC_RX_FF_DEPTH-5]-Add_rd[MAC_RX_FF_DEPTH-1:MAC_RX_FF_DEPTH-5];
533 always @ (posedge Clk_SYS or posedge Reset)
541 Rx_Hwmark_pl <=Rx_Hwmark;
542 Rx_Lwmark_pl <=Rx_Lwmark;
545 always @ (posedge Clk_SYS or posedge Reset)
548 else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark_pl)
550 else if (Packet_number_inFF>=1||Fifo_data_count>=Rx_Hwmark_pl)
554 //control Add_rd signal;
555 always @ (posedge Clk_SYS or posedge Reset)
558 else if (Current_state_SYS==SYS_read&&!Dout[35])
562 always @ (posedge Reset or posedge Clk_SYS)
567 Add_rd_gray[MAC_RX_FF_DEPTH-1] <=Add_rd[MAC_RX_FF_DEPTH-1];
568 for (i=MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
569 Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i];
573 always @ (posedge Clk_SYS or posedge Reset)
577 Add_wr_gray_dl1 <=Add_wr_gray;
579 always @ (posedge Clk_SYS or posedge Reset)
581 Add_wr_jump_rd_pl1 <=0;
583 Add_wr_jump_rd_pl1 <=Add_wr_jump;
585 always @ (posedge Clk_SYS or posedge Reset)
588 else if (!Add_wr_jump_rd_pl1)
590 Add_wr_ungray[MAC_RX_FF_DEPTH-1] =Add_wr_gray_dl1[MAC_RX_FF_DEPTH-1];
591 for (i=MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
592 Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];
595 always @ (posedge Clk_SYS or posedge Reset)
598 else if (Add_rd==Add_wr_ungray)
603 always @ (posedge Clk_SYS or posedge Reset)
609 assign Rx_mac_data =Dout_dl1[31:0];
610 assign Rx_mac_BE =Dout_dl1[33:32];
611 assign Rx_mac_eop =Dout_dl1[35];
614 always @ (posedge Clk_SYS or posedge Reset)
617 else if (Current_state_SYS==SYS_read&&!Dout[35])
622 always @ (posedge Clk_SYS or posedge Reset)
626 Rx_mac_pa <=Rx_mac_pa_tmp;
628 always @ (posedge Clk_SYS or posedge Reset)
631 else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read)
636 always @ (posedge Clk_SYS or posedge Reset)
639 Rx_mac_sop_tmp_dl1 <=0;
644 Rx_mac_sop_tmp_dl1 <=Rx_mac_sop_tmp;
645 Rx_mac_sop <=Rx_mac_sop_tmp_dl1;
648 //******************************************************************************
650 duram #(36,MAC_RX_FF_DEPTH)
651 U_duram(.data_a (Din ),
653 .address_a (Add_wr ),
654 .address_b (Add_rd ),
659 endmodule // MAC_rx_FF