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   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  reg_int_sim.v                                               ////
   4 ////                                                              ////
   5 ////  This file is part of the Ethernet IP core project           ////
   6 ////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Jon Gao (gaojon@yahoo.com)                            ////
  10 ////                                                              ////
  11 ////                                                              ////
  12 //////////////////////////////////////////////////////////////////////
  13 ////                                                              ////
  14 //// Copyright (C) 2001 Authors                                   ////
  15 ////                                                              ////
  16 //// This source file may be used and distributed without         ////
  17 //// restriction provided that this copyright statement is not    ////
  18 //// removed from the file and that any derivative work contains  ////
  19 //// the original copyright notice and the associated disclaimer. ////
  20 ////                                                              ////
  21 //// This source file is free software; you can redistribute it   ////
  22 //// and/or modify it under the terms of the GNU Lesser General   ////
  23 //// Public License as published by the Free Software Foundation; ////
  24 //// either version 2.1 of the License, or (at your option) any   ////
  25 //// later version.                                               ////
  26 ////                                                              ////
  27 //// This source is distributed in the hope that it will be       ////
  28 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  29 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  30 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  31 //// details.                                                     ////
  32 ////                                                              ////
  33 //// You should have received a copy of the GNU Lesser General    ////
  34 //// Public License along with this source; if not, download it   ////
  35 //// from http://www.opencores.org/lgpl.shtml                     ////
  36 ////                                                              ////
  37 //////////////////////////////////////////////////////////////////////
  38 //
  39 // CVS Revision History
  40 //
  41 // $Log: reg_int_sim.v,v $
  42 // Revision 1.1  2005/12/13 12:54:38  maverickist
  43 // first simulation passed
  44 //
  45
  46 module reg_int_sim (
  47 input                   Reset                                   ,
  48 input                   Clk_reg                                 ,
  49                                 //Tx host interface
  50 output  [4:0]   Tx_Hwmark                               ,
  51 output  [4:0]   Tx_Lwmark                               ,
  52 output                  pause_frame_send_en             ,
  53 output  [15:0]  pause_quanta_set                ,
  54 output                  MAC_tx_add_en                   ,
  55 output                  FullDuplex                      ,
  56 output  [3:0]   MaxRetry                        ,
  57 output  [5:0]   IFGset                                  ,
  58 output  [7:0]   MAC_tx_add_prom_data    ,
  59 output  [2:0]   MAC_tx_add_prom_add             ,
  60 output                  MAC_tx_add_prom_wr              ,
  61 output                  tx_pause_en                             ,
  62 output                  xoff_cpu                        ,
  63 output                  xon_cpu                 ,
  64                                 //Rx host interface
  65 output                  MAC_rx_add_chk_en               ,
  66 output  [7:0]   MAC_rx_add_prom_data    ,
  67 output  [2:0]   MAC_rx_add_prom_add             ,
  68 output                  MAC_rx_add_prom_wr              ,
  69 output                  broadcast_filter_en         ,
  70 output  [15:0]  broadcast_MAX           ,
  71 output                  RX_APPEND_CRC                   ,
  72 output                  CRC_chk_en                              ,
  73 output  [5:0]   RX_IFG_SET                              ,
  74 output  [15:0]  RX_MAX_LENGTH                   ,//     1518
  75 output  [6:0]   RX_MIN_LENGTH                   ,//     64
  76                                 //RMON host interface
  77 output  [5:0]   CPU_rd_addr                             ,
  78 output                  CPU_rd_apply                    ,
  79 input                   CPU_rd_grant                    ,
  80 input   [31:0]  CPU_rd_dout                             ,
  81                                 //Phy int host interface
  82 output                  Line_loop_en                    ,
  83 output  [2:0]   Speed                                   ,
  84                                 //MII to CPU
  85 output  [7:0]   Divider                         ,// Divider for the host clock
  86 output  [15:0]  CtrlData                        ,// Control Data (to be written to the PHY reg.)
  87 output  [4:0]   Rgad                            ,// Register Address (within the PHY)
  88 output  [4:0]   Fiad                            ,// PHY Address
  89 output          NoPre                           ,// No Preamble (no 32-bit preamble)
  90 output          WCtrlData                       ,// Write Control Data operation
  91 output          RStat                           ,// Read Status operation
  92 output          ScanStat                        ,// Scan Status operation
  93 input           Busy                            ,// Busy Signal
  94 input           LinkFail                        ,// Link Integrity Signal
  95 input           Nvalid                          ,// Invalid Status (qualifier for the valid scan result)
  96 input   [15:0]  Prsd                            ,// Read Status Data (data read from the PHY)
  97 input           WCtrlDataStart                  ,// This signals resets the WCTRLDATA bit in the MIIM Command register
  98 input           RStatStart                      ,// This signal resets the RSTAT BIT in the MIIM Command register
  99 input           UpdateMIIRX_DATAReg             ,// Updates MII RX_DATA register with read data
 100 );
 101
 102    assign       Tx_Hwmark                                       =5'h1e;
 103    assign       Tx_Lwmark                                       =5'h19;
 104    assign       pause_frame_send_en                     =0;
 105    assign       pause_quanta_set                            =0;
 106    assign       MAC_tx_add_en                           =0;
 107    assign       FullDuplex                              =1;
 108    assign       MaxRetry                                    =2;
 109    assign       IFGset                                          =10;
 110    assign       MAC_tx_add_prom_data                =0;
 111    assign       MAC_tx_add_prom_add                     =0;
 112    assign       MAC_tx_add_prom_wr                      =0;
 113    assign       tx_pause_en                                     =0;
 114    assign       xoff_cpu                                    =0;
 115    assign       xon_cpu                         =0;
 116
 117    assign       MAC_rx_add_chk_en                               =0;
 118    assign       MAC_rx_add_prom_data             =0;
 119    assign       MAC_rx_add_prom_add                 =0;
 120    assign       MAC_rx_add_prom_wr                  =0;
 121    assign       broadcast_filter_en                 =0;
 122    assign       broadcast_MAX                   =10;
 123    assign       RX_APPEND_CRC                       =0;
 124    assign       CRC_chk_en                                  =1;
 125    assign       RX_IFG_SET                                  =10;
 126    assign       RX_MAX_LENGTH                       =1518;
 127    assign       RX_MIN_LENGTH                       =64;
 128
 129    assign       CPU_rd_addr                                             =0;
 130    assign       CPU_rd_apply                        =0;
 131
 132    assign       Line_loop_en                                            =0;
 133    assign       Speed                                           =3'b001;
 134
 135 endmodule // reg_int_sim