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   1
   2 module host_sim
   3   (input                                Reset                                   ,
   4    input                            Clk_reg                                     ,
   5    output  reg             CSB                     ,
   6    output  reg             WRB                     ,
   7    output  reg             CPU_init_end            ,
   8    output  reg    [15:0]   CD_in                   ,
   9    input          [15:0]   CD_out                  ,
  10    output  reg    [7:0]    CA
  11    );
  12
  13    ////////////////////////////////////////
  14    task    CPU_init;
  15       begin
  16          CA      =0;
  17          CD_in   =0;
  18          WRB     =1;
  19          CSB     =1;
  20       end
  21    endtask
  22
  23    ////////////////////////////////////////
  24    task    CPU_wr;
  25       input[6:0]      Addr;
  26       input[15:0]     Data;
  27       begin
  28          CA      ={Addr,1'b0};
  29          CD_in   =Data;
  30          WRB     =0;
  31          CSB     =0;
  32          #20;
  33          CA      =0;
  34          CD_in   =0;
  35          WRB     =1;
  36          CSB     =1;
  37          #20;
  38       end
  39    endtask
  40    /////////////////////////////////////////
  41    task    CPU_rd;
  42       input[6:0]      Addr;
  43       begin
  44          CA      ={Addr,1'b0};
  45          WRB     =1;
  46          CSB     =0;
  47          #20;
  48          CA      =0;
  49          WRB     =1;
  50          CSB     =1;
  51          #20;
  52       end
  53    endtask
  54    /////////////////////////////////////////
  55
  56    integer         i;
  57
  58    reg [31:0]      CPU_data [255:0];
  59    reg [7:0]       write_times;
  60    reg [7:0]       write_add;
  61    reg [15:0]      write_data;
  62
  63    initial
  64      begin
  65         CPU_init;
  66         CPU_init_end=0;
  67         $readmemh("../data/CPU.vec",CPU_data);
  68         {write_times,write_add,write_data}=CPU_data[0];
  69         #90 ;
  70         for (i=0;i<write_times;i=i+1)
  71           begin
  72              {write_times,write_add,write_data}=CPU_data[i];
  73              CPU_wr(write_add[6:0],write_data);
  74           end
  75         CPU_init_end=1;
  76      end
  77 endmodule // host_sim