1 // Copyright (C) 1991-2005 Altera Corporation
2 // Your use of Altera Corporation's design tools, logic functions
3 // and other software and tools, and its AMPP partner logic
4 // functions, and any output files any of the foregoing
5 // (including device programming or simulation files), and any
6 // associated documentation or information are expressly subject
7 // to the terms and conditions of the Altera Program License
8 // Subscription Agreement, Altera MegaCore Function License
9 // Agreement, or other applicable license agreement, including,
10 // without limitation, that your use is for the sole purpose of
11 // programming logic devices manufactured by Altera and sold by
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13 // applicable agreement for further details.
16 // Quartus II 5.1 Build 176 10/26/2005
19 //START_MODULE_NAME------------------------------------------------------------
21 // Module Name : ALTERA_MF_MEMORY_INITIALIZATION
23 // Description : Common function to read intel-hex format data file with
24 // extension .hex and creates the equivalent verilog format
25 // data file with extension .ver.
27 // Limitation : Supports only record type '00'(data record), '01'(end of
28 // file record) and '02'(extended segment address record).
30 // Results expected: Creates the verilog format data file with extension .ver
31 // and return the name of the file.
33 //END_MODULE_NAME--------------------------------------------------------------
36 `timescale 1 ps / 1 ps
37 module lcell (in, out);
44 // BEGINNING OF MODULE
45 `timescale 1 ps / 1 ps
51 `define MAX_BUFFER_SZ 2048
52 `define MAX_NAME_SZ 128
55 `define CARRIAGE_RETURN 8'h0D
60 `define MASK15 32'h000000FF
64 module ALTERA_MF_MEMORY_INITIALIZATION;
67 /****************************************************************/
68 /* Read in Intel-hex format data to verilog format data. */
69 /* Intel-hex format :nnaaaaattddddcc */
70 /****************************************************************/
72 input[`MAX_NAME_SZ*8 : 1] in_file;
74 output [`MAX_NAME_SZ*8 : 1] out_file;
75 reg [`MAX_NAME_SZ*8 : 1] in_file;
76 reg [`MAX_NAME_SZ*8 : 1] out_file;
78 reg [3:0] hex, tmp_char;
81 integer ifp, ofp, r, r2;
82 integer i, j, k, m, n;
88 integer off_addr, nn, aaaa, tt, cc, aah, aal, dd, sum ;
97 error_status = `FALSE;
114 if((in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT"))
118 ifp = $fopen(in_file, "r");
121 $display("ERROR: cannot read %0s.", in_file);
127 if((out_file[4*8 : 1] == ".hex") || (out_file[4*8 : 1] == ".HEX"))
128 out_file[3*8 : 1] = `EXT_STR;
131 $display("ERROR: Invalid input file name %0s. Expecting file with .hex extension and Intel-hex data format.", in_file);
135 ofp = $fopen(out_file, "w");
138 $display("ERROR : cannot write %0s.", out_file);
142 while((!done) && (!error_status))
151 error_status = `TRUE;
152 $display("WARNING: %0s, Intel-hex data file is empty.", in_file);
156 error_status = `TRUE;
157 $display("ERROR: %0s, line %0d, Missing the last record.", in_file, line_no);
160 else if (r == `COLON)
172 // get record length bytes
173 for (i = 0; i < 2; i = i+1)
177 if ((r >= "0") && (r <= "9"))
178 nn = (nn * 16) + (r - 'h30);
179 else if ((r >= "A") && (r <= "F"))
180 nn = (nn * 16) + 10 + (r - 'h41);
181 else if ((r >= "a") && (r <= "f"))
182 nn = (nn * 16) + 10 + (r - 'h61);
185 error_status = `TRUE;
186 $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
193 for (i = 0; i < 4; i = i+1)
197 if ((r >= "0") && (r <= "9"))
199 else if ((r >= "A") && (r <= "F"))
200 hex = 10 + (r - 'h41);
201 else if ((r >= "a") && (r <= "f"))
202 hex = 10 + (r - 'h61);
205 error_status = `TRUE;
206 $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
211 aaaa = (aaaa * 16) + hex;
214 aal = (aal * 16) + hex;
216 aah = (aah * 16) + hex;
219 // get record type bytes
220 for (i = 0; i < 2; i = i+1)
224 if ((r >= "0") && (r <= "9"))
225 tt = (tt * 16) + (r - 'h30);
226 else if ((r >= "A") && (r <= "F"))
227 tt = (tt * 16) + 10 + (r - 'h41);
228 else if ((r >= "a") && (r <= "f"))
229 tt = (tt * 16) + 10 + (r - 'h61);
232 error_status = `TRUE;
233 $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
239 if((tt == 2) && (nn != 2) )
241 error_status = `TRUE;
242 $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
247 // get the sum of all the bytes for record length, address and record types
248 sum = nn + aah + aal + tt ;
250 // check the record type
258 if ((width % `AWORD) != 0)
261 // k = no. of bytes per entry.
264 $fdisplay(ofp,"@%0h", (aaaa + off_addr));
265 for (j = 1; j <= k; j = j +1)
269 for(m = 1; m <= 2; m= m+1)
271 if((((k-j)*8) + ((3-m)*4) - width) < 4)
277 // get the data bytes
278 for(m = 1; m <= 2; m= m+1)
282 if ((r >= "0") && (r <= "9"))
284 else if ((r >= "A") && (r <= "F"))
285 hex = 10 + (r - 'h41);
286 else if ((r >= "a") && (r <= "f"))
287 hex = 10 + (r - 'h61);
290 error_status = `TRUE;
291 $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
296 if((((k-j)*8) + ((3-m)*4) - width) < 4)
297 $fwrite(ofp, "%h", hex);
298 dd = (dd * 16) + hex;
312 end // end of while (i < nn)
320 // address base record
325 // get the extended segment address record
326 for(i = 1; i <= (nn*2); i= i+1)
330 if ((r >= "0") && (r <= "9"))
332 else if ((r >= "A") && (r <= "F"))
333 hex = 10 + (r - 'h41);
334 else if ((r >= "a") && (r <= "f"))
335 hex = 10 + (r - 'h61);
338 error_status = `TRUE;
339 $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
344 off_addr = (off_addr * `H10) + hex;
345 dd = (dd * 16) + hex;
354 off_addr = off_addr * `H10;
358 error_status = `TRUE;
359 $display("ERROR: %0s, line %0d, Unknown record type.", in_file, line_no);
363 // get the checksum bytes
364 for (i = 0; i < 2; i = i+1)
368 if ((r >= "0") && (r <= "9"))
369 cc = (cc * 16) + (r - 'h30);
370 else if ((r >= "A") && (r <= "F"))
371 cc = 10 + (cc * 16) + (r - 'h41);
372 else if ((r >= "a") && (r <= "f"))
373 cc = 10 + (cc * 16) + (r - 'h61);
376 error_status = `TRUE;
377 $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
383 // Perform check sum.
384 if(((~sum+1)& `MASK15) != cc)
386 error_status = `TRUE;
387 $display("ERROR: %0s, line %0d, Invalid checksum.", in_file, line_no);
391 else if ((r == `NEWLINE) || (r == `CARRIAGE_RETURN))
393 line_no = line_no +1;
395 else if (r == `SPACE)
397 // continue to next character;
401 error_status = `TRUE;
402 $display("ERROR:%0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
412 endtask // convert_hex2ver
414 endmodule // ALTERA_MF_MEMORY_INITIALIZATION
417 //START_MODULE_NAME------------------------------------------------------------
419 // Module Name : ALTERA_DEVICE_FAMILIES
421 // Description : Common Altera device families comparison
427 //END_MODULE_NAME--------------------------------------------------------------
429 // BEGINNING OF MODULE
430 `timescale 1 ps / 1 ps
432 // MODULE DECLARATION
433 module ALTERA_DEVICE_FAMILIES;
435 function IS_FAMILY_ACEX1K;
436 input[8*20:1] device;
439 if ((device == "ACEX1K") || (device == "acex1k") || (device == "ACEX 1K") || (device == "acex 1k"))
444 IS_FAMILY_ACEX1K = is_acex1k;
446 endfunction //IS_FAMILY_ACEX1K
448 function IS_FAMILY_APEX20K;
449 input[8*20:1] device;
452 if ((device == "APEX20K") || (device == "apex20k") || (device == "APEX 20K") || (device == "apex 20k") || (device == "RAPHAEL") || (device == "raphael"))
457 IS_FAMILY_APEX20K = is_apex20k;
459 endfunction //IS_FAMILY_APEX20K
461 function IS_FAMILY_APEX20KC;
462 input[8*20:1] device;
465 if ((device == "APEX20KC") || (device == "apex20kc") || (device == "APEX 20KC") || (device == "apex 20kc"))
470 IS_FAMILY_APEX20KC = is_apex20kc;
472 endfunction //IS_FAMILY_APEX20KC
474 function IS_FAMILY_APEX20KE;
475 input[8*20:1] device;
478 if ((device == "APEX20KE") || (device == "apex20ke") || (device == "APEX 20KE") || (device == "apex 20ke"))
483 IS_FAMILY_APEX20KE = is_apex20ke;
485 endfunction //IS_FAMILY_APEX20KE
487 function IS_FAMILY_APEXII;
488 input[8*20:1] device;
491 if ((device == "APEX II") || (device == "apex ii") || (device == "APEXII") || (device == "apexii") || (device == "APEX 20KF") || (device == "apex 20kf") || (device == "APEX20KF") || (device == "apex20kf"))
496 IS_FAMILY_APEXII = is_apexii;
498 endfunction //IS_FAMILY_APEXII
500 function IS_FAMILY_EXCALIBUR_ARM;
501 input[8*20:1] device;
502 reg is_excalibur_arm;
504 if ((device == "EXCALIBUR_ARM") || (device == "excalibur_arm") || (device == "Excalibur ARM") || (device == "EXCALIBUR ARM") || (device == "excalibur arm") || (device == "ARM-BASED EXCALIBUR") || (device == "arm-based excalibur") || (device == "ARM_BASED_EXCALIBUR") || (device == "arm_based_excalibur"))
505 is_excalibur_arm = 1;
507 is_excalibur_arm = 0;
509 IS_FAMILY_EXCALIBUR_ARM = is_excalibur_arm;
511 endfunction //IS_FAMILY_EXCALIBUR_ARM
513 function IS_FAMILY_FLEX10KE;
514 input[8*20:1] device;
517 if ((device == "FLEX10KE") || (device == "flex10ke") || (device == "FLEX 10KE") || (device == "flex 10ke"))
522 IS_FAMILY_FLEX10KE = is_flex10ke;
524 endfunction //IS_FAMILY_FLEX10KE
526 function IS_FAMILY_MERCURY;
527 input[8*20:1] device;
530 if ((device == "Mercury") || (device == "MERCURY") || (device == "mercury") || (device == "DALI") || (device == "dali"))
535 IS_FAMILY_MERCURY = is_mercury;
537 endfunction //IS_FAMILY_MERCURY
539 function IS_FAMILY_STRATIX;
540 input[8*20:1] device;
543 if ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager"))
548 IS_FAMILY_STRATIX = is_stratix;
550 endfunction //IS_FAMILY_STRATIX
552 function IS_FAMILY_STRATIXGX;
553 input[8*20:1] device;
556 if ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora"))
561 IS_FAMILY_STRATIXGX = is_stratixgx;
563 endfunction //IS_FAMILY_STRATIXGX
565 function IS_FAMILY_CYCLONE;
566 input[8*20:1] device;
569 if ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado"))
574 IS_FAMILY_CYCLONE = is_cyclone;
576 endfunction //IS_FAMILY_CYCLONE
578 function IS_FAMILY_MAXII;
579 input[8*20:1] device;
582 if ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami"))
587 IS_FAMILY_MAXII = is_maxii;
589 endfunction //IS_FAMILY_MAXII
591 function IS_FAMILY_HARDCOPYSTRATIX;
592 input[8*20:1] device;
593 reg is_hardcopystratix;
595 if ((device == "HardCopy Stratix") || (device == "HARDCOPY STRATIX") || (device == "hardcopy stratix") || (device == "Stratix HC") || (device == "STRATIX HC") || (device == "stratix hc") || (device == "StratixHC") || (device == "STRATIXHC") || (device == "stratixhc") || (device == "HardcopyStratix") || (device == "HARDCOPYSTRATIX") || (device == "hardcopystratix"))
596 is_hardcopystratix = 1;
598 is_hardcopystratix = 0;
600 IS_FAMILY_HARDCOPYSTRATIX = is_hardcopystratix;
602 endfunction //IS_FAMILY_HARDCOPYSTRATIX
604 function IS_FAMILY_STRATIXII;
605 input[8*20:1] device;
608 if ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong"))
613 IS_FAMILY_STRATIXII = is_stratixii;
615 endfunction //IS_FAMILY_STRATIXII
617 function IS_FAMILY_STRATIXIIGX;
618 input[8*20:1] device;
621 if ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx"))
626 IS_FAMILY_STRATIXIIGX = is_stratixiigx;
628 endfunction //IS_FAMILY_STRATIXIIGX
630 function IS_FAMILY_CYCLONEII;
631 input[8*20:1] device;
634 if ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan"))
639 IS_FAMILY_CYCLONEII = is_cycloneii;
641 endfunction //IS_FAMILY_CYCLONEII
643 function IS_FAMILY_HARDCOPYII;
644 input[8*20:1] device;
647 if ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion"))
652 IS_FAMILY_HARDCOPYII = is_hardcopyii;
654 endfunction //IS_FAMILY_HARDCOPYII
656 function FEATURE_FAMILY_STRATIXGX;
657 input[8*20:1] device;
658 reg var_family_stratixgx;
660 if (IS_FAMILY_STRATIXGX(device) )
661 var_family_stratixgx = 1;
663 var_family_stratixgx = 0;
665 FEATURE_FAMILY_STRATIXGX = var_family_stratixgx;
667 endfunction //FEATURE_FAMILY_STRATIXGX
669 function FEATURE_FAMILY_CYCLONE;
670 input[8*20:1] device;
671 reg var_family_cyclone;
673 if (IS_FAMILY_CYCLONE(device) )
674 var_family_cyclone = 1;
676 var_family_cyclone = 0;
678 FEATURE_FAMILY_CYCLONE = var_family_cyclone;
680 endfunction //FEATURE_FAMILY_CYCLONE
682 function FEATURE_FAMILY_STRATIXII;
683 input[8*20:1] device;
684 reg var_family_stratixii;
686 if (IS_FAMILY_STRATIXII(device) || IS_FAMILY_HARDCOPYII(device) || IS_FAMILY_STRATIXIIGX(device) )
687 var_family_stratixii = 1;
689 var_family_stratixii = 0;
691 FEATURE_FAMILY_STRATIXII = var_family_stratixii;
693 endfunction //FEATURE_FAMILY_STRATIXII
695 function FEATURE_FAMILY_STRATIX_HC;
696 input[8*20:1] device;
697 reg var_family_stratix_hc;
699 if (IS_FAMILY_HARDCOPYSTRATIX(device) )
700 var_family_stratix_hc = 1;
702 var_family_stratix_hc = 0;
704 FEATURE_FAMILY_STRATIX_HC = var_family_stratix_hc;
706 endfunction //FEATURE_FAMILY_STRATIX_HC
708 function FEATURE_FAMILY_STRATIX;
709 input[8*20:1] device;
710 reg var_family_stratix;
712 if (IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIX_HC(device) || FEATURE_FAMILY_STRATIXGX(device) || FEATURE_FAMILY_CYCLONE(device) || FEATURE_FAMILY_STRATIXII(device) || FEATURE_FAMILY_MAXII(device) || FEATURE_FAMILY_CYCLONEII(device) )
713 var_family_stratix = 1;
715 var_family_stratix = 0;
717 FEATURE_FAMILY_STRATIX = var_family_stratix;
719 endfunction //FEATURE_FAMILY_STRATIX
721 function FEATURE_FAMILY_MAXII;
722 input[8*20:1] device;
723 reg var_family_maxii;
725 if (IS_FAMILY_MAXII(device) )
726 var_family_maxii = 1;
728 var_family_maxii = 0;
730 FEATURE_FAMILY_MAXII = var_family_maxii;
732 endfunction //FEATURE_FAMILY_MAXII
734 function FEATURE_FAMILY_CYCLONEII;
735 input[8*20:1] device;
736 reg var_family_cycloneii;
738 if (IS_FAMILY_CYCLONEII(device) )
739 var_family_cycloneii = 1;
741 var_family_cycloneii = 0;
743 FEATURE_FAMILY_CYCLONEII = var_family_cycloneii;
745 endfunction //FEATURE_FAMILY_CYCLONEII
747 function FEATURE_FAMILY_HAS_MEGARAM;
748 input[8*20:1] device;
749 reg var_family_has_megaram;
751 if (IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIX_HC(device) || IS_FAMILY_STRATIXGX(device) || FEATURE_FAMILY_STRATIXII(device) )
752 var_family_has_megaram = 1;
754 var_family_has_megaram = 0;
756 FEATURE_FAMILY_HAS_MEGARAM = var_family_has_megaram;
758 endfunction //FEATURE_FAMILY_HAS_MEGARAM
760 function FEATURE_FAMILY_HAS_M512;
761 input[8*20:1] device;
762 reg var_family_has_m512;
764 if (IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIX_HC(device) || IS_FAMILY_STRATIXGX(device) || IS_FAMILY_STRATIXII(device) || IS_FAMILY_STRATIXIIGX(device) )
765 var_family_has_m512 = 1;
767 var_family_has_m512 = 0;
769 FEATURE_FAMILY_HAS_M512 = var_family_has_m512;
771 endfunction //FEATURE_FAMILY_HAS_M512
773 function FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM;
774 input[8*20:1] device;
775 reg var_family_has_stratixii_style_ram;
777 if (FEATURE_FAMILY_STRATIXII(device) || FEATURE_FAMILY_CYCLONEII(device) )
778 var_family_has_stratixii_style_ram = 1;
780 var_family_has_stratixii_style_ram = 0;
782 FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM = var_family_has_stratixii_style_ram;
784 endfunction //FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM
786 function FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO;
787 input[8*20:1] device;
788 reg var_family_has_inverted_output_ddio;
790 if (FEATURE_FAMILY_CYCLONEII(device) )
791 var_family_has_inverted_output_ddio = 1;
793 var_family_has_inverted_output_ddio = 0;
795 FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO = var_family_has_inverted_output_ddio;
797 endfunction //FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO
799 function IS_VALID_FAMILY;
800 input[8*20:1] device;
803 if (((device == "ACEX1K") || (device == "acex1k") || (device == "ACEX 1K") || (device == "acex 1k"))
804 || ((device == "APEX20K") || (device == "apex20k") || (device == "APEX 20K") || (device == "apex 20k") || (device == "RAPHAEL") || (device == "raphael"))
805 || ((device == "APEX20KC") || (device == "apex20kc") || (device == "APEX 20KC") || (device == "apex 20kc"))
806 || ((device == "APEX20KE") || (device == "apex20ke") || (device == "APEX 20KE") || (device == "apex 20ke"))
807 || ((device == "APEX II") || (device == "apex ii") || (device == "APEXII") || (device == "apexii") || (device == "APEX 20KF") || (device == "apex 20kf") || (device == "APEX20KF") || (device == "apex20kf"))
808 || ((device == "EXCALIBUR_ARM") || (device == "excalibur_arm") || (device == "Excalibur ARM") || (device == "EXCALIBUR ARM") || (device == "excalibur arm") || (device == "ARM-BASED EXCALIBUR") || (device == "arm-based excalibur") || (device == "ARM_BASED_EXCALIBUR") || (device == "arm_based_excalibur"))
809 || ((device == "FLEX10KE") || (device == "flex10ke") || (device == "FLEX 10KE") || (device == "flex 10ke"))
810 || ((device == "FLEX10K") || (device == "flex10k") || (device == "FLEX 10K") || (device == "flex 10k"))
811 || ((device == "FLEX10KA") || (device == "flex10ka") || (device == "FLEX 10KA") || (device == "flex 10ka"))
812 || ((device == "FLEX6000") || (device == "flex6000") || (device == "FLEX 6000") || (device == "flex 6000") || (device == "FLEX6K") || (device == "flex6k"))
813 || ((device == "MAX7000B") || (device == "max7000b") || (device == "MAX 7000B") || (device == "max 7000b"))
814 || ((device == "MAX7000AE") || (device == "max7000ae") || (device == "MAX 7000AE") || (device == "max 7000ae"))
815 || ((device == "MAX3000A") || (device == "max3000a") || (device == "MAX 3000A") || (device == "max 3000a"))
816 || ((device == "MAX7000S") || (device == "max7000s") || (device == "MAX 7000S") || (device == "max 7000s"))
817 || ((device == "MAX7000A") || (device == "max7000a") || (device == "MAX 7000A") || (device == "max 7000a"))
818 || ((device == "Mercury") || (device == "MERCURY") || (device == "mercury") || (device == "DALI") || (device == "dali"))
819 || ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager"))
820 || ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora"))
821 || ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado"))
822 || ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami"))
823 || ((device == "HardCopy Stratix") || (device == "HARDCOPY STRATIX") || (device == "hardcopy stratix") || (device == "Stratix HC") || (device == "STRATIX HC") || (device == "stratix hc") || (device == "StratixHC") || (device == "STRATIXHC") || (device == "stratixhc") || (device == "HardcopyStratix") || (device == "HARDCOPYSTRATIX") || (device == "hardcopystratix"))
824 || ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong"))
825 || ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx"))
826 || ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan"))
827 || ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion")))
832 IS_VALID_FAMILY = is_valid;
834 endfunction // IS_VALID_FAMILY
837 endmodule // ALTERA_DEVICE_FAMILIES
839 ///////////////////////////////////////////////////////////////////////////////
841 // STRATIX_PLL and STRATIXII_PLL
843 ///////////////////////////////////////////////////////////////////////////////
847 module dffp ( Q, CLK, ENA, D, CLRN, PRN );
859 always @ (posedge CLK or negedge CLRN or negedge PRN )
860 if (PRN == 1'b0) Q = 1;
861 else if (CLRN == 1'b0) Q = 0;
862 else if ((CLK == 1) & (ENA == 1'b1)) Q = D;
866 ///////////////////////////////////////////////////////////////////////////////
868 // Module Name : stx_m_cntr
870 // Description : Simulation model for the M counter. This is the
871 // loop feedback counter for the Stratix PLL.
873 ///////////////////////////////////////////////////////////////////////////////
875 `timescale 1 ps / 1 ps
876 module stx_m_cntr (clk,
886 input [31:0] initial_value;
887 input [31:0] modulus;
888 input [31:0] time_delay;
893 // INTERNAL VARIABLES AND NETS
896 reg first_rising_edge;
903 first_rising_edge = 1;
907 always @(reset or clk)
913 first_rising_edge = 1;
916 if (clk == 1 && clk_last_value !== clk && first_rising_edge)
918 first_rising_edge = 0;
921 else if (first_rising_edge == 0)
928 tmp_cout = ~tmp_cout;
932 clk_last_value = clk;
934 cout_tmp <= #(time_delay) tmp_cout;
937 and (cout, cout_tmp, 1'b1);
939 endmodule // stx_m_cntr
941 ///////////////////////////////////////////////////////////////////////////////
943 // Module Name : stx_n_cntr
945 // Description : Simulation model for the N counter. This is the
946 // input clock divide counter for the Stratix PLL.
948 ///////////////////////////////////////////////////////////////////////////////
950 `timescale 1 ps / 1 ps
951 module stx_n_cntr (clk,
960 input [31:0] modulus;
961 input [31:0] time_delay;
966 // INTERNAL VARIABLES AND NETS
969 reg first_rising_edge;
971 reg clk_last_valid_value;
977 first_rising_edge = 1;
981 always @(reset or clk)
987 first_rising_edge = 1;
990 if (clk_last_value !== clk)
994 $display("Warning : Invalid transition to 'X' detected on Stratix PLL input clk. This edge will be ignored.");
995 $display("Time: %0t Instance: %m", $time);
997 else if ((clk === 1'b1) && first_rising_edge)
999 first_rising_edge = 0;
1002 else if ((first_rising_edge == 0) && (clk_last_valid_value !== clk))
1004 if (count < modulus)
1009 tmp_cout = ~tmp_cout;
1014 clk_last_value = clk;
1016 clk_last_valid_value = clk;
1018 cout_tmp <= #(time_delay) tmp_cout;
1021 and (cout, cout_tmp, 1'b1);
1023 endmodule // stx_n_cntr
1025 ///////////////////////////////////////////////////////////////////////////////
1027 // Module Name : stx_scale_cntr
1029 // Description : Simulation model for the output scale-down counters.
1030 // This is a common model for the L0, L1, G0, G1, G2, G3, E0,
1031 // E1, E2 and E3 output counters of the Stratix PLL.
1033 ///////////////////////////////////////////////////////////////////////////////
1035 `timescale 1 ps / 1 ps
1036 module stx_scale_cntr (clk,
1051 input [31:0] initial_value;
1053 input [31:0] time_delay;
1054 input [31:0] ph_tap;
1059 // INTERNAL VARIABLES AND NETS
1061 reg first_rising_edge;
1065 integer output_shift_count;
1067 reg [31:0] high_reg;
1069 reg high_cnt_xfer_done;
1074 first_rising_edge = 0;
1076 output_shift_count = 0;
1077 high_cnt_xfer_done = 0;
1080 always @(clk or reset)
1092 output_shift_count = 0;
1094 first_rising_edge = 0;
1096 else if (clk_last_value !== clk)
1100 else if (mode == "bypass")
1102 else if (first_rising_edge == 0)
1106 output_shift_count = output_shift_count + 1;
1107 if (output_shift_count == initial_value)
1110 first_rising_edge = 1;
1114 else if (output_shift_count < initial_value)
1117 output_shift_count = output_shift_count + 1;
1122 if (mode == "even" && (count == (high_reg*2) + 1))
1125 if (high_cnt_xfer_done === 1'b1)
1128 high_cnt_xfer_done = 0;
1131 else if (mode == "odd" && (count == (high_reg*2)))
1134 if (high_cnt_xfer_done === 1'b1)
1137 high_cnt_xfer_done = 0;
1140 else if (count == (high_reg + low_reg)*2 + 1)
1143 count = 1; // reset count
1144 if (high_reg != high)
1147 high_cnt_xfer_done = 1;
1152 clk_last_value = clk;
1153 cout_tmp <= #(time_delay) tmp_cout;
1156 and (cout, cout_tmp, 1'b1);
1158 endmodule // stx_scale_cntr
1160 ///////////////////////////////////////////////////////////////////////////////
1162 // Module Name : MF_pll_reg
1164 // Description : Simulation model for a simple DFF.
1165 // This is required for the generation of the bit slip-signals.
1166 // No timing, powers upto 0.
1168 ///////////////////////////////////////////////////////////////////////////////
1170 `timescale 1ps / 1ps
1171 module MF_pll_reg (q,
1188 // INTERNAL VARIABLES
1191 // DEFAULT VALUES THRO' PULLUPs
1192 tri1 prn, clrn, ena;
1196 always @ (posedge clk or negedge clrn or negedge prn )
1200 else if (clrn == 1'b0)
1202 else if ((clk == 1) & (ena == 1'b1))
1206 endmodule // MF_pll_reg
1208 //////////////////////////////////////////////////////////////////////////////
1210 // Module Name : MF_stratix_pll
1212 // Description : The behavioral model for Stratix PLL.
1214 // Limitations : Applies to the Stratix and Stratix GX device families
1215 // No support for spread spectrum feature in the model
1217 // Outputs : Up to 10 output clocks, each defined by its own set of
1218 // parameters. Locked output (active high) indicates when the
1219 // PLL locks. clkbad, clkloss and activeclock are used for
1220 // clock switchover to indicate which input clock has gone
1221 // bad, when the clock switchover initiates and which input
1222 // clock is being used as the reference, respectively.
1223 // scandataout is the data output of the serial scan chain.
1225 //////////////////////////////////////////////////////////////////////////////
1227 `timescale 1 ps/1 ps
1228 `define WORD_LENGTH 18
1230 module MF_stratix_pll (inclk,
1248 // lvds mode specific ports
1253 parameter operation_mode = "normal";
1254 parameter qualify_conf_done = "off";
1255 parameter compensate_clock = "clk0";
1256 parameter pll_type = "auto";
1257 parameter scan_chain = "long";
1259 parameter clk0_multiply_by = 1;
1260 parameter clk0_divide_by = 1;
1261 parameter clk0_phase_shift = 0;
1262 parameter clk0_time_delay = 0;
1263 parameter clk0_duty_cycle = 50;
1265 parameter clk1_multiply_by = 1;
1266 parameter clk1_divide_by = 1;
1267 parameter clk1_phase_shift = 0;
1268 parameter clk1_time_delay = 0;
1269 parameter clk1_duty_cycle = 50;
1271 parameter clk2_multiply_by = 1;
1272 parameter clk2_divide_by = 1;
1273 parameter clk2_phase_shift = 0;
1274 parameter clk2_time_delay = 0;
1275 parameter clk2_duty_cycle = 50;
1277 parameter clk3_multiply_by = 1;
1278 parameter clk3_divide_by = 1;
1279 parameter clk3_phase_shift = 0;
1280 parameter clk3_time_delay = 0;
1281 parameter clk3_duty_cycle = 50;
1283 parameter clk4_multiply_by = 1;
1284 parameter clk4_divide_by = 1;
1285 parameter clk4_phase_shift = 0;
1286 parameter clk4_time_delay = 0;
1287 parameter clk4_duty_cycle = 50;
1289 parameter clk5_multiply_by = 1;
1290 parameter clk5_divide_by = 1;
1291 parameter clk5_phase_shift = 0;
1292 parameter clk5_time_delay = 0;
1293 parameter clk5_duty_cycle = 50;
1295 parameter extclk0_multiply_by = 1;
1296 parameter extclk0_divide_by = 1;
1297 parameter extclk0_phase_shift = 0;
1298 parameter extclk0_time_delay = 0;
1299 parameter extclk0_duty_cycle = 50;
1301 parameter extclk1_multiply_by = 1;
1302 parameter extclk1_divide_by = 1;
1303 parameter extclk1_phase_shift = 0;
1304 parameter extclk1_time_delay = 0;
1305 parameter extclk1_duty_cycle = 50;
1307 parameter extclk2_multiply_by = 1;
1308 parameter extclk2_divide_by = 1;
1309 parameter extclk2_phase_shift = 0;
1310 parameter extclk2_time_delay = 0;
1311 parameter extclk2_duty_cycle = 50;
1313 parameter extclk3_multiply_by = 1;
1314 parameter extclk3_divide_by = 1;
1315 parameter extclk3_phase_shift = 0;
1316 parameter extclk3_time_delay = 0;
1317 parameter extclk3_duty_cycle = 50;
1319 parameter primary_clock = "inclk0";
1320 parameter inclk0_input_frequency = 10000;
1321 parameter inclk1_input_frequency = 10000;
1322 parameter gate_lock_signal = "no";
1323 parameter gate_lock_counter = 1;
1324 parameter valid_lock_multiplier = 5;
1325 parameter invalid_lock_multiplier = 5;
1327 parameter switch_over_on_lossclk = "off";
1328 parameter switch_over_on_gated_lock = "off";
1329 parameter switch_over_counter = 1;
1330 parameter enable_switch_over_counter = "off";
1331 parameter feedback_source = "e0";
1332 parameter bandwidth = 0;
1333 parameter bandwidth_type = "auto";
1334 parameter down_spread = "0.0";
1335 parameter spread_frequency = 0;
1336 parameter common_rx_tx = "off";
1337 parameter rx_outclock_resource = "auto";
1338 parameter use_vco_bypass = "false";
1339 parameter use_dc_coupling = "false";
1341 parameter pfd_min = 0;
1342 parameter pfd_max = 0;
1343 parameter vco_min = 0;
1344 parameter vco_max = 0;
1345 parameter vco_center = 0;
1347 // ADVANCED USE PARAMETERS
1348 parameter m_initial = 1;
1355 parameter l0_high = 1;
1356 parameter l0_low = 1;
1357 parameter l0_initial = 1;
1358 parameter l0_mode = "bypass";
1359 parameter l0_ph = 0;
1360 parameter l0_time_delay = 0;
1362 parameter l1_high = 1;
1363 parameter l1_low = 1;
1364 parameter l1_initial = 1;
1365 parameter l1_mode = "bypass";
1366 parameter l1_ph = 0;
1367 parameter l1_time_delay = 0;
1369 parameter g0_high = 1;
1370 parameter g0_low = 1;
1371 parameter g0_initial = 1;
1372 parameter g0_mode = "bypass";
1373 parameter g0_ph = 0;
1374 parameter g0_time_delay = 0;
1376 parameter g1_high = 1;
1377 parameter g1_low = 1;
1378 parameter g1_initial = 1;
1379 parameter g1_mode = "bypass";
1380 parameter g1_ph = 0;
1381 parameter g1_time_delay = 0;
1383 parameter g2_high = 1;
1384 parameter g2_low = 1;
1385 parameter g2_initial = 1;
1386 parameter g2_mode = "bypass";
1387 parameter g2_ph = 0;
1388 parameter g2_time_delay = 0;
1390 parameter g3_high = 1;
1391 parameter g3_low = 1;
1392 parameter g3_initial = 1;
1393 parameter g3_mode = "bypass";
1394 parameter g3_ph = 0;
1395 parameter g3_time_delay = 0;
1397 parameter e0_high = 1;
1398 parameter e0_low = 1;
1399 parameter e0_initial = 1;
1400 parameter e0_mode = "bypass";
1401 parameter e0_ph = 0;
1402 parameter e0_time_delay = 0;
1404 parameter e1_high = 1;
1405 parameter e1_low = 1;
1406 parameter e1_initial = 1;
1407 parameter e1_mode = "bypass";
1408 parameter e1_ph = 0;
1409 parameter e1_time_delay = 0;
1411 parameter e2_high = 1;
1412 parameter e2_low = 1;
1413 parameter e2_initial = 1;
1414 parameter e2_mode = "bypass";
1415 parameter e2_ph = 0;
1416 parameter e2_time_delay = 0;
1418 parameter e3_high = 1;
1419 parameter e3_low = 1;
1420 parameter e3_initial = 1;
1421 parameter e3_mode = "bypass";
1422 parameter e3_ph = 0;
1423 parameter e3_time_delay = 0;
1426 parameter m_time_delay = 0;
1427 parameter n_time_delay = 0;
1429 parameter extclk0_counter = "e0";
1430 parameter extclk1_counter = "e1";
1431 parameter extclk2_counter = "e2";
1432 parameter extclk3_counter = "e3";
1434 parameter clk0_counter = "g0";
1435 parameter clk1_counter = "g1";
1436 parameter clk2_counter = "g2";
1437 parameter clk3_counter = "g3";
1438 parameter clk4_counter = "l0";
1439 parameter clk5_counter = "l1";
1441 // LVDS mode parameters
1442 parameter enable0_counter = "l0";
1443 parameter enable1_counter = "l0";
1445 parameter charge_pump_current = 0;
1446 parameter loop_filter_r = "1.0";
1447 parameter loop_filter_c = 1;
1449 parameter pll_compensation_delay = 0;
1450 parameter simulation_type = "timing";
1452 //parameter for stratix lvds
1453 parameter clk0_phase_shift_num = 0;
1454 parameter clk1_phase_shift_num = 0;
1455 parameter clk2_phase_shift_num = 0;
1457 parameter skip_vco = "off";
1459 parameter clk0_use_even_counter_mode = "off";
1460 parameter clk1_use_even_counter_mode = "off";
1461 parameter clk2_use_even_counter_mode = "off";
1462 parameter clk3_use_even_counter_mode = "off";
1463 parameter clk4_use_even_counter_mode = "off";
1464 parameter clk5_use_even_counter_mode = "off";
1465 parameter extclk0_use_even_counter_mode = "off";
1466 parameter extclk1_use_even_counter_mode = "off";
1467 parameter extclk2_use_even_counter_mode = "off";
1468 parameter extclk3_use_even_counter_mode = "off";
1470 parameter clk0_use_even_counter_value = "off";
1471 parameter clk1_use_even_counter_value = "off";
1472 parameter clk2_use_even_counter_value = "off";
1473 parameter clk3_use_even_counter_value = "off";
1474 parameter clk4_use_even_counter_value = "off";
1475 parameter clk5_use_even_counter_value = "off";
1476 parameter extclk0_use_even_counter_value = "off";
1477 parameter extclk1_use_even_counter_value = "off";
1478 parameter extclk2_use_even_counter_value = "off";
1479 parameter extclk3_use_even_counter_value = "off";
1489 input [3:0] extclkena;
1493 // lvds specific input ports
1498 output [3:0] extclk;
1499 output [1:0] clkbad;
1504 // lvds specific output ports
1521 wire extclkena0_ipd;
1522 wire extclkena1_ipd;
1523 wire extclkena2_ipd;
1524 wire extclkena3_ipd;
1528 wire comparator_ipd;
1531 buf (inclk0_ipd, inclk[0]);
1532 buf (inclk1_ipd, inclk[1]);
1534 buf (fbin_ipd, fbin);
1535 buf (areset_ipd, areset);
1536 buf (pfdena_ipd, pfdena);
1537 buf (clkena0_ipd, clkena[0]);
1538 buf (clkena1_ipd, clkena[1]);
1539 buf (clkena2_ipd, clkena[2]);
1540 buf (clkena3_ipd, clkena[3]);
1541 buf (clkena4_ipd, clkena[4]);
1542 buf (clkena5_ipd, clkena[5]);
1543 buf (extclkena0_ipd, extclkena[0]);
1544 buf (extclkena1_ipd, extclkena[1]);
1545 buf (extclkena2_ipd, extclkena[2]);
1546 buf (extclkena3_ipd, extclkena[3]);
1547 buf (scanclk_ipd, scanclk);
1548 buf (scanaclr_ipd, scanaclr);
1549 buf (scandata_ipd, scandata);
1550 buf (comparator_ipd, comparator);
1551 buf (clkswitch_ipd, clkswitch);
1553 // INTERNAL VARIABLES AND NETS
1554 integer scan_chain_length;
1560 integer egpp_offset;
1562 integer delay_chain;
1565 integer initial_delay;
1568 integer phase_shift[0:7];
1569 integer last_phase_shift[0:7];
1571 integer m_times_vco_period;
1572 integer new_m_times_vco_period;
1573 integer refclk_period;
1574 integer fbclk_period;
1575 integer primary_clock_frequency;
1581 integer tmp_vco_per;
1584 integer temp_offset;
1585 integer cycles_to_lock;
1586 integer cycles_to_unlock;
1589 integer loop_xplier;
1590 integer loop_initial;
1592 integer loop_time_delay;
1593 integer cycle_to_adjust;
1594 integer total_pull_back;
1595 integer pull_back_M;
1596 integer pull_back_ext_cntr;
1599 time first_fbclk_time;
1601 time scanaclr_rising_time;
1602 time scanaclr_falling_time;
1604 reg got_first_refclk;
1605 reg got_second_refclk;
1606 reg got_first_fbclk;
1607 reg refclk_last_value;
1608 reg fbclk_last_value;
1609 reg inclk_last_value;
1611 reg pll_about_to_lock;
1613 reg l0_got_first_rising_edge;
1614 reg l1_got_first_rising_edge;
1615 reg vco_l0_last_value;
1616 reg vco_l1_last_value;
1617 reg areset_ipd_last_value;
1618 reg ena_ipd_last_value;
1619 reg pfdena_ipd_last_value;
1620 reg inclk_out_of_range;
1621 reg schedule_vco_last_value;
1626 reg [31:0] m_initial_val;
1628 reg [31:0] m_val_tmp;
1631 reg [31:0] n_val_tmp;
1633 reg [31:0] m_time_delay_val;
1634 reg [31:0] n_time_delay_val;
1636 reg [8*6:1] m_mode_val;
1637 reg [8*6:1] m2_mode_val;
1638 reg [8*6:1] n_mode_val;
1639 reg [8*6:1] n2_mode_val;
1640 reg [31:0] l0_high_val;
1641 reg [31:0] l0_low_val;
1642 reg [31:0] l0_initial_val;
1643 reg [31:0] l0_time_delay_val;
1644 reg [8*6:1] l0_mode_val;
1645 reg [31:0] l1_high_val;
1646 reg [31:0] l1_low_val;
1647 reg [31:0] l1_initial_val;
1648 reg [31:0] l1_time_delay_val;
1649 reg [8*6:1] l1_mode_val;
1651 reg [31:0] g0_high_val;
1652 reg [31:0] g0_low_val;
1653 reg [31:0] g0_initial_val;
1654 reg [31:0] g0_time_delay_val;
1655 reg [8*6:1] g0_mode_val;
1657 reg [31:0] g1_high_val;
1658 reg [31:0] g1_low_val;
1659 reg [31:0] g1_initial_val;
1660 reg [31:0] g1_time_delay_val;
1661 reg [8*6:1] g1_mode_val;
1663 reg [31:0] g2_high_val;
1664 reg [31:0] g2_low_val;
1665 reg [31:0] g2_initial_val;
1666 reg [31:0] g2_time_delay_val;
1667 reg [8*6:1] g2_mode_val;
1669 reg [31:0] g3_high_val;
1670 reg [31:0] g3_low_val;
1671 reg [31:0] g3_initial_val;
1672 reg [31:0] g3_time_delay_val;
1673 reg [8*6:1] g3_mode_val;
1675 reg [31:0] e0_high_val;
1676 reg [31:0] e0_low_val;
1677 reg [31:0] e0_initial_val;
1678 reg [31:0] e0_time_delay_val;
1679 reg [8*6:1] e0_mode_val;
1681 reg [31:0] e1_high_val;
1682 reg [31:0] e1_low_val;
1683 reg [31:0] e1_initial_val;
1684 reg [31:0] e1_time_delay_val;
1685 reg [8*6:1] e1_mode_val;
1687 reg [31:0] e2_high_val;
1688 reg [31:0] e2_low_val;
1689 reg [31:0] e2_initial_val;
1690 reg [31:0] e2_time_delay_val;
1691 reg [8*6:1] e2_mode_val;
1693 reg [31:0] e3_high_val;
1694 reg [31:0] e3_low_val;
1695 reg [31:0] e3_initial_val;
1696 reg [31:0] e3_time_delay_val;
1697 reg [8*6:1] e3_mode_val;
1699 reg scanclk_last_value;
1700 reg scanaclr_last_value;
1702 reg transfer_enable;
1703 reg [288:0] scan_data;
1705 reg schedule_offset;
1779 reg vco_period_was_phase_adjusted;
1780 reg phase_adjust_was_scheduled;
1782 // for external feedback mode
1784 reg [31:0] ext_fbk_cntr_high;
1785 reg [31:0] ext_fbk_cntr_low;
1786 reg [31:0] ext_fbk_cntr_modulus;
1787 reg [31:0] ext_fbk_cntr_delay;
1788 reg [8*2:1] ext_fbk_cntr;
1789 reg [8*6:1] ext_fbk_cntr_mode;
1790 integer ext_fbk_cntr_ph;
1791 integer ext_fbk_cntr_initial;
1797 wire [31:0] cntr_e0_initial;
1798 wire [31:0] cntr_e1_initial;
1799 wire [31:0] cntr_e2_initial;
1800 wire [31:0] cntr_e3_initial;
1801 wire [31:0] cntr_e0_delay;
1802 wire [31:0] cntr_e1_delay;
1803 wire [31:0] cntr_e2_delay;
1804 wire [31:0] cntr_e3_delay;
1805 reg [31:0] ext_fbk_delay;
1807 // variables for clk_switch
1810 reg inclk0_last_value;
1811 reg inclk1_last_value;
1812 reg other_clock_value;
1813 reg other_clock_last_value;
1814 reg primary_clk_is_bad;
1815 reg current_clk_is_bad;
1816 reg external_switch;
1817 reg [8*6:1] current_clock;
1820 reg got_curr_clk_falling_edge_after_clkswitch;
1821 reg active_clk_was_switched;
1825 integer switch_over_count;
1827 reg scandataout_tmp;
1829 reg pll_in_quiet_period;
1830 time start_quiet_time;
1831 reg quiet_period_violation;
1833 reg scanclr_violation;
1834 reg scanclr_clk_violation;
1835 reg got_first_scanclk_after_scanclr_inactive_edge;
1840 // internal parameters
1841 parameter EGPP_SCAN_CHAIN = 289;
1842 parameter GPP_SCAN_CHAIN = 193;
1843 parameter TRST = 5000;
1844 parameter TRSTCLK = 5000;
1846 // internal variables for scaling of multiply_by and divide_by values
1847 integer i_clk0_mult_by;
1848 integer i_clk0_div_by;
1849 integer i_clk1_mult_by;
1850 integer i_clk1_div_by;
1851 integer i_clk2_mult_by;
1852 integer i_clk2_div_by;
1853 integer i_clk3_mult_by;
1854 integer i_clk3_div_by;
1855 integer i_clk4_mult_by;
1856 integer i_clk4_div_by;
1857 integer i_clk5_mult_by;
1858 integer i_clk5_div_by;
1859 integer i_extclk0_mult_by;
1860 integer i_extclk0_div_by;
1861 integer i_extclk1_mult_by;
1862 integer i_extclk1_div_by;
1863 integer i_extclk2_mult_by;
1864 integer i_extclk2_div_by;
1865 integer i_extclk3_mult_by;
1866 integer i_extclk3_div_by;
1867 integer max_d_value;
1868 integer new_multiplier;
1870 // internal variables for storing the phase shift number.(used in lvds mode only)
1871 integer i_clk0_phase_shift;
1872 integer i_clk1_phase_shift;
1873 integer i_clk2_phase_shift;
1875 // user to advanced internal signals
1877 integer i_m_initial;
1903 integer i_l0_initial;
1904 integer i_l1_initial;
1905 integer i_g0_initial;
1906 integer i_g1_initial;
1907 integer i_g2_initial;
1908 integer i_g3_initial;
1909 integer i_e0_initial;
1910 integer i_e1_initial;
1911 integer i_e2_initial;
1912 integer i_e3_initial;
1913 reg [8*6:1] i_l0_mode;
1914 reg [8*6:1] i_l1_mode;
1915 reg [8*6:1] i_g0_mode;
1916 reg [8*6:1] i_g1_mode;
1917 reg [8*6:1] i_g2_mode;
1918 reg [8*6:1] i_g3_mode;
1919 reg [8*6:1] i_e0_mode;
1920 reg [8*6:1] i_e1_mode;
1921 reg [8*6:1] i_e2_mode;
1922 reg [8*6:1] i_e3_mode;
1925 integer i_vco_center;
1940 integer i_l0_time_delay;
1941 integer i_l1_time_delay;
1942 integer i_g0_time_delay;
1943 integer i_g1_time_delay;
1944 integer i_g2_time_delay;
1945 integer i_g3_time_delay;
1946 integer i_e0_time_delay;
1947 integer i_e1_time_delay;
1948 integer i_e2_time_delay;
1949 integer i_e3_time_delay;
1950 integer i_m_time_delay;
1951 integer i_n_time_delay;
1952 integer i_extclk3_counter;
1953 integer i_extclk2_counter;
1954 integer i_extclk1_counter;
1955 integer i_extclk0_counter;
1956 integer i_clk5_counter;
1957 integer i_clk4_counter;
1958 integer i_clk3_counter;
1959 integer i_clk2_counter;
1960 integer i_clk1_counter;
1961 integer i_clk0_counter;
1962 integer i_charge_pump_current;
1963 integer i_loop_filter_r;
1964 integer max_neg_abs;
1965 integer output_count;
1966 integer new_divisor;
1968 // uppercase to lowercase parameter values
1969 reg [8*`WORD_LENGTH:1] l_operation_mode;
1970 reg [8*`WORD_LENGTH:1] l_pll_type;
1971 reg [8*`WORD_LENGTH:1] l_qualify_conf_done;
1972 reg [8*`WORD_LENGTH:1] l_compensate_clock;
1973 reg [8*`WORD_LENGTH:1] l_scan_chain;
1974 reg [8*`WORD_LENGTH:1] l_primary_clock;
1975 reg [8*`WORD_LENGTH:1] l_gate_lock_signal;
1976 reg [8*`WORD_LENGTH:1] l_switch_over_on_lossclk;
1977 reg [8*`WORD_LENGTH:1] l_switch_over_on_gated_lock;
1978 reg [8*`WORD_LENGTH:1] l_enable_switch_over_counter;
1979 reg [8*`WORD_LENGTH:1] l_feedback_source;
1980 reg [8*`WORD_LENGTH:1] l_bandwidth_type;
1981 reg [8*`WORD_LENGTH:1] l_simulation_type;
1982 reg [8*`WORD_LENGTH:1] l_enable0_counter;
1983 reg [8*`WORD_LENGTH:1] l_enable1_counter;
1990 // finds the closest integer fraction of a given pair of numerator and denominator.
1991 task find_simple_integer_fraction;
1995 output fraction_num;
1996 output fraction_div;
1997 parameter max_iter = 20;
2000 integer denominator;
2002 integer fraction_num;
2003 integer fraction_div;
2005 integer quotient_array[max_iter-1:0];
2006 integer int_loop_iter;
2010 integer old_m_value;
2022 i_max_iter = max_iter;
2024 while (loop_iter < i_max_iter)
2026 int_quot = num / den;
2027 quotient_array[loop_iter] = int_quot;
2028 num = num - (den*int_quot);
2029 loop_iter=loop_iter+1;
2031 if ((num == 0) || (max_denom != -1) || (loop_iter == i_max_iter))
2033 // calculate the numerator and denominator if there is a restriction on the
2034 // max denom value or if the loop is ending
2037 // get the rounded value at this stage for the remaining fraction
2040 m_value = (2*num/den);
2042 // calculate the fraction numerator and denominator at this stage
2043 for (int_loop_iter = loop_iter-1; int_loop_iter >= 0; int_loop_iter=int_loop_iter-1)
2047 m_value = quotient_array[int_loop_iter];
2052 old_m_value = m_value;
2053 m_value = quotient_array[int_loop_iter]*m_value + d_value;
2054 d_value = old_m_value;
2057 // if the denominator is less than the maximum denom_value or if there is no restriction save it
2058 if ((d_value <= max_denom) || (max_denom == -1))
2060 fraction_num = m_value;
2061 fraction_div = d_value;
2063 // end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
2064 if (((d_value > max_denom) && (max_denom != -1)) || (num == 0))
2066 i_max_iter = loop_iter;
2069 // swap the numerator and denominator for the next round
2075 endtask // find_simple_integer_fraction
2077 // get the absolute value
2078 function integer abs;
2088 // find twice the period of the slowest clock
2089 function integer slowest_clk;
2090 input L0, L1, G0, G1, G2, G3, E0, E1, E2, E3, scan_chain, refclk, m_mod;
2091 integer L0, L1, G0, G1, G2, G3, E0, E1, E2, E3;
2092 reg [8*5:1] scan_chain;
2095 integer max_modulus;
2101 if (G0 > max_modulus)
2103 if (G1 > max_modulus)
2105 if (G2 > max_modulus)
2107 if (G3 > max_modulus)
2109 if (scan_chain == "long")
2111 if (E0 > max_modulus)
2113 if (E1 > max_modulus)
2115 if (E2 > max_modulus)
2117 if (E3 > max_modulus)
2121 slowest_clk = ((refclk/m_mod) * max_modulus *2);
2125 // count the number of digits in the given integer
2126 function integer count_digit;
2129 integer count, result;
2135 result = (result / 10);
2139 count_digit = count;
2143 // reduce the given huge number(X) to Y significant digits
2144 function integer scale_num;
2148 integer fac_ten, lc;
2151 count = count_digit(X);
2153 for (lc = 0; lc < (count-Y); lc = lc + 1)
2154 fac_ten = fac_ten * 10;
2156 scale_num = (X / fac_ten);
2160 // find the greatest common denominator of X and Y
2161 function integer gcd;
2166 if (X < Y) // find which is smaller.
2182 R = S % L; // divide bigger number by smaller.
2183 // remainder becomes smaller number.
2185 if (R == 0) // if evenly divisible then L is gcd else it is 1.
2193 // find the least common multiple of A1 to A10
2194 function integer lcm;
2195 input A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
2196 integer A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
2197 integer M1, M2, M3, M4, M5 , M6, M7, M8, M9, R;
2199 M1 = (A1 * A2)/gcd(A1, A2);
2200 M2 = (M1 * A3)/gcd(M1, A3);
2201 M3 = (M2 * A4)/gcd(M2, A4);
2202 M4 = (M3 * A5)/gcd(M3, A5);
2203 M5 = (M4 * A6)/gcd(M4, A6);
2204 M6 = (M5 * A7)/gcd(M5, A7);
2205 M7 = (M6 * A8)/gcd(M6, A8);
2206 M8 = (M7 * A9)/gcd(M7, A9);
2207 M9 = (M8 * A10)/gcd(M8, A10);
2210 else if ((M9 <= 10) && (M9 >= 3))
2213 R = scale_num(M9,3);
2220 // find the factor of division of the output clock frequency
2221 // compared to the VCO
2222 function integer output_counter_value;
2223 input clk_divide, clk_mult, M, N;
2224 integer clk_divide, clk_mult, M, N;
2227 R = (clk_divide * M)/(clk_mult * N);
2228 output_counter_value = R;
2232 // find the mode of each of the PLL counters - bypass, even or odd
2233 function [8*6:1] counter_mode;
2235 input output_counter_value;
2237 integer output_counter_value;
2238 integer half_cycle_high;
2241 half_cycle_high = (2*duty_cycle*output_counter_value)/100;
2242 if (output_counter_value == 1)
2244 else if ((half_cycle_high % 2) == 0)
2252 // find the number of VCO clock cycles to hold the output clock high
2253 function integer counter_high;
2254 input output_counter_value, duty_cycle;
2255 integer output_counter_value, duty_cycle;
2256 integer half_cycle_high;
2257 integer tmp_counter_high;
2260 half_cycle_high = (2*duty_cycle*output_counter_value)/100;
2261 mode = ((half_cycle_high % 2) == 0);
2262 tmp_counter_high = half_cycle_high/2;
2263 counter_high = tmp_counter_high + !mode;
2267 // find the number of VCO clock cycles to hold the output clock low
2268 function integer counter_low;
2269 input output_counter_value, duty_cycle;
2270 integer output_counter_value, duty_cycle, counter_h;
2271 integer half_cycle_high;
2273 integer tmp_counter_high;
2275 half_cycle_high = (2*duty_cycle*output_counter_value)/100;
2276 mode = ((half_cycle_high % 2) == 0);
2277 tmp_counter_high = half_cycle_high/2;
2278 counter_h = tmp_counter_high + !mode;
2279 counter_low = output_counter_value - counter_h;
2283 // find the smallest time delay amongst t1 to t10
2284 function integer mintimedelay;
2285 input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
2286 integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
2287 integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
2332 // find the numerically largest negative number, and return its absolute value
2333 function integer maxnegabs;
2334 input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
2335 integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
2336 integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
2338 if (t1 < t2) m1 = t1; else m1 = t2;
2339 if (m1 < t3) m2 = m1; else m2 = t3;
2340 if (m2 < t4) m3 = m2; else m3 = t4;
2341 if (m3 < t5) m4 = m3; else m4 = t5;
2342 if (m4 < t6) m5 = m4; else m5 = t6;
2343 if (m5 < t7) m6 = m5; else m6 = t7;
2344 if (m6 < t8) m7 = m6; else m7 = t8;
2345 if (m7 < t9) m8 = m7; else m8 = t9;
2346 if (m8 < t10) m9 = m8; else m9 = t10;
2347 maxnegabs = (m9 < 0) ? 0 - m9 : 0;
2351 // adjust the given tap_phase by adding the largest negative number (ph_base)
2352 function integer ph_adjust;
2353 input tap_phase, ph_base;
2354 integer tap_phase, ph_base;
2356 ph_adjust = tap_phase + ph_base;
2360 // find the actual time delay for each PLL counter
2361 function integer counter_time_delay;
2362 input clk_time_delay, m_time_delay, n_time_delay;
2363 integer clk_time_delay, m_time_delay, n_time_delay;
2365 counter_time_delay = clk_time_delay + m_time_delay - n_time_delay;
2369 // find the number of VCO clock cycles to wait initially before the first
2370 // rising edge of the output clock
2371 function integer counter_initial;
2372 input tap_phase, m, n;
2373 integer tap_phase, m, n, phase;
2375 if (tap_phase < 0) tap_phase = 0 - tap_phase;
2376 // adding 0.5 for rounding correction (required in order to round
2377 // to the nearest integer instead of truncating)
2378 phase = ((tap_phase * m) / (360 * n)) + 0.5;
2379 counter_initial = phase;
2383 // find which VCO phase tap to align the rising edge of the output clock to
2384 function integer counter_ph;
2390 // adding 0.5 for rounding correction
2391 phase = (tap_phase * m / n) + 0.5;
2392 counter_ph = (phase % 360)/45;
2396 // convert the given string to length 6 by padding with spaces
2397 function [8*6:1] translate_string;
2399 reg [8*6:1] new_mode;
2401 if (mode == "bypass")
2402 new_mode = "bypass";
2403 else if (mode == "even")
2405 else if (mode == "odd")
2408 translate_string = new_mode;
2412 // convert string to integer with sign
2413 function integer str2int;
2419 integer m, magnitude;
2426 for (m=1; m<=16; m=m+1)
2428 tmp = reg_s[128:121];
2429 digit = tmp & 8'b00001111;
2431 // Accumulate ascii digits 0-9 only.
2432 if ((tmp>=48) && (tmp<=57))
2433 magnitude = (magnitude * 10) + digit;
2435 sign = -1; // Found a '-' character, i.e. number is negative.
2437 str2int = sign*magnitude;
2441 // this is for stratix lvds only
2442 // convert phase delay to integer
2443 function integer get_int_phase_shift;
2445 input i_phase_shift;
2446 integer i_phase_shift;
2449 if (i_phase_shift != 0)
2451 get_int_phase_shift = i_phase_shift;
2455 get_int_phase_shift = str2int(s);
2460 // calculate the given phase shift (in ps) in terms of degrees
2461 function integer get_phase_degree;
2463 integer phase_shift, result;
2465 result = (phase_shift * 360) / inclk0_input_frequency;
2466 // this is to round up the calculation result
2468 result = result + 1;
2469 else if ( result < 0 )
2470 result = result - 1;
2474 // assign the rounded up result
2475 get_phase_degree = result;
2479 // convert uppercase parameter values to lowercase
2480 // assumes that the maximum character length of a parameter is 18
2481 function [8*`WORD_LENGTH:1] alpha_tolower;
2482 input [8*`WORD_LENGTH:1] given_string;
2484 reg [8*`WORD_LENGTH:1] return_string;
2485 reg [8*`WORD_LENGTH:1] reg_string;
2487 reg [8:1] conv_char;
2490 return_string = " "; // initialise strings to spaces
2492 reg_string = given_string;
2493 for (byte_count = `WORD_LENGTH; byte_count >= 1; byte_count = byte_count - 1)
2495 tmp = reg_string[8*`WORD_LENGTH:(8*(`WORD_LENGTH-1)+1)];
2496 reg_string = reg_string << 8;
2497 if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90
2499 conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set
2500 return_string = {return_string, conv_char};
2503 return_string = {return_string, tmp};
2506 alpha_tolower = return_string;
2512 // convert string parameter values from uppercase to lowercase,
2513 // as expected in this model
2514 l_operation_mode = alpha_tolower(operation_mode);
2515 l_pll_type = alpha_tolower(pll_type);
2516 l_qualify_conf_done = alpha_tolower(qualify_conf_done);
2517 l_compensate_clock = alpha_tolower(compensate_clock);
2518 l_scan_chain = alpha_tolower(scan_chain);
2519 l_primary_clock = alpha_tolower(primary_clock);
2520 l_gate_lock_signal = alpha_tolower(gate_lock_signal);
2521 l_switch_over_on_lossclk = alpha_tolower(switch_over_on_lossclk);
2522 l_switch_over_on_gated_lock = alpha_tolower(switch_over_on_gated_lock);
2523 l_enable_switch_over_counter = alpha_tolower(enable_switch_over_counter);
2524 l_feedback_source = alpha_tolower(feedback_source);
2525 l_bandwidth_type = alpha_tolower(bandwidth_type);
2526 l_simulation_type = alpha_tolower(simulation_type);
2527 l_enable0_counter = alpha_tolower(enable0_counter);
2528 l_enable1_counter = alpha_tolower(enable1_counter);
2532 // set the limit of the divide_by value that can be returned by
2533 // the following function.
2536 // scale down the multiply_by and divide_by values provided by the design
2537 // before attempting to use them in the calculations below
2538 find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
2539 max_d_value, i_clk0_mult_by, i_clk0_div_by);
2540 find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
2541 max_d_value, i_clk1_mult_by, i_clk1_div_by);
2542 find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
2543 max_d_value, i_clk2_mult_by, i_clk2_div_by);
2544 find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
2545 max_d_value, i_clk3_mult_by, i_clk3_div_by);
2546 find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
2547 max_d_value, i_clk4_mult_by, i_clk4_div_by);
2548 find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
2549 max_d_value, i_clk5_mult_by, i_clk5_div_by);
2550 find_simple_integer_fraction(extclk0_multiply_by, extclk0_divide_by,
2551 max_d_value, i_extclk0_mult_by, i_extclk0_div_by);
2552 find_simple_integer_fraction(extclk1_multiply_by, extclk1_divide_by,
2553 max_d_value, i_extclk1_mult_by, i_extclk1_div_by);
2554 find_simple_integer_fraction(extclk2_multiply_by, extclk2_divide_by,
2555 max_d_value, i_extclk2_mult_by, i_extclk2_div_by);
2556 find_simple_integer_fraction(extclk3_multiply_by, extclk3_divide_by,
2557 max_d_value, i_extclk3_mult_by, i_extclk3_div_by);
2559 // convert user parameters to advanced
2561 if (l_pll_type == "lvds")
2562 i_m = clk0_multiply_by;
2564 i_m = lcm (i_clk0_mult_by, i_clk1_mult_by,
2565 i_clk2_mult_by, i_clk3_mult_by,
2566 i_clk4_mult_by, i_clk5_mult_by,
2568 i_extclk1_mult_by, i_extclk2_mult_by,
2569 i_extclk3_mult_by, inclk0_input_frequency);
2570 i_m_time_delay = maxnegabs (str2int(clk0_time_delay),
2571 str2int(clk1_time_delay),
2572 str2int(clk2_time_delay),
2573 str2int(clk3_time_delay),
2574 str2int(clk4_time_delay),
2575 str2int(clk5_time_delay),
2576 str2int(extclk0_time_delay),
2577 str2int(extclk1_time_delay),
2578 str2int(extclk2_time_delay),
2579 str2int(extclk3_time_delay));
2580 i_n_time_delay = mintimedelay(str2int(clk0_time_delay),
2581 str2int(clk1_time_delay),
2582 str2int(clk2_time_delay),
2583 str2int(clk3_time_delay),
2584 str2int(clk4_time_delay),
2585 str2int(clk5_time_delay),
2586 str2int(extclk0_time_delay),
2587 str2int(extclk1_time_delay),
2588 str2int(extclk2_time_delay),
2589 str2int(extclk3_time_delay));
2590 if (l_pll_type == "lvds")
2591 i_g0_high = counter_high(output_counter_value(i_clk2_div_by,
2592 i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
2594 i_g0_high = counter_high(output_counter_value(i_clk0_div_by,
2595 i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
2598 i_g1_high = counter_high(output_counter_value(i_clk1_div_by,
2599 i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
2600 i_g2_high = counter_high(output_counter_value(i_clk2_div_by,
2601 i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
2602 i_g3_high = counter_high(output_counter_value(i_clk3_div_by,
2603 i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
2604 if (l_pll_type == "lvds")
2606 i_l0_high = i_g0_high;
2607 i_l1_high = i_g0_high;
2611 i_l0_high = counter_high(output_counter_value(i_clk4_div_by,
2612 i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
2613 i_l1_high = counter_high(output_counter_value(i_clk5_div_by,
2614 i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
2616 i_e0_high = counter_high(output_counter_value(i_extclk0_div_by,
2617 i_extclk0_mult_by, i_m, i_n), extclk0_duty_cycle);
2618 i_e1_high = counter_high(output_counter_value(i_extclk1_div_by,
2619 i_extclk1_mult_by, i_m, i_n), extclk1_duty_cycle);
2620 i_e2_high = counter_high(output_counter_value(i_extclk2_div_by,
2621 i_extclk2_mult_by, i_m, i_n), extclk2_duty_cycle);
2622 i_e3_high = counter_high(output_counter_value(i_extclk3_div_by,
2623 i_extclk3_mult_by, i_m, i_n), extclk3_duty_cycle);
2624 if (l_pll_type == "lvds")
2625 i_g0_low = counter_low(output_counter_value(i_clk2_div_by,
2626 i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
2628 i_g0_low = counter_low(output_counter_value(i_clk0_div_by,
2629 i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
2630 i_g1_low = counter_low(output_counter_value(i_clk1_div_by,
2631 i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
2632 i_g2_low = counter_low(output_counter_value(i_clk2_div_by,
2633 i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
2634 i_g3_low = counter_low(output_counter_value(i_clk3_div_by,
2635 i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
2636 if (l_pll_type == "lvds")
2638 i_l0_low = i_g0_low;
2639 i_l1_low = i_g0_low;
2643 i_l0_low = counter_low(output_counter_value(i_clk4_div_by,
2644 i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
2645 i_l1_low = counter_low(output_counter_value(i_clk5_div_by,
2646 i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
2648 i_e0_low = counter_low(output_counter_value(i_extclk0_div_by,
2649 i_extclk0_mult_by, i_m, i_n), extclk0_duty_cycle);
2650 i_e1_low = counter_low(output_counter_value(i_extclk1_div_by,
2651 i_extclk1_mult_by, i_m, i_n), extclk1_duty_cycle);
2652 i_e2_low = counter_low(output_counter_value(i_extclk2_div_by,
2653 i_extclk2_mult_by, i_m, i_n), extclk2_duty_cycle);
2654 i_e3_low = counter_low(output_counter_value(i_extclk3_div_by,
2655 i_extclk3_mult_by, i_m, i_n), extclk3_duty_cycle);
2657 if (l_pll_type == "flvds")
2659 // Need to readjust phase shift values when the clock multiply value has been readjusted.
2660 new_multiplier = clk0_multiply_by / i_clk0_mult_by;
2661 i_clk0_phase_shift = (clk0_phase_shift_num * new_multiplier);
2662 i_clk1_phase_shift = (clk1_phase_shift_num * new_multiplier);
2663 i_clk2_phase_shift = (clk2_phase_shift_num * new_multiplier);
2667 i_clk0_phase_shift = get_int_phase_shift(clk0_phase_shift, clk0_phase_shift_num);
2668 i_clk1_phase_shift = get_int_phase_shift(clk1_phase_shift, clk1_phase_shift_num);
2669 i_clk2_phase_shift = get_int_phase_shift(clk2_phase_shift, clk2_phase_shift_num);
2672 max_neg_abs = maxnegabs(i_clk0_phase_shift,
2675 str2int(clk3_phase_shift),
2676 str2int(clk4_phase_shift),
2677 str2int(clk5_phase_shift),
2678 str2int(extclk0_phase_shift),
2679 str2int(extclk1_phase_shift),
2680 str2int(extclk2_phase_shift),
2681 str2int(extclk3_phase_shift));
2682 if (l_pll_type == "lvds")
2683 i_g0_initial = counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
2685 i_g0_initial = counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
2687 i_g1_initial = counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
2688 i_g2_initial = counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
2689 i_g3_initial = counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs)), i_m, i_n);
2690 if (l_pll_type == "lvds")
2692 i_l0_initial = i_g0_initial;
2693 i_l1_initial = i_g0_initial;
2697 i_l0_initial = counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs)), i_m, i_n);
2698 i_l1_initial = counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs)), i_m, i_n);
2700 i_e0_initial = counter_initial(get_phase_degree(ph_adjust(str2int(extclk0_phase_shift), max_neg_abs)), i_m, i_n);
2701 i_e1_initial = counter_initial(get_phase_degree(ph_adjust(str2int(extclk1_phase_shift), max_neg_abs)), i_m, i_n);
2702 i_e2_initial = counter_initial(get_phase_degree(ph_adjust(str2int(extclk2_phase_shift), max_neg_abs)), i_m, i_n);
2703 i_e3_initial = counter_initial(get_phase_degree(ph_adjust(str2int(extclk3_phase_shift), max_neg_abs)), i_m, i_n);
2704 if (l_pll_type == "lvds")
2705 i_g0_mode = counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
2707 i_g0_mode = counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
2708 i_g1_mode = counter_mode(clk1_duty_cycle,output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
2709 i_g2_mode = counter_mode(clk2_duty_cycle,output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
2710 i_g3_mode = counter_mode(clk3_duty_cycle,output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
2711 if (l_pll_type == "lvds")
2713 i_l0_mode = "bypass";
2714 i_l1_mode = "bypass";
2718 i_l0_mode = counter_mode(clk4_duty_cycle,output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
2719 i_l1_mode = counter_mode(clk5_duty_cycle,output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
2721 i_e0_mode = counter_mode(extclk0_duty_cycle,output_counter_value(i_extclk0_div_by, i_extclk0_mult_by, i_m, i_n));
2722 i_e1_mode = counter_mode(extclk1_duty_cycle,output_counter_value(i_extclk1_div_by, i_extclk1_mult_by, i_m, i_n));
2723 i_e2_mode = counter_mode(extclk2_duty_cycle,output_counter_value(i_extclk2_div_by, i_extclk2_mult_by, i_m, i_n));
2724 i_e3_mode = counter_mode(extclk3_duty_cycle,output_counter_value(i_extclk3_div_by, i_extclk3_mult_by, i_m, i_n));
2725 i_m_ph = counter_ph(get_phase_degree(max_neg_abs), i_m, i_n);
2726 i_m_initial = counter_initial(get_phase_degree(max_neg_abs), i_m, i_n);
2727 if (l_pll_type == "lvds")
2728 i_g0_ph = counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
2730 i_g0_ph = counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
2732 i_g1_ph = counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
2733 i_g2_ph = counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
2734 i_g3_ph = counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs)), i_m, i_n);
2735 if (l_pll_type == "lvds")
2742 i_l0_ph = counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs)), i_m, i_n);
2743 i_l1_ph = counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs)), i_m, i_n);
2745 i_e0_ph = counter_ph(get_phase_degree(ph_adjust(str2int(extclk0_phase_shift),max_neg_abs)), i_m, i_n);
2746 i_e1_ph = counter_ph(get_phase_degree(ph_adjust(str2int(extclk1_phase_shift),max_neg_abs)), i_m, i_n);
2747 i_e2_ph = counter_ph(get_phase_degree(ph_adjust(str2int(extclk2_phase_shift),max_neg_abs)), i_m, i_n);
2748 i_e3_ph = counter_ph(get_phase_degree(ph_adjust(str2int(extclk3_phase_shift),max_neg_abs)), i_m, i_n);
2750 if (l_pll_type == "lvds")
2751 i_g0_time_delay = counter_time_delay ( str2int(clk2_time_delay),
2755 i_g0_time_delay = counter_time_delay ( str2int(clk0_time_delay),
2758 i_g1_time_delay = counter_time_delay ( str2int(clk1_time_delay),
2761 i_g2_time_delay = counter_time_delay ( str2int(clk2_time_delay),
2764 i_g3_time_delay = counter_time_delay ( str2int(clk3_time_delay),
2767 if (l_pll_type == "lvds")
2769 i_l0_time_delay = i_g0_time_delay;
2770 i_l1_time_delay = i_g0_time_delay;
2774 i_l0_time_delay = counter_time_delay ( str2int(clk4_time_delay),
2777 i_l1_time_delay = counter_time_delay ( str2int(clk5_time_delay),
2781 i_e0_time_delay = counter_time_delay ( str2int( extclk0_time_delay),
2784 i_e1_time_delay = counter_time_delay ( str2int( extclk1_time_delay),
2787 i_e2_time_delay = counter_time_delay ( str2int( extclk2_time_delay),
2790 i_e3_time_delay = counter_time_delay ( str2int( extclk3_time_delay),
2793 i_extclk3_counter = "e3" ;
2794 i_extclk2_counter = "e2" ;
2795 i_extclk1_counter = "e1" ;
2796 i_extclk0_counter = "e0" ;
2797 i_clk5_counter = "l1" ;
2798 i_clk4_counter = "l0" ;
2799 i_clk3_counter = "g3" ;
2800 i_clk2_counter = "g2" ;
2801 i_clk1_counter = "g1" ;
2803 if (l_pll_type == "lvds")
2805 l_enable0_counter = "l0";
2806 l_enable1_counter = "l1";
2807 i_clk0_counter = "l0" ;
2810 i_clk0_counter = "g0" ;
2812 // in external feedback mode, need to adjust M value to take
2813 // into consideration the external feedback counter value
2814 if (l_operation_mode == "external_feedback")
2816 // if there is a negative phase shift, m_initial can only be 1
2817 if (max_neg_abs > 0)
2820 if (l_feedback_source == "extclk0")
2822 if (i_e0_mode == "bypass")
2825 output_count = i_e0_high + i_e0_low;
2827 else if (l_feedback_source == "extclk1")
2829 if (i_e1_mode == "bypass")
2832 output_count = i_e1_high + i_e1_low;
2834 else if (l_feedback_source == "extclk2")
2836 if (i_e2_mode == "bypass")
2839 output_count = i_e2_high + i_e2_low;
2841 else if (l_feedback_source == "extclk3")
2843 if (i_e3_mode == "bypass")
2846 output_count = i_e3_high + i_e3_low;
2848 else // default to e0
2850 if (i_e0_mode == "bypass")
2853 output_count = i_e0_high + i_e0_low;
2856 if (i_m > output_count)
2857 i_m = i_m / output_count;
2860 new_divisor = gcd(i_m, output_count);
2861 i_m = i_m / new_divisor;
2862 i_n = output_count / new_divisor;
2872 i_l0_high = l0_high;
2873 i_l1_high = l1_high;
2874 i_g0_high = g0_high;
2875 i_g1_high = g1_high;
2876 i_g2_high = g2_high;
2877 i_g3_high = g3_high;
2878 i_e0_high = e0_high;
2879 i_e1_high = e1_high;
2880 i_e2_high = e2_high;
2881 i_e3_high = e3_high;
2892 i_l0_initial = l0_initial;
2893 i_l1_initial = l1_initial;
2894 i_g0_initial = g0_initial;
2895 i_g1_initial = g1_initial;
2896 i_g2_initial = g2_initial;
2897 i_g3_initial = g3_initial;
2898 i_e0_initial = e0_initial;
2899 i_e1_initial = e1_initial;
2900 i_e2_initial = e2_initial;
2901 i_e3_initial = e3_initial;
2902 i_l0_mode = alpha_tolower(l0_mode);
2903 i_l1_mode = alpha_tolower(l1_mode);
2904 i_g0_mode = alpha_tolower(g0_mode);
2905 i_g1_mode = alpha_tolower(g1_mode);
2906 i_g2_mode = alpha_tolower(g2_mode);
2907 i_g3_mode = alpha_tolower(g3_mode);
2908 i_e0_mode = alpha_tolower(e0_mode);
2909 i_e1_mode = alpha_tolower(e1_mode);
2910 i_e2_mode = alpha_tolower(e2_mode);
2911 i_e3_mode = alpha_tolower(e3_mode);
2922 i_m_ph = m_ph; // default
2923 i_m_initial = m_initial;
2924 i_l0_time_delay = l0_time_delay;
2925 i_l1_time_delay = l1_time_delay;
2926 i_g0_time_delay = g0_time_delay;
2927 i_g1_time_delay = g1_time_delay;
2928 i_g2_time_delay = g2_time_delay;
2929 i_g3_time_delay = g3_time_delay;
2930 i_e0_time_delay = e0_time_delay;
2931 i_e1_time_delay = e1_time_delay;
2932 i_e2_time_delay = e2_time_delay;
2933 i_e3_time_delay = e3_time_delay;
2934 i_m_time_delay = m_time_delay;
2935 i_n_time_delay = n_time_delay;
2936 i_extclk3_counter = alpha_tolower(extclk3_counter);
2937 i_extclk2_counter = alpha_tolower(extclk2_counter);
2938 i_extclk1_counter = alpha_tolower(extclk1_counter);
2939 i_extclk0_counter = alpha_tolower(extclk0_counter);
2940 i_clk5_counter = alpha_tolower(clk5_counter);
2941 i_clk4_counter = alpha_tolower(clk4_counter);
2942 i_clk3_counter = alpha_tolower(clk3_counter);
2943 i_clk2_counter = alpha_tolower(clk2_counter);
2944 i_clk1_counter = alpha_tolower(clk1_counter);
2945 i_clk0_counter = alpha_tolower(clk0_counter);
2947 end // user to advanced conversion
2949 // set the scan_chain length
2950 if (l_scan_chain == "long")
2951 scan_chain_length = EGPP_SCAN_CHAIN;
2952 else if (l_scan_chain == "short")
2953 scan_chain_length = GPP_SCAN_CHAIN;
2955 if (l_primary_clock == "inclk0")
2957 refclk_period = inclk0_input_frequency * i_n;
2958 primary_clock_frequency = inclk0_input_frequency;
2960 else if (l_primary_clock == "inclk1")
2962 refclk_period = inclk1_input_frequency * i_n;
2963 primary_clock_frequency = inclk1_input_frequency;
2966 m_times_vco_period = refclk_period;
2967 new_m_times_vco_period = refclk_period;
2973 schedule_offset = 1;
2974 vco_out[7:0] = 8'b0;
2975 fbclk_last_value = 0;
2978 got_first_refclk = 0;
2979 got_first_fbclk = 0;
2981 first_fbclk_time = 0;
2986 l0_got_first_rising_edge = 0;
2987 l1_got_first_rising_edge = 0;
2988 vco_l0_last_value = 0;
2997 for (i = 0; i <= 7; i = i + 1)
3000 last_phase_shift[i] = 0;
3004 cycle_to_adjust = 0;
3008 total_pull_back = 0;
3010 pull_back_ext_cntr = 0;
3011 vco_period_was_phase_adjusted = 0;
3012 phase_adjust_was_scheduled = 0;
3013 ena_ipd_last_value = 0;
3014 inclk_out_of_range = 0;
3015 scandataout_tmp = 0;
3016 schedule_vco_last_value = 0;
3018 // set initial values for counter parameters
3019 m_initial_val = i_m_initial;
3021 m_time_delay_val = i_m_time_delay;
3023 n_time_delay_val = i_n_time_delay;
3030 m_mode_val = "bypass";
3032 m2_mode_val = "bypass";
3034 n_mode_val = "bypass";
3036 n2_mode_val = "bypass";
3038 if (skip_vco == "on")
3042 m_time_delay_val = 0;
3046 l0_high_val = i_l0_high;
3047 l0_low_val = i_l0_low;
3048 l0_initial_val = i_l0_initial;
3049 l0_mode_val = i_l0_mode;
3050 l0_time_delay_val = i_l0_time_delay;
3052 l1_high_val = i_l1_high;
3053 l1_low_val = i_l1_low;
3054 l1_initial_val = i_l1_initial;
3055 l1_mode_val = i_l1_mode;
3056 l1_time_delay_val = i_l1_time_delay;
3058 g0_high_val = i_g0_high;
3059 g0_low_val = i_g0_low;
3060 g0_initial_val = i_g0_initial;
3061 g0_mode_val = i_g0_mode;
3062 g0_time_delay_val = i_g0_time_delay;
3064 g1_high_val = i_g1_high;
3065 g1_low_val = i_g1_low;
3066 g1_initial_val = i_g1_initial;
3067 g1_mode_val = i_g1_mode;
3068 g1_time_delay_val = i_g1_time_delay;
3070 g2_high_val = i_g2_high;
3071 g2_low_val = i_g2_low;
3072 g2_initial_val = i_g2_initial;
3073 g2_mode_val = i_g2_mode;
3074 g2_time_delay_val = i_g2_time_delay;
3076 g3_high_val = i_g3_high;
3077 g3_low_val = i_g3_low;
3078 g3_initial_val = i_g3_initial;
3079 g3_mode_val = i_g3_mode;
3080 g3_time_delay_val = i_g3_time_delay;
3082 e0_high_val = i_e0_high;
3083 e0_low_val = i_e0_low;
3084 e0_initial_val = i_e0_initial;
3085 e0_mode_val = i_e0_mode;
3086 e0_time_delay_val = i_e0_time_delay;
3088 e1_high_val = i_e1_high;
3089 e1_low_val = i_e1_low;
3090 e1_initial_val = i_e1_initial;
3091 e1_mode_val = i_e1_mode;
3092 e1_time_delay_val = i_e1_time_delay;
3094 e2_high_val = i_e2_high;
3095 e2_low_val = i_e2_low;
3096 e2_initial_val = i_e2_initial;
3097 e2_mode_val = i_e2_mode;
3098 e2_time_delay_val = i_e2_time_delay;
3100 e3_high_val = i_e3_high;
3101 e3_low_val = i_e3_low;
3102 e3_initial_val = i_e3_initial;
3103 e3_mode_val = i_e3_mode;
3104 e3_time_delay_val = i_e3_time_delay;
3108 inclk_last_value = 0;
3110 ext_fbk_cntr_ph = 0;
3111 ext_fbk_cntr_initial = 1;
3113 // initialize clkswitch variables
3117 inclk0_last_value = 0;
3118 inclk1_last_value = 0;
3119 other_clock_value = 0;
3120 other_clock_last_value = 0;
3121 primary_clk_is_bad = 0;
3122 current_clk_is_bad = 0;
3123 external_switch = 0;
3124 current_clock = l_primary_clock;
3125 if (l_primary_clock == "inclk0")
3130 got_curr_clk_falling_edge_after_clkswitch = 0;
3133 switch_over_count = 0;
3134 active_clk_was_switched = 0;
3136 // initialize quiet_time
3137 quiet_time = slowest_clk ( l0_high_val+l0_low_val,
3138 l1_high_val+l1_low_val,
3139 g0_high_val+g0_low_val,
3140 g1_high_val+g1_low_val,
3141 g2_high_val+g2_low_val,
3142 g3_high_val+g3_low_val,
3143 e0_high_val+e0_low_val,
3144 e1_high_val+e1_low_val,
3145 e2_high_val+e2_low_val,
3146 e3_high_val+e3_low_val,
3148 refclk_period, m_val);
3149 pll_in_quiet_period = 0;
3150 start_quiet_time = 0;
3151 quiet_period_violation = 0;
3153 scanclr_violation = 0;
3154 scanclr_clk_violation = 0;
3155 got_first_scanclk_after_scanclr_inactive_edge = 0;
3157 scanaclr_rising_time = 0;
3158 scanaclr_falling_time = 0;
3160 // VCO feedback loop settings for external feedback mode
3161 // first find which ext counter is used for feedback
3163 if (l_operation_mode == "external_feedback")
3165 if (l_feedback_source == "extclk0")
3167 if (i_extclk0_counter == "e0")
3168 ext_fbk_cntr = "e0";
3169 else if (i_extclk0_counter == "e1")
3170 ext_fbk_cntr = "e1";
3171 else if (i_extclk0_counter == "e2")
3172 ext_fbk_cntr = "e2";
3173 else if (i_extclk0_counter == "e3")
3174 ext_fbk_cntr = "e3";
3175 else ext_fbk_cntr = "e0";
3177 else if (l_feedback_source == "extclk1")
3179 if (i_extclk1_counter == "e0")
3180 ext_fbk_cntr = "e0";
3181 else if (i_extclk1_counter == "e1")
3182 ext_fbk_cntr = "e1";
3183 else if (i_extclk1_counter == "e2")
3184 ext_fbk_cntr = "e2";
3185 else if (i_extclk1_counter == "e3")
3186 ext_fbk_cntr = "e3";
3187 else ext_fbk_cntr = "e0";
3189 else if (l_feedback_source == "extclk2")
3191 if (i_extclk2_counter == "e0")
3192 ext_fbk_cntr = "e0";
3193 else if (i_extclk2_counter == "e1")
3194 ext_fbk_cntr = "e1";
3195 else if (i_extclk2_counter == "e2")
3196 ext_fbk_cntr = "e2";
3197 else if (i_extclk2_counter == "e3")
3198 ext_fbk_cntr = "e3";
3199 else ext_fbk_cntr = "e0";
3201 else if (l_feedback_source == "extclk3")
3203 if (i_extclk3_counter == "e0")
3204 ext_fbk_cntr = "e0";
3205 else if (i_extclk3_counter == "e1")
3206 ext_fbk_cntr = "e1";
3207 else if (i_extclk3_counter == "e2")
3208 ext_fbk_cntr = "e2";
3209 else if (i_extclk3_counter == "e3")
3210 ext_fbk_cntr = "e3";
3211 else ext_fbk_cntr = "e0";
3214 // now save this counter's parameters
3215 if (ext_fbk_cntr == "e0")
3217 ext_fbk_cntr_high = e0_high_val;
3218 ext_fbk_cntr_low = e0_low_val;
3219 ext_fbk_cntr_ph = i_e0_ph;
3220 ext_fbk_cntr_initial = i_e0_initial;
3221 ext_fbk_cntr_delay = e0_time_delay_val;
3222 ext_fbk_cntr_mode = e0_mode_val;
3224 else if (ext_fbk_cntr == "e1")
3226 ext_fbk_cntr_high = e1_high_val;
3227 ext_fbk_cntr_low = e1_low_val;
3228 ext_fbk_cntr_ph = i_e1_ph;
3229 ext_fbk_cntr_initial = i_e1_initial;
3230 ext_fbk_cntr_delay = e1_time_delay_val;
3231 ext_fbk_cntr_mode = e1_mode_val;
3233 else if (ext_fbk_cntr == "e2")
3235 ext_fbk_cntr_high = e2_high_val;
3236 ext_fbk_cntr_low = e2_low_val;
3237 ext_fbk_cntr_ph = i_e2_ph;
3238 ext_fbk_cntr_initial = i_e2_initial;
3239 ext_fbk_cntr_delay = e2_time_delay_val;
3240 ext_fbk_cntr_mode = e2_mode_val;
3242 else if (ext_fbk_cntr == "e3")
3244 ext_fbk_cntr_high = e3_high_val;
3245 ext_fbk_cntr_low = e3_low_val;
3246 ext_fbk_cntr_ph = i_e3_ph;
3247 ext_fbk_cntr_initial = i_e3_initial;
3248 ext_fbk_cntr_delay = e3_time_delay_val;
3249 ext_fbk_cntr_mode = e3_mode_val;
3252 if (ext_fbk_cntr_mode == "bypass")
3253 ext_fbk_cntr_modulus = 1;
3255 ext_fbk_cntr_modulus = ext_fbk_cntr_high + ext_fbk_cntr_low;
3261 cycles_to_unlock = 0;
3262 if (l_pll_type == "fast")
3267 pll_about_to_lock = 0;
3274 assign inclk_m = l_operation_mode == "external_feedback" ? (l_feedback_source == "extclk0" ? extclk0_tmp :
3275 l_feedback_source == "extclk1" ? extclk1_tmp :
3276 l_feedback_source == "extclk2" ? extclk2_tmp :
3277 l_feedback_source == "extclk3" ? extclk3_tmp : 'b0) :
3280 stx_m_cntr m1 (.clk(inclk_m),
3281 .reset(areset_ipd || (!ena_ipd) || stop_vco),
3283 .initial_value(m_initial_val),
3285 .time_delay(m_delay));
3287 always @(clkswitch_ipd)
3289 if (clkswitch_ipd == 1'b1)
3290 external_switch = 1;
3291 clkloss_tmp <= clkswitch_ipd;
3294 always @(inclk0_ipd or inclk1_ipd)
3296 // save the inclk event value
3297 if (inclk0_ipd !== inclk0_last_value)
3299 if (current_clock !== "inclk0")
3300 other_clock_value = inclk0_ipd;
3302 if (inclk1_ipd !== inclk1_last_value)
3304 if (current_clock !== "inclk1")
3305 other_clock_value = inclk1_ipd;
3308 // check if either input clk is bad
3309 if (inclk0_ipd === 1'b1 && inclk0_ipd !== inclk0_last_value)
3311 clk0_count = clk0_count + 1;
3313 if (current_clock == "inclk0")
3314 current_clk_is_bad = 0;
3318 // no event on other clk for 2 cycles
3320 if (current_clock == "inclk1")
3321 current_clk_is_bad = 1;
3324 if (inclk1_ipd === 1'b1 && inclk1_ipd !== inclk1_last_value)
3326 clk1_count = clk1_count + 1;
3328 if (current_clock == "inclk1")
3329 current_clk_is_bad = 0;
3333 // no event on other clk for 2 cycles
3335 if (current_clock == "inclk0")
3336 current_clk_is_bad = 1;
3340 // check if the bad clk is the primary clock
3341 if (((l_primary_clock == "inclk0") && (clk0_is_bad == 1'b1)) || ((l_primary_clock == "inclk1") && (clk1_is_bad == 1'b1)))
3342 primary_clk_is_bad = 1;
3344 primary_clk_is_bad = 0;
3347 if ((inclk0_ipd !== inclk0_last_value) && (current_clock == "inclk0"))
3349 if (external_switch == 1'b1)
3351 if (!got_curr_clk_falling_edge_after_clkswitch)
3353 if (inclk0_ipd === 1'b0)
3354 got_curr_clk_falling_edge_after_clkswitch = 1;
3355 inclk_n = inclk0_ipd;
3358 else inclk_n = inclk0_ipd;
3360 if ((inclk1_ipd !== inclk1_last_value) && (current_clock == "inclk1"))
3362 if (external_switch == 1'b1)
3364 if (!got_curr_clk_falling_edge_after_clkswitch)
3366 if (inclk1_ipd === 1'b0)
3367 got_curr_clk_falling_edge_after_clkswitch = 1;
3368 inclk_n = inclk1_ipd;
3371 else inclk_n = inclk1_ipd;
3373 if ((other_clock_value == 1'b1) && (other_clock_value != other_clock_last_value) && (l_switch_over_on_lossclk == "on") && (l_enable_switch_over_counter == "on") && primary_clk_is_bad)
3374 switch_over_count = switch_over_count + 1;
3375 if ((other_clock_value == 1'b0) && (other_clock_value != other_clock_last_value))
3377 if ((external_switch && (got_curr_clk_falling_edge_after_clkswitch || current_clk_is_bad)) || (l_switch_over_on_lossclk == "on" && primary_clk_is_bad && ((l_enable_switch_over_counter == "off" || switch_over_count == switch_over_counter))))
3379 got_curr_clk_falling_edge_after_clkswitch = 0;
3380 if (current_clock == "inclk0")
3382 current_clock = "inclk1";
3386 current_clock = "inclk0";
3388 active_clock = ~active_clock;
3389 active_clk_was_switched = 1;
3390 switch_over_count = 0;
3391 external_switch = 0;
3392 current_clk_is_bad = 0;
3396 if (l_switch_over_on_lossclk == "on" && (clkswitch_ipd != 1'b1))
3398 if (primary_clk_is_bad)
3404 inclk0_last_value = inclk0_ipd;
3405 inclk1_last_value = inclk1_ipd;
3406 other_clock_last_value = other_clock_value;
3410 and (clkbad[0], clk0_is_bad, 1'b1);
3411 and (clkbad[1], clk1_is_bad, 1'b1);
3412 and (activeclock, active_clock, 1'b1);
3413 and (clkloss, clkloss_tmp, 1'b1);
3415 stx_n_cntr n1 ( .clk(inclk_n),
3419 .time_delay(n_time_delay_val));
3421 stx_scale_cntr l0 ( .clk(vco_out[i_l0_ph]),
3422 .reset(areset_ipd || (!ena_ipd) || stop_vco),
3426 .initial_value(l0_initial_val),
3428 .time_delay(l0_time_delay_val),
3431 stx_scale_cntr l1 ( .clk(vco_out[i_l1_ph]),
3432 .reset(areset_ipd || (!ena_ipd) || stop_vco),
3436 .initial_value(l1_initial_val),
3438 .time_delay(l1_time_delay_val),
3441 stx_scale_cntr g0 ( .clk(vco_out[i_g0_ph]),
3442 .reset(areset_ipd || (!ena_ipd) || stop_vco),
3446 .initial_value(g0_initial_val),
3448 .time_delay(g0_time_delay_val),
3451 MF_pll_reg lvds_dffa ( .d(comparator_ipd),
3458 MF_pll_reg lvds_dffb ( .d(dffa_out),
3462 .clk(lvds_dffb_clk),
3465 assign lvds_dffb_clk = (l_enable0_counter == "l0") ? l0_clk : (l_enable0_counter == "l1") ? l1_clk : 1'b0;
3467 MF_pll_reg lvds_dffc ( .d(dffb_out),
3471 .clk(lvds_dffc_clk),
3474 assign lvds_dffc_clk = (l_enable0_counter == "l0") ? l0_clk : (l_enable0_counter == "l1") ? l1_clk : 1'b0;
3476 assign nce_temp = ~dffc_out && dffb_out;
3478 MF_pll_reg lvds_dffd ( .d(nce_temp),
3482 .clk(~lvds_dffd_clk),
3485 assign lvds_dffd_clk = (l_enable0_counter == "l0") ? l0_clk : (l_enable0_counter == "l1") ? l1_clk : 1'b0;
3487 assign nce_l0 = (l_enable0_counter == "l0") ? dffd_out : 'b0;
3488 assign nce_l1 = (l_enable0_counter == "l1") ? dffd_out : 'b0;
3490 stx_scale_cntr g1 ( .clk(vco_out[i_g1_ph]),
3491 .reset(areset_ipd || (!ena_ipd) || stop_vco),
3495 .initial_value(g1_initial_val),
3497 .time_delay(g1_time_delay_val),
3500 stx_scale_cntr g2 ( .clk(vco_out[i_g2_ph]),
3501 .reset(areset_ipd || (!ena_ipd) || stop_vco),
3505 .initial_value(g2_initial_val),
3507 .time_delay(g2_time_delay_val),
3510 stx_scale_cntr g3 ( .clk(vco_out[i_g3_ph]),
3511 .reset(areset_ipd || (!ena_ipd) || stop_vco),
3515 .initial_value(g3_initial_val),
3517 .time_delay(g3_time_delay_val),
3519 assign cntr_e0_initial = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e0") ? 1 : e0_initial_val;
3520 assign cntr_e0_delay = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e0") ? ext_fbk_delay : e0_time_delay_val;
3522 stx_scale_cntr e0 ( .clk(vco_out[i_e0_ph]),
3523 .reset(areset_ipd || (!ena_ipd) || stop_vco),
3527 .initial_value(cntr_e0_initial),
3529 .time_delay(cntr_e0_delay),
3532 assign cntr_e1_initial = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e1") ? 1 : e1_initial_val;
3533 assign cntr_e1_delay = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e1") ? ext_fbk_delay : e1_time_delay_val;
3534 stx_scale_cntr e1 ( .clk(vco_out[i_e1_ph]),
3535 .reset(areset_ipd || (!ena_ipd) || stop_vco),
3539 .initial_value(cntr_e1_initial),
3541 .time_delay(cntr_e1_delay),
3544 assign cntr_e2_initial = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e2") ? 1 : e2_initial_val;
3545 assign cntr_e2_delay = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e2") ? ext_fbk_delay : e2_time_delay_val;
3546 stx_scale_cntr e2 ( .clk(vco_out[i_e2_ph]),
3547 .reset(areset_ipd || (!ena_ipd) || stop_vco),
3551 .initial_value(cntr_e2_initial),
3553 .time_delay(cntr_e2_delay),
3556 assign cntr_e3_initial = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e3") ? 1 : e3_initial_val;
3557 assign cntr_e3_delay = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e3") ? ext_fbk_delay : e3_time_delay_val;
3558 stx_scale_cntr e3 ( .clk(vco_out[i_e3_ph]),
3559 .reset(areset_ipd || (!ena_ipd) || stop_vco),
3563 .initial_value(cntr_e3_initial),
3565 .time_delay(cntr_e3_delay),
3569 always @(vco_out[i_l0_ph] or posedge areset_ipd or negedge ena_ipd or stop_vco)
3571 if ((areset_ipd == 1'b1) || (ena_ipd == 1'b0) || (stop_vco == 1'b1))
3574 l0_got_first_rising_edge = 0;
3579 if (l0_got_first_rising_edge == 1'b0)
3581 if (vco_out[i_l0_ph] == 1'b1 && vco_out[i_l0_ph] != vco_l0_last_value)
3582 l0_got_first_rising_edge = 1;
3584 else if (vco_out[i_l0_ph] != vco_l0_last_value)
3586 l0_count = l0_count + 1;
3587 if (l0_count == (l0_high_val + l0_low_val) * 2)
3591 if (vco_out[i_l0_ph] == 1'b0 && vco_out[i_l0_ph] != vco_l0_last_value)
3596 l0_got_first_rising_edge = 0;
3601 vco_l0_last_value = vco_out[i_l0_ph];
3604 always @(vco_out[i_l1_ph] or posedge areset_ipd or negedge ena_ipd or stop_vco)
3606 if (areset_ipd == 1'b1 || ena_ipd == 1'b0 || stop_vco == 1'b1)
3609 l1_got_first_rising_edge = 0;
3614 if (l1_got_first_rising_edge == 1'b0)
3616 if (vco_out[i_l1_ph] == 1'b1 && vco_out[i_l1_ph] != vco_l1_last_value)
3617 l1_got_first_rising_edge = 1;
3619 else if (vco_out[i_l1_ph] != vco_l1_last_value)
3621 l1_count = l1_count + 1;
3622 if (l1_count == (l1_high_val + l1_low_val) * 2)
3626 if (vco_out[i_l1_ph] == 1'b0 && vco_out[i_l1_ph] != vco_l1_last_value)
3631 l1_got_first_rising_edge = 0;
3636 vco_l1_last_value = vco_out[i_l1_ph];
3639 assign enable0_tmp = (l_enable0_counter == "l0") ? l0_tmp : l1_tmp;
3640 assign enable1_tmp = (l_enable1_counter == "l0") ? l0_tmp : l1_tmp;
3642 always @ (inclk_n or ena_ipd or areset_ipd)
3644 if (areset_ipd == 'b1)
3649 else if (inclk_n == 'b1 && inclk_last_value != inclk_n)
3652 gate_count = gate_count + 1;
3653 if (gate_count == gate_lock_counter)
3656 inclk_last_value = inclk_n;
3659 assign locked = (l_gate_lock_signal == "yes") ? gate_out && locked_tmp : locked_tmp;
3661 always @ (scanclk_ipd or scanaclr_ipd)
3663 if (scanaclr_ipd === 1'b1 && scanaclr_last_value === 1'b0)
3664 scanaclr_rising_time = $time;
3665 else if (scanaclr_ipd === 1'b0 && scanaclr_last_value === 1'b1)
3667 scanaclr_falling_time = $time;
3668 // check for scanaclr active pulse width
3669 if ($time - scanaclr_rising_time < TRST)
3671 scanclr_violation = 1;
3672 $display ("Warning : Detected SCANACLR ACTIVE pulse width violation. Required is 5000 ps, actual is %0t. Reconfiguration may not work.", $time - scanaclr_rising_time);
3673 $display ("Time: %0t Instance: %m", $time);
3676 scanclr_violation = 0;
3677 for (i = 0; i <= scan_chain_length; i = i + 1)
3680 got_first_scanclk_after_scanclr_inactive_edge = 0;
3682 else if ((scanclk_ipd === 'b1 && scanclk_last_value !== scanclk_ipd) && (got_first_scanclk_after_scanclr_inactive_edge === 1'b0) && ($time - scanaclr_falling_time < TRSTCLK))
3684 scanclr_clk_violation = 1;
3685 $display ("Warning : Detected SCANACLR INACTIVE time violation before rising edge of SCANCLK. Required is 5000 ps, actual is %0t. Reconfiguration may not work.", $time - scanaclr_falling_time);
3686 $display ("Time: %0t Instance: %m", $time);
3687 got_first_scanclk_after_scanclr_inactive_edge = 1;
3689 else if (scanclk_ipd == 'b1 && scanclk_last_value != scanclk_ipd && scanaclr_ipd === 1'b0)
3691 if (pll_in_quiet_period && ($time - start_quiet_time < quiet_time))
3693 $display("Time: %0t", $time, " Warning : Detected transition on SCANCLK during quiet time. PLL may not function correctly.");
3694 quiet_period_violation = 1;
3697 pll_in_quiet_period = 0;
3698 for (j = scan_chain_length-1; j >= 1; j = j - 1)
3700 scan_data[j] = scan_data[j - 1];
3702 scan_data[0] = scandata_ipd;
3704 if (got_first_scanclk_after_scanclr_inactive_edge === 1'b0)
3706 got_first_scanclk_after_scanclr_inactive_edge = 1;
3707 scanclr_clk_violation = 0;
3710 else if (scanclk_ipd === 1'b0 && scanclk_last_value !== scanclk_ipd && scanaclr_ipd === 1'b0)
3712 if (pll_in_quiet_period && ($time - start_quiet_time < quiet_time))
3714 $display("Time: %0t", $time, " Warning : Detected transition on SCANCLK during quiet time. PLL may not function correctly.");
3715 quiet_period_violation = 1;
3717 else if (scan_data[scan_chain_length-1] == 1'b1)
3719 pll_in_quiet_period = 1;
3720 quiet_period_violation = 0;
3722 start_quiet_time = $time;
3723 // initiate transfer
3724 scandataout_tmp <= 1'b1;
3725 quiet_time = slowest_clk ( l0_high_val+l0_low_val,
3726 l1_high_val+l1_low_val,
3727 g0_high_val+g0_low_val,
3728 g1_high_val+g1_low_val,
3729 g2_high_val+g2_low_val,
3730 g3_high_val+g3_low_val,
3731 e0_high_val+e0_low_val,
3732 e1_high_val+e1_low_val,
3733 e2_high_val+e2_low_val,
3734 e3_high_val+e3_low_val,
3736 refclk_period, m_val);
3740 scanclk_last_value = scanclk_ipd;
3741 scanaclr_last_value = scanaclr_ipd;
3744 always @(scandataout_tmp)
3746 if (scandataout_tmp == 1'b1)
3747 scandataout_tmp <= #(quiet_time) 1'b0;
3750 always @(posedge transfer)
3752 if (transfer == 1'b1)
3754 $display("NOTE : Reconfiguring PLL");
3755 $display ("Time: %0t Instance: %m", $time);
3756 if (l_scan_chain == "long")
3760 if (scan_data[273] == 1'b1)
3762 e3_mode_val = "bypass";
3763 if (scan_data[283] == 1'b1)
3765 e3_mode_val = "off";
3766 $display("Warning : The specified bit settings will turn OFF the E3 counter. It cannot be turned on unless the part is re-initialized.");
3769 else if (scan_data[283] == 1'b1)
3770 e3_mode_val = "odd";
3772 e3_mode_val = "even";
3773 // before reading delay bits, clear e3_time_delay_val
3774 e3_time_delay_val = 32'b0;
3775 e3_time_delay_val = scan_data[287:284];
3776 e3_time_delay_val = e3_time_delay_val * 250;
3777 if (e3_time_delay_val > 3000)
3778 e3_time_delay_val = 3000;
3779 e3_high_val[8:0] <= scan_data[272:264];
3780 e3_low_val[8:0] <= scan_data[282:274];
3781 if (scan_data[272:264] == 9'b000000000)
3782 e3_high_val[9:0] <= 10'b1000000000;
3783 if (scan_data[282:274] == 9'b000000000)
3784 e3_low_val[9:0] <= 10'b1000000000;
3786 if (ext_fbk_cntr == "e3")
3788 ext_fbk_cntr_high = e3_high_val;
3789 ext_fbk_cntr_low = e3_low_val;
3790 ext_fbk_cntr_delay = e3_time_delay_val;
3791 ext_fbk_cntr_mode = e3_mode_val;
3795 if (scan_data[249] == 1'b1)
3797 e2_mode_val = "bypass";
3798 if (scan_data[259] == 1'b1)
3800 e2_mode_val = "off";
3801 $display("Warning : The specified bit settings will turn OFF the E2 counter. It cannot be turned on unless the part is re-initialized.");
3804 else if (scan_data[259] == 1'b1)
3805 e2_mode_val = "odd";
3807 e2_mode_val = "even";
3808 e2_time_delay_val = 32'b0;
3809 e2_time_delay_val = scan_data[263:260];
3810 e2_time_delay_val = e2_time_delay_val * 250;
3811 if (e2_time_delay_val > 3000)
3812 e2_time_delay_val = 3000;
3813 e2_high_val[8:0] <= scan_data[248:240];
3814 e2_low_val[8:0] <= scan_data[258:250];
3815 if (scan_data[248:240] == 9'b000000000)
3816 e2_high_val[9:0] <= 10'b1000000000;
3817 if (scan_data[258:250] == 9'b000000000)
3818 e2_low_val[9:0] <= 10'b1000000000;
3820 if (ext_fbk_cntr == "e2")
3822 ext_fbk_cntr_high = e2_high_val;
3823 ext_fbk_cntr_low = e2_low_val;
3824 ext_fbk_cntr_delay = e2_time_delay_val;
3825 ext_fbk_cntr_mode = e2_mode_val;
3829 if (scan_data[225] == 1'b1)
3831 e1_mode_val = "bypass";
3832 if (scan_data[235] == 1'b1)
3834 e1_mode_val = "off";
3835 $display("Warning : The specified bit settings will turn OFF the E1 counter. It cannot be turned on unless the part is re-initialized.");
3838 else if (scan_data[235] == 1'b1)
3839 e1_mode_val = "odd";
3841 e1_mode_val = "even";
3842 e1_time_delay_val = 32'b0;
3843 e1_time_delay_val = scan_data[239:236];
3844 e1_time_delay_val = e1_time_delay_val * 250;
3845 if (e1_time_delay_val > 3000)
3846 e1_time_delay_val = 3000;
3847 e1_high_val[8:0] <= scan_data[224:216];
3848 e1_low_val[8:0] <= scan_data[234:226];
3849 if (scan_data[224:216] == 9'b000000000)
3850 e1_high_val[9:0] <= 10'b1000000000;
3851 if (scan_data[234:226] == 9'b000000000)
3852 e1_low_val[9:0] <= 10'b1000000000;
3854 if (ext_fbk_cntr == "e1")
3856 ext_fbk_cntr_high = e1_high_val;
3857 ext_fbk_cntr_low = e1_low_val;
3858 ext_fbk_cntr_delay = e1_time_delay_val;
3859 ext_fbk_cntr_mode = e1_mode_val;
3863 if (scan_data[201] == 1'b1)
3865 e0_mode_val = "bypass";
3866 if (scan_data[211] == 1'b1)
3868 e0_mode_val = "off";
3869 $display("Warning : The specified bit settings will turn OFF the E0 counter. It cannot be turned on unless the part is re-initialized.");
3872 else if (scan_data[211] == 1'b1)
3873 e0_mode_val = "odd";
3875 e0_mode_val = "even";
3876 e0_time_delay_val = 32'b0;
3877 e0_time_delay_val = scan_data[215:212];
3878 e0_time_delay_val = e0_time_delay_val * 250;
3879 if (e0_time_delay_val > 3000)
3880 e0_time_delay_val = 3000;
3881 e0_high_val[8:0] <= scan_data[200:192];
3882 e0_low_val[8:0] <= scan_data[210:202];
3883 if (scan_data[200:192] == 9'b000000000)
3884 e0_high_val[9:0] <= 10'b1000000000;
3885 if (scan_data[210:202] == 9'b000000000)
3886 e0_low_val[9:0] <= 10'b1000000000;
3888 if (ext_fbk_cntr == "e0")
3890 ext_fbk_cntr_high = e0_high_val;
3891 ext_fbk_cntr_low = e0_low_val;
3892 ext_fbk_cntr_delay = e0_time_delay_val;
3893 ext_fbk_cntr_mode = e0_mode_val;
3898 if (scan_data[177] == 1'b1)
3900 l1_mode_val = "bypass";
3901 if (scan_data[187] == 1'b1)
3903 l1_mode_val = "off";
3904 $display("Warning : The specified bit settings will turn OFF the L1 counter. It cannot be turned on unless the part is re-initialized.");
3907 else if (scan_data[187] == 1'b1)
3908 l1_mode_val = "odd";
3910 l1_mode_val = "even";
3911 l1_time_delay_val = 32'b0;
3912 l1_time_delay_val = scan_data[191:188];
3913 l1_time_delay_val = l1_time_delay_val * 250;
3914 if (l1_time_delay_val > 3000)
3915 l1_time_delay_val = 3000;
3916 l1_high_val[8:0] <= scan_data[176:168];
3917 l1_low_val[8:0] <= scan_data[186:178];
3918 if (scan_data[176:168] == 9'b000000000)
3919 l1_high_val[9:0] <= 10'b1000000000;
3920 if (scan_data[186:178] == 9'b000000000)
3921 l1_low_val[9:0] <= 10'b1000000000;
3924 if (scan_data[153] == 1'b1)
3926 l0_mode_val = "bypass";
3927 if (scan_data[163] == 1'b1)
3929 l0_mode_val = "off";
3930 $display("Warning : The specified bit settings will turn OFF the L0 counter. It cannot be turned on unless the part is re-initialized.");
3933 else if (scan_data[163] == 1'b1)
3934 l0_mode_val = "odd";
3936 l0_mode_val = "even";
3937 l0_time_delay_val = 32'b0;
3938 l0_time_delay_val = scan_data[167:164];
3939 l0_time_delay_val = l0_time_delay_val * 250;
3940 if (l0_time_delay_val > 3000)
3941 l0_time_delay_val = 3000;
3942 l0_high_val[8:0] <= scan_data[152:144];
3943 l0_low_val[8:0] <= scan_data[162:154];
3944 if (scan_data[152:144] == 9'b000000000)
3945 l0_high_val[9:0] <= 10'b1000000000;
3946 if (scan_data[162:154] == 9'b000000000)
3947 l0_low_val[9:0] <= 10'b1000000000;
3950 if (scan_data[129] == 1'b1)
3952 g3_mode_val = "bypass";
3953 if (scan_data[139] == 1'b1)
3955 g3_mode_val = "off";
3956 $display("Warning : The specified bit settings will turn OFF the G3 counter. It cannot be turned on unless the part is re-initialized.");
3959 else if (scan_data[139] == 1'b1)
3960 g3_mode_val = "odd";
3962 g3_mode_val = "even";
3963 g3_time_delay_val = 32'b0;
3964 g3_time_delay_val = scan_data[143:140];
3965 g3_time_delay_val = g3_time_delay_val * 250;
3966 if (g3_time_delay_val > 3000)
3967 g3_time_delay_val = 3000;
3968 g3_high_val[8:0] <= scan_data[128:120];
3969 g3_low_val[8:0] <= scan_data[138:130];
3970 if (scan_data[128:120] == 9'b000000000)
3971 g3_high_val[9:0] <= 10'b1000000000;
3972 if (scan_data[138:130] == 9'b000000000)
3973 g3_low_val[9:0] <= 10'b1000000000;
3976 if (scan_data[105] == 1'b1)
3978 g2_mode_val = "bypass";
3979 if (scan_data[115] == 1'b1)
3981 g2_mode_val = "off";
3982 $display("Warning : The specified bit settings will turn OFF the G2 counter. It cannot be turned on unless the part is re-initialized.");
3985 else if (scan_data[115] == 1'b1)
3986 g2_mode_val = "odd";
3988 g2_mode_val = "even";
3989 g2_time_delay_val = 32'b0;
3990 g2_time_delay_val = scan_data[119:116];
3991 g2_time_delay_val = g2_time_delay_val * 250;
3992 if (g2_time_delay_val > 3000)
3993 g2_time_delay_val = 3000;
3994 g2_high_val[8:0] <= scan_data[104:96];
3995 g2_low_val[8:0] <= scan_data[114:106];
3996 if (scan_data[104:96] == 9'b000000000)
3997 g2_high_val[9:0] <= 10'b1000000000;
3998 if (scan_data[114:106] == 9'b000000000)
3999 g2_low_val[9:0] <= 10'b1000000000;
4002 if (scan_data[81] == 1'b1)
4004 g1_mode_val = "bypass";
4005 if (scan_data[91] == 1'b1)
4007 g1_mode_val = "off";
4008 $display("Warning : The specified bit settings will turn OFF the G1 counter. It cannot be turned on unless the part is re-initialized.");
4011 else if (scan_data[91] == 1'b1)
4012 g1_mode_val = "odd";
4014 g1_mode_val = "even";
4015 g1_time_delay_val = 32'b0;
4016 g1_time_delay_val = scan_data[95:92];
4017 g1_time_delay_val = g1_time_delay_val * 250;
4018 if (g1_time_delay_val > 3000)
4019 g1_time_delay_val = 3000;
4020 g1_high_val[8:0] <= scan_data[80:72];
4021 g1_low_val[8:0] <= scan_data[90:82];
4022 if (scan_data[80:72] == 9'b000000000)
4023 g1_high_val[9:0] <= 10'b1000000000;
4024 if (scan_data[90:82] == 9'b000000000)
4025 g1_low_val[9:0] <= 10'b1000000000;
4028 if (scan_data[57] == 1'b1)
4030 g0_mode_val = "bypass";
4031 if (scan_data[67] == 1'b1)
4033 g0_mode_val = "off";
4034 $display("Warning : The specified bit settings will turn OFF the G0 counter. It cannot be turned on unless the part is re-initialized.");
4037 else if (scan_data[67] == 1'b1)
4038 g0_mode_val = "odd";
4040 g0_mode_val = "even";
4041 g0_time_delay_val = 32'b0;
4042 g0_time_delay_val = scan_data[71:68];
4043 g0_time_delay_val = g0_time_delay_val * 250;
4044 if (g0_time_delay_val > 3000)
4045 g0_time_delay_val = 3000;
4046 g0_high_val[8:0] <= scan_data[56:48];
4047 g0_low_val[8:0] <= scan_data[66:58];
4048 if (scan_data[56:48] == 9'b000000000)
4049 g0_high_val[9:0] <= 10'b1000000000;
4050 if (scan_data[66:58] == 9'b000000000)
4051 g0_low_val[9:0] <= 10'b1000000000;
4055 m_val_tmp[8:0] = scan_data[32:24];
4056 if (scan_data[33] !== 1'b1)
4058 if (m_val_tmp[8:0] == 9'b000000001)
4062 $display ("Warning : Illegal 1 value for M counter. Instead, the M counter should be BYPASSED. Reconfiguration may not work.");
4064 else if (m_val_tmp[8:0] == 9'b000000000)
4065 m_val_tmp[9:0] = 10'b1000000000;
4068 if (m_mode_val === "bypass")
4069 $display ("Warning : M counter switched from BYPASS mode to enabled (M modulus = %d). PLL may lose lock.", m_val_tmp[9:0]);
4071 $display("PLL reconfigured with : M modulus = %d ", m_val_tmp[9:0]);
4075 else if (scan_data[33] == 1'b1)
4077 if (scan_data[24] !== 1'b0)
4081 $display ("Warning : Illegal value for counter M in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.");
4084 if (m_mode_val !== "bypass")
4085 $display ("Warning : M counter switched from enabled to BYPASS mode. PLL may lose lock.");
4086 m_val_tmp[9:0] = 10'b0000000001;
4087 m_mode_val = "bypass";
4088 $display("PLL reconfigured with : M modulus = %d ", m_val_tmp[9:0]);
4092 if (skip_vco == "on")
4093 m_val_tmp[9:0] = 10'b0000000001;
4099 m2_val[8:0] = scan_data[42:34];
4100 if (scan_data[43] !== 1'b1)
4102 if (m2_val[8:0] == 9'b000000001)
4106 $display ("Warning : Illegal 1 value for M2 counter. Instead, the M2 counter should be BYPASSED. Reconfiguration may not work.");
4108 else if (m2_val[8:0] == 9'b000000000)
4109 m2_val[9:0] = 10'b1000000000;
4112 if (m2_mode_val === "bypass")
4113 $display ("Warning : M2 counter switched from BYPASS mode to enabled (M2 modulus = %d). Pll may lose lock.", m2_val[9:0]);
4115 $display(" M2 modulus = %d ", m2_val[9:0]);
4119 else if (scan_data[43] == 1'b1)
4121 if (scan_data[34] !== 1'b0)
4125 $display ("Warning : Illegal value for counter M2 in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.");
4128 if (m2_mode_val !== "bypass")
4129 $display ("Warning : M2 counter switched from enabled to BYPASS mode. PLL may lose lock.");
4130 m2_val[9:0] = 10'b0000000001;
4131 m2_mode_val = "bypass";
4132 $display(" M2 modulus = %d ", m2_val[9:0]);
4135 if (m_mode_val != m2_mode_val)
4139 $display ("Warning : Incompatible modes for M1/M2 counters. Either both should be BYASSED or both NON-BYPASSED. Reconfiguration may not work.");
4143 m_time_delay_val = 32'b0;
4144 m_time_delay_val = scan_data[47:44];
4145 m_time_delay_val = m_time_delay_val * 250;
4146 if (m_time_delay_val > 3000)
4147 m_time_delay_val = 3000;
4148 if (skip_vco == "on")
4149 m_time_delay_val = 32'b0;
4150 $display(" M time delay = %0d", m_time_delay_val);
4154 n_val_tmp[8:0] = scan_data[8:0];
4155 if (scan_data[9] !== 1'b1)
4157 if (n_val_tmp[8:0] == 9'b000000001)
4161 $display ("Warning : Illegal 1 value for N counter. Instead, the N counter should be BYPASSED. Reconfiguration may not work.");
4163 else if (n_val_tmp[8:0] == 9'b000000000)
4164 n_val_tmp[9:0] = 10'b1000000000;
4167 if (n_mode_val === "bypass")
4168 $display ("Warning : N counter switched from BYPASS mode to enabled (N modulus = %d). PLL may lose lock.", n_val_tmp[9:0]);
4170 $display(" N modulus = %d ", n_val_tmp[9:0]);
4174 else if (scan_data[9] == 1'b1) // bypass
4176 if (scan_data[0] !== 1'b0)
4180 $display ("Warning : Illegal value for counter N in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.");
4183 if (n_mode_val !== "bypass")
4184 $display ("Warning : N counter switched from enabled to BYPASS mode. PLL may lose lock.");
4185 n_val_tmp[9:0] = 10'b0000000001;
4186 n_mode_val = "bypass";
4187 $display(" N modulus = %d ", n_val_tmp[9:0]);
4195 n2_val[8:0] = scan_data[18:10];
4196 if (scan_data[19] !== 1'b1)
4198 if (n2_val[8:0] == 9'b000000001)
4202 $display ("Warning : Illegal 1 value for N2 counter. Instead, the N2 counter should be BYPASSED. Reconfiguration may not work.");
4204 else if (n2_val[8:0] == 9'b000000000)
4205 n2_val = 10'b1000000000;
4208 if (n2_mode_val === "bypass")
4209 $display ("Warning : N2 counter switched from BYPASS mode to enabled (N2 modulus = %d). PLL may lose lock.", n2_val[9:0]);
4211 $display(" N2 modulus = %d ", n2_val[9:0]);
4215 else if (scan_data[19] == 1'b1) // bypass
4217 if (scan_data[10] !== 1'b0)
4221 $display ("Warning : Illegal value for counter N2 in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.");
4224 if (n2_mode_val !== "bypass")
4225 $display ("Warning : N2 counter switched from enabled to BYPASS mode. PLL may lose lock.");
4226 n2_val[9:0] = 10'b0000000001;
4227 n2_mode_val = "bypass";
4228 $display(" N2 modulus = %d ", n2_val[9:0]);
4231 if (n_mode_val != n2_mode_val)
4235 $display ("Warning : Incompatible modes for N1/N2 counters. Either both should be BYASSED or both NON-BYPASSED.");
4239 n_time_delay_val = 32'b0;
4240 n_time_delay_val = scan_data[23:20];
4241 n_time_delay_val = n_time_delay_val * 250;
4242 if (n_time_delay_val > 3000)
4243 n_time_delay_val = 3000;
4244 $display(" N time delay = %0d", n_time_delay_val);
4247 // clear the scan_chain
4248 for (i = 0; i <= scan_chain_length; i = i + 1)
4253 always @(negedge transfer)
4255 if (l_scan_chain == "long")
4257 $display(" E3 high = %d, E3 low = %d, E3 mode = %s, E3 time delay = %0d", e3_high_val[9:0], e3_low_val[9:0], e3_mode_val, e3_time_delay_val);
4258 $display(" E2 high = %d, E2 low = %d, E2 mode = %s, E2 time delay = %0d", e2_high_val[9:0], e2_low_val[9:0], e2_mode_val, e2_time_delay_val);
4259 $display(" E1 high = %d, E1 low = %d, E1 mode = %s, E1 time delay = %0d", e1_high_val[9:0], e1_low_val[9:0], e1_mode_val, e1_time_delay_val);
4260 $display(" E0 high = %d, E0 low = %d, E0 mode = %s, E0 time delay = %0d", e0_high_val[9:0], e0_low_val[9:0], e0_mode_val, e0_time_delay_val);
4262 $display(" L1 high = %d, L1 low = %d, L1 mode = %s, L1 time delay = %0d", l1_high_val[9:0], l1_low_val[9:0], l1_mode_val, l1_time_delay_val);
4263 $display(" L0 high = %d, L0 low = %d, L0 mode = %s, L0 time delay = %0d", l0_high_val[9:0], l0_low_val[9:0], l0_mode_val, l0_time_delay_val);
4264 $display(" G3 high = %d, G3 low = %d, G3 mode = %s, G3 time delay = %0d", g3_high_val[9:0], g3_low_val[9:0], g3_mode_val, g3_time_delay_val);
4265 $display(" G2 high = %d, G2 low = %d, G2 mode = %s, G2 time delay = %0d", g2_high_val[9:0], g2_low_val[9:0], g2_mode_val, g2_time_delay_val);
4266 $display(" G1 high = %d, G1 low = %d, G1 mode = %s, G1 time delay = %0d", g1_high_val[9:0], g1_low_val[9:0], g1_mode_val, g1_time_delay_val);
4267 $display(" G0 high = %d, G0 low = %d, G0 mode = %s, G0 time delay = %0d", g0_high_val[9:0], g0_low_val[9:0], g0_mode_val, g0_time_delay_val);
4270 always @(schedule_vco or areset_ipd or ena_ipd)
4274 for (i = 0; i <= 7; i=i+1)
4275 last_phase_shift[i] = phase_shift[i];
4277 cycle_to_adjust = 0;
4279 m_times_vco_period = new_m_times_vco_period;
4281 // give appropriate messages
4282 // if areset was asserted
4283 if (areset_ipd == 1'b1 && areset_ipd_last_value !== areset_ipd)
4285 $display (" Note : Stratix PLL was reset");
4286 $display ("Time: %0t Instance: %m", $time);
4289 // if ena was deasserted
4290 if (ena_ipd == 1'b0 && ena_ipd_last_value !== ena_ipd)
4292 $display (" Note : Stratix PLL was disabled");
4293 $display ("Time: %0t Instance: %m", $time);
4296 // illegal value on areset_ipd
4297 if (areset_ipd === 1'bx && (areset_ipd_last_value === 1'b0 || areset_ipd_last_value === 1'b1))
4299 $display("Warning : Illegal value 'X' detected on ARESET input");
4300 $display ("Time: %0t Instance: %m", $time);
4303 if ((schedule_vco !== schedule_vco_last_value) && (areset_ipd == 1'b1 || ena_ipd == 1'b0 || stop_vco == 1'b1))
4306 // drop VCO taps to 0
4307 for (i = 0; i <= 7; i=i+1)
4309 for (j = 0; j <= last_phase_shift[i] + 1; j=j+1)
4310 vco_out[i] <= #(j) 1'b0;
4312 last_phase_shift[i] = 0;
4315 // reset lock parameters
4317 if (l_pll_type == "fast")
4320 pll_about_to_lock = 0;
4322 cycles_to_unlock = 0;
4324 got_first_refclk = 0;
4325 got_second_refclk = 0;
4327 got_first_fbclk = 0;
4329 first_fbclk_time = 0;
4333 schedule_offset = 1;
4335 vco_period_was_phase_adjusted = 0;
4336 phase_adjust_was_scheduled = 0;
4338 // reset enable0 and enable1 counter parameters
4341 // l0_got_first_rising_edge = 0;
4342 // l1_got_first_rising_edge = 0;
4344 end else if (ena_ipd === 1'b1 && areset_ipd === 1'b0 && stop_vco === 1'b0)
4347 // else note areset deassert time
4348 // note it as refclk_time to prevent false triggering
4349 // of stop_vco after areset
4350 if (areset_ipd === 1'b0 && areset_ipd_last_value === 1'b1)
4352 refclk_time = $time;
4355 // calculate loop_xplier : this will be different from m_val in ext. fbk mode
4356 loop_xplier = m_val;
4357 loop_initial = i_m_initial - 1;
4359 loop_time_delay = m_time_delay_val;
4361 if (l_operation_mode == "external_feedback")
4363 if (ext_fbk_cntr_mode == "bypass")
4364 ext_fbk_cntr_modulus = 1;
4366 ext_fbk_cntr_modulus = ext_fbk_cntr_high + ext_fbk_cntr_low;
4368 loop_xplier = m_val * (ext_fbk_cntr_modulus);
4369 loop_ph = ext_fbk_cntr_ph;
4370 loop_initial = ext_fbk_cntr_initial - 1 + ((i_m_initial - 1) * (ext_fbk_cntr_modulus));
4371 loop_time_delay = m_time_delay_val + ext_fbk_cntr_delay;
4374 // convert initial value to delay
4375 initial_delay = (loop_initial * m_times_vco_period)/loop_xplier;
4377 // convert loop ph_tap to delay
4378 rem = m_times_vco_period % loop_xplier;
4379 vco_per = m_times_vco_period/loop_xplier;
4381 vco_per = vco_per + 1;
4382 fbk_phase = (loop_ph * vco_per)/8;
4384 if (l_operation_mode == "external_feedback")
4386 pull_back_ext_cntr = ext_fbk_cntr_delay + (ext_fbk_cntr_initial - 1) * (m_times_vco_period/loop_xplier) + fbk_phase;
4388 while (pull_back_ext_cntr > refclk_period)
4389 pull_back_ext_cntr = pull_back_ext_cntr - refclk_period;
4391 pull_back_M = m_time_delay_val + (i_m_initial - 1) * (ext_fbk_cntr_modulus) * (m_times_vco_period/loop_xplier);
4393 while (pull_back_M > refclk_period)
4394 pull_back_M = pull_back_M - refclk_period;
4397 pull_back_ext_cntr = 0;
4398 pull_back_M = initial_delay + m_time_delay_val + fbk_phase;
4401 total_pull_back = pull_back_M + pull_back_ext_cntr;
4402 if (l_simulation_type == "timing")
4403 total_pull_back = total_pull_back + pll_compensation_delay;
4405 while (total_pull_back > refclk_period)
4406 total_pull_back = total_pull_back - refclk_period;
4408 if (total_pull_back > 0)
4409 offset = refclk_period - total_pull_back;
4411 if (l_operation_mode == "external_feedback")
4413 fbk_delay = pull_back_M;
4414 if (l_simulation_type == "timing")
4415 fbk_delay = fbk_delay + pll_compensation_delay;
4417 ext_fbk_delay = pull_back_ext_cntr - fbk_phase;
4420 fbk_delay = total_pull_back - fbk_phase;
4423 offset = offset - fbk_phase;
4424 fbk_delay = total_pull_back;
4429 m_delay = fbk_delay;
4431 for (i = 1; i <= loop_xplier; i=i+1)
4434 tmp_vco_per = m_times_vco_period/loop_xplier;
4435 if (rem != 0 && l_index <= rem)
4437 tmp_rem = (loop_xplier * l_index) % rem;
4438 cycle_to_adjust = (loop_xplier * l_index) / rem;
4440 cycle_to_adjust = cycle_to_adjust + 1;
4442 if (cycle_to_adjust == i)
4444 tmp_vco_per = tmp_vco_per + 1;
4445 l_index = l_index + 1;
4448 // calculate high and low periods
4449 high_time = tmp_vco_per/2;
4450 if (tmp_vco_per % 2 != 0)
4451 high_time = high_time + 1;
4452 low_time = tmp_vco_per - high_time;
4454 // schedule the rising and falling egdes
4455 for (j=0; j<=1; j=j+1)
4458 if (vco_val == 1'b0)
4459 sched_time = sched_time + high_time;
4461 sched_time = sched_time + low_time;
4464 if (schedule_offset == 1'b1)
4466 sched_time = sched_time + offset;
4467 schedule_offset = 0;
4470 // schedule taps with appropriate phase shifts
4471 for (k = 0; k <= 7; k=k+1)
4473 phase_shift[k] = (k*tmp_vco_per)/8;
4475 vco_out[k] <= #(sched_time + phase_shift[k]) vco_val;
4477 vco_out[k] <= #(sched_time + last_phase_shift[k]) vco_val;
4484 if (vco_val == 1'b0)
4485 sched_time = sched_time + high_time;
4487 sched_time = sched_time + low_time;
4488 for (k = 0; k <= 7; k=k+1)
4490 phase_shift[k] = (k*tmp_vco_per)/8;
4491 vco_out[k] <= #(sched_time+phase_shift[k]) vco_val;
4496 // this may no longer be required
4498 schedule_vco <= #(sched_time) ~schedule_vco;
4499 if (vco_period_was_phase_adjusted)
4501 m_times_vco_period = refclk_period;
4502 new_m_times_vco_period = refclk_period;
4503 vco_period_was_phase_adjusted = 0;
4504 phase_adjust_was_scheduled = 1;
4506 tmp_vco_per = m_times_vco_period/loop_xplier;
4507 for (k = 0; k <= 7; k=k+1)
4508 phase_shift[k] = (k*tmp_vco_per)/8;
4512 areset_ipd_last_value = areset_ipd;
4513 ena_ipd_last_value = ena_ipd;
4514 schedule_vco_last_value = schedule_vco;
4518 always @(pfdena_ipd)
4520 if (pfdena_ipd === 1'b0)
4525 $display (" Note : PFDENA was deasserted");
4526 $display ("Time: %0t Instance: %m", $time);
4528 else if (pfdena_ipd === 1'b1 && pfdena_ipd_last_value === 1'b0)
4530 // PFD was disabled, now enabled again
4531 got_first_refclk = 0;
4532 got_second_refclk = 0;
4533 refclk_time = $time;
4535 pfdena_ipd_last_value = pfdena_ipd;
4538 always @(negedge refclk)
4540 refclk_last_value = refclk;
4543 always @(negedge fbclk)
4545 fbclk_last_value = fbclk;
4548 always @(posedge refclk or posedge fbclk)
4550 if (refclk == 1'b1 && refclk_last_value !== refclk && areset_ipd === 1'b0)
4553 if (! got_first_refclk)
4555 got_first_refclk = 1;
4558 got_second_refclk = 1;
4559 refclk_period = $time - refclk_time;
4561 // check if incoming freq. will cause VCO range to be
4563 if ( (vco_max != 0 && vco_min != 0) && (skip_vco == "off") && (pfdena_ipd === 1'b1) &&
4564 ((refclk_period/loop_xplier > vco_max) ||
4565 (refclk_period/loop_xplier < vco_min)) )
4567 if (pll_is_locked == 1'b1)
4569 $display ("Warning : Input clock freq. is not within VCO range. PLL may lose lock");
4570 $display ("Time: %0t Instance: %m", $time);
4571 if (inclk_out_of_range === 1'b1)
4576 if (l_pll_type == "fast")
4578 pll_about_to_lock = 0;
4580 $display ("Note : Stratix PLL lost lock");
4581 $display ("Time: %0t Instance: %m", $time);
4583 schedule_offset = 1;
4584 vco_period_was_phase_adjusted = 0;
4585 phase_adjust_was_scheduled = 0;
4591 $display ("Warning : Input clock freq. is not within VCO range. PLL may not lock");
4592 $display ("Time: %0t Instance: %m", $time);
4596 inclk_out_of_range = 1;
4598 else if ( vco_min == 0 && vco_max == 0 && pll_type == "cdr")
4600 if (refclk_period != primary_clock_frequency)
4604 $display("Warning : Incoming clock period %d for Stratix PLL does not match the specified inclock period %d. ALTGXB simulation may not function correctly.", refclk_period, primary_clock_frequency);
4605 $display ("Time: %0t Instance: %m", $time);
4611 inclk_out_of_range = 0;
4615 if (stop_vco == 1'b1)
4618 schedule_vco = ~schedule_vco;
4620 refclk_time = $time;
4623 if (fbclk == 1'b1 && fbclk_last_value !== fbclk)
4626 if (!got_first_fbclk)
4628 got_first_fbclk = 1;
4629 first_fbclk_time = $time;
4632 fbclk_period = $time - fbclk_time;
4634 // need refclk_period here, so initialized to proper value above
4635 if ( ( ($time - refclk_time > 1.5 * refclk_period) && pfdena_ipd === 1'b1 && pll_is_locked == 1'b1) || ( ($time - refclk_time > 5 * refclk_period) && pfdena_ipd === 1'b1) )
4639 got_first_refclk = 0;
4640 got_first_fbclk = 0;
4641 got_second_refclk = 0;
4642 if (pll_is_locked == 1'b1)
4646 if (l_pll_type == "fast")
4648 $display ("Note : Stratix PLL lost lock due to loss of input clock");
4649 $display ("Time: %0t Instance: %m", $time);
4651 pll_about_to_lock = 0;
4653 cycles_to_unlock = 0;
4659 if (got_second_refclk && pfdena_ipd === 1'b1 && (!inclk_out_of_range))
4661 // now we know actual incoming period
4662 // if (abs(refclk_period - fbclk_period) > 2)
4664 // new_m_times_vco_period = refclk_period;
4666 // else if (abs(fbclk_time - refclk_time) <= 2 || (refclk_period - abs(fbclk_time - refclk_time) <= 2))
4667 if (abs(fbclk_time - refclk_time) <= 5 || (got_first_fbclk && abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5))
4669 // considered in phase
4670 if (cycles_to_lock == valid_lock_multiplier - 1)
4671 pll_about_to_lock <= 1;
4672 if (cycles_to_lock == valid_lock_multiplier)
4674 if (pll_is_locked === 1'b0)
4676 $display (" Note : Stratix PLL locked to incoming clock");
4677 $display ("Time: %0t Instance: %m", $time);
4681 if (l_pll_type == "fast")
4684 // increment lock counter only if the second part of the above
4685 // time check is NOT true
4686 if (!(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5))
4688 cycles_to_lock = cycles_to_lock + 1;
4691 // adjust m_times_vco_period
4692 new_m_times_vco_period = refclk_period;
4696 // if locked, begin unlock
4699 cycles_to_unlock = cycles_to_unlock + 1;
4700 if (cycles_to_unlock == invalid_lock_multiplier)
4704 if (l_pll_type == "fast")
4706 pll_about_to_lock = 0;
4708 $display ("Note : Stratix PLL lost lock");
4709 $display ("Time: %0t Instance: %m", $time);
4711 schedule_offset = 1;
4712 vco_period_was_phase_adjusted = 0;
4713 phase_adjust_was_scheduled = 0;
4716 if (abs(refclk_period - fbclk_period) <= 2)
4718 // frequency is still good
4719 if ($time == fbclk_time && (!phase_adjust_was_scheduled))
4721 if (abs(fbclk_time - refclk_time) > refclk_period/2)
4723 if (abs(fbclk_time - refclk_time) > 1.5 * refclk_period)
4725 // input clock may have stopped : do nothing
4728 new_m_times_vco_period = m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
4729 vco_period_was_phase_adjusted = 1;
4733 new_m_times_vco_period = m_times_vco_period - abs(fbclk_time - refclk_time);
4734 vco_period_was_phase_adjusted = 1;
4739 new_m_times_vco_period = refclk_period;
4740 phase_adjust_was_scheduled = 0;
4745 if (quiet_period_violation == 1'b1 || reconfig_err == 1'b1 || scanclr_violation == 1'b1 || scanclr_clk_violation == 1'b1)
4748 if (l_pll_type == "fast")
4752 refclk_last_value = refclk;
4753 fbclk_last_value = fbclk;
4756 assign clk0_tmp = i_clk0_counter == "l0" ? l0_clk : i_clk0_counter == "l1" ? l1_clk : i_clk0_counter == "g0" ? g0_clk : i_clk0_counter == "g1" ? g1_clk : i_clk0_counter == "g2" ? g2_clk : i_clk0_counter == "g3" ? g3_clk : 'b0;
4758 assign clk0 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk0_tmp : 'bx;
4760 dffp ena0_reg ( .D(clkena0_ipd),
4767 assign clk1_tmp = i_clk1_counter == "l0" ? l0_clk : i_clk1_counter == "l1" ? l1_clk : i_clk1_counter == "g0" ? g0_clk : i_clk1_counter == "g1" ? g1_clk : i_clk1_counter == "g2" ? g2_clk : i_clk1_counter == "g3" ? g3_clk : 'b0;
4769 assign clk1 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk1_tmp : 'bx;
4771 dffp ena1_reg ( .D(clkena1_ipd),
4778 assign clk2_tmp = i_clk2_counter == "l0" ? l0_clk : i_clk2_counter == "l1" ? l1_clk : i_clk2_counter == "g0" ? g0_clk : i_clk2_counter == "g1" ? g1_clk : i_clk2_counter == "g2" ? g2_clk : i_clk2_counter == "g3" ? g3_clk : 'b0;
4780 assign clk2 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk2_tmp : 'bx;
4782 dffp ena2_reg ( .D(clkena2_ipd),
4789 assign clk3_tmp = i_clk3_counter == "l0" ? l0_clk : i_clk3_counter == "l1" ? l1_clk : i_clk3_counter == "g0" ? g0_clk : i_clk3_counter == "g1" ? g1_clk : i_clk3_counter == "g2" ? g2_clk : i_clk3_counter == "g3" ? g3_clk : 'b0;
4791 assign clk3 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk3_tmp : 'bx;
4793 dffp ena3_reg ( .D(clkena3_ipd),
4800 assign clk4_tmp = i_clk4_counter == "l0" ? l0_clk : i_clk4_counter == "l1" ? l1_clk : i_clk4_counter == "g0" ? g0_clk : i_clk4_counter == "g1" ? g1_clk : i_clk4_counter == "g2" ? g2_clk : i_clk4_counter == "g3" ? g3_clk : 'b0;
4802 assign clk4 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk4_tmp : 'bx;
4804 dffp ena4_reg ( .D(clkena4_ipd),
4811 assign clk5_tmp = i_clk5_counter == "l0" ? l0_clk : i_clk5_counter == "l1" ? l1_clk : i_clk5_counter == "g0" ? g0_clk : i_clk5_counter == "g1" ? g1_clk : i_clk5_counter == "g2" ? g2_clk : i_clk5_counter == "g3" ? g3_clk : 'b0;
4813 assign clk5 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk5_tmp : 'bx;
4815 dffp ena5_reg ( .D(clkena5_ipd),
4822 assign extclk0_tmp = i_extclk0_counter == "e0" ? e0_clk : i_extclk0_counter == "e1" ? e1_clk : i_extclk0_counter == "e2" ? e2_clk : i_extclk0_counter == "e3" ? e3_clk : i_extclk0_counter == "g0" ? g0_clk : 'b0;
4824 assign extclk0 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? extclk0_tmp : 'bx;
4826 dffp extena0_reg ( .D(extclkena0_ipd),
4833 assign extclk1_tmp = i_extclk1_counter == "e0" ? e0_clk : i_extclk1_counter == "e1" ? e1_clk : i_extclk1_counter == "e2" ? e2_clk : i_extclk1_counter == "e3" ? e3_clk : i_extclk1_counter == "g0" ? g0_clk : 'b0;
4835 assign extclk1 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? extclk1_tmp : 'bx;
4837 dffp extena1_reg ( .D(extclkena1_ipd),
4844 assign extclk2_tmp = i_extclk2_counter == "e0" ? e0_clk : i_extclk2_counter == "e1" ? e1_clk : i_extclk2_counter == "e2" ? e2_clk : i_extclk2_counter == "e3" ? e3_clk : i_extclk2_counter == "g0" ? g0_clk : 'b0;
4846 assign extclk2 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? extclk2_tmp : 'bx;
4848 dffp extena2_reg ( .D(extclkena2_ipd),
4855 assign extclk3_tmp = i_extclk3_counter == "e0" ? e0_clk : i_extclk3_counter == "e1" ? e1_clk : i_extclk3_counter == "e2" ? e2_clk : i_extclk3_counter == "e3" ? e3_clk : i_extclk3_counter == "g0" ? g0_clk : 'b0;
4857 assign extclk3 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? extclk3_tmp : 'bx;
4859 dffp extena3_reg ( .D(extclkena3_ipd),
4866 assign enable_0 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || pll_about_to_lock == 1'b1 ? enable0_tmp : 'bx;
4867 assign enable_1 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || pll_about_to_lock == 1'b1 ? enable1_tmp : 'bx;
4869 // ACCELERATE OUTPUTS
4870 and (clk[0], ena0, clk0);
4871 and (clk[1], ena1, clk1);
4872 and (clk[2], ena2, clk2);
4873 and (clk[3], ena3, clk3);
4874 and (clk[4], ena4, clk4);
4875 and (clk[5], ena5, clk5);
4877 and (extclk[0], extena0, extclk0);
4878 and (extclk[1], extena1, extclk1);
4879 and (extclk[2], extena2, extclk2);
4880 and (extclk[3], extena3, extclk3);
4882 and (enable0, 1'b1, enable_0);
4883 and (enable1, 1'b1, enable_1);
4885 and (scandataout, 1'b1, scandataout_tmp);
4887 endmodule // MF_stratix_pll
4889 ///////////////////////////////////////////////////////////////////////////////
4891 // Module Name : arm_m_cntr
4893 // Description : Simulation model for the M counter. This is the
4894 // loop feedback counter for the StratixII PLL.
4896 ///////////////////////////////////////////////////////////////////////////////
4898 `timescale 1 ps / 1 ps
4899 module arm_m_cntr ( clk,
4909 input [31:0] initial_value;
4910 input [31:0] modulus;
4911 input [31:0] time_delay;
4916 // INTERNAL VARIABLES AND NETS
4919 reg first_rising_edge;
4926 first_rising_edge = 1;
4930 always @(reset or clk)
4936 first_rising_edge = 1;
4937 cout_tmp <= tmp_cout;
4940 if (clk == 1 && clk_last_value !== clk && first_rising_edge)
4942 first_rising_edge = 0;
4944 cout_tmp <= #(time_delay) tmp_cout;
4946 else if (first_rising_edge == 0)
4948 if (count < modulus)
4953 tmp_cout = ~tmp_cout;
4954 cout_tmp <= #(time_delay) tmp_cout;
4958 clk_last_value = clk;
4960 // cout_tmp <= #(time_delay) tmp_cout;
4963 and (cout, cout_tmp, 1'b1);
4965 endmodule // arm_m_cntr
4967 ///////////////////////////////////////////////////////////////////////////////
4969 // Module Name : arm_n_cntr
4971 // Description : Simulation model for the N counter. This is the
4972 // input clock divide counter for the StratixII PLL.
4974 ///////////////////////////////////////////////////////////////////////////////
4976 `timescale 1 ps / 1 ps
4977 module arm_n_cntr ( clk,
4985 input [31:0] modulus;
4990 // INTERNAL VARIABLES AND NETS
4993 reg first_rising_edge;
5000 first_rising_edge = 1;
5004 always @(reset or clk)
5010 first_rising_edge = 1;
5013 if (clk == 1 && clk_last_value !== clk && first_rising_edge)
5015 first_rising_edge = 0;
5018 else if (first_rising_edge == 0)
5020 if (count < modulus)
5025 tmp_cout = ~tmp_cout;
5029 clk_last_value = clk;
5033 assign cout = tmp_cout;
5035 endmodule // arm_n_cntr
5037 ///////////////////////////////////////////////////////////////////////////////
5039 // Module Name : arm_scale_cntr
5041 // Description : Simulation model for the output scale-down counters.
5042 // This is a common model for the C0, C1, C2, C3, C4 and
5043 // C5 output counters of the StratixII PLL.
5045 ///////////////////////////////////////////////////////////////////////////////
5047 `timescale 1 ps / 1 ps
5048 module arm_scale_cntr ( clk,
5062 input [31:0] initial_value;
5064 input [31:0] ph_tap;
5069 // INTERNAL VARIABLES AND NETS
5071 reg first_rising_edge;
5075 integer output_shift_count;
5081 first_rising_edge = 0;
5083 output_shift_count = 1;
5086 always @(clk or reset)
5096 output_shift_count = 1;
5098 first_rising_edge = 0;
5100 else if (clk_last_value !== clk)
5104 else if (mode == "bypass")
5107 first_rising_edge = 1;
5109 else if (first_rising_edge == 0)
5113 if (output_shift_count == initial_value)
5116 first_rising_edge = 1;
5119 output_shift_count = output_shift_count + 1;
5122 else if (output_shift_count < initial_value)
5125 output_shift_count = output_shift_count + 1;
5130 if (mode == " even" && (count == (high*2) + 1))
5132 else if (mode == " odd" && (count == (high*2)))
5134 else if (count == (high + low)*2 + 1)
5137 count = 1; // reset count
5141 clk_last_value = clk;
5142 cout_tmp <= tmp_cout;
5145 and (cout, cout_tmp, 1'b1);
5147 endmodule // arm_scale_cntr
5150 //////////////////////////////////////////////////////////////////////////////
5152 // Module Name : MF_stratixii_pll
5154 // Description : Behavioral model for StratixII pll.
5156 // Limitations : Does not support Spread Spectrum and Bandwidth.
5158 // Outputs : Up to 6 output clocks, each defined by its own set of
5159 // parameters. Locked output (active high) indicates when the
5160 // PLL locks. clkbad, clkloss and activeclock are used for
5161 // clock switchover to indicate which input clock has gone
5162 // bad, when the clock switchover initiates and which input
5163 // clock is being used as the reference, respectively.
5164 // scandataout is the data output of the serial scan chain.
5166 //////////////////////////////////////////////////////////////////////////////
5168 `timescale 1 ps/1 ps
5169 `define WORD_LENGTH 18
5171 module MF_stratixii_pll (inclk,
5196 parameter operation_mode = "normal";
5197 parameter pll_type = "auto";
5198 parameter compensate_clock = "clk0";
5199 parameter feedback_source = "clk0";
5200 parameter qualify_conf_done = "off";
5202 parameter test_input_comp_delay_chain_bits = 0;
5203 parameter test_feedback_comp_delay_chain_bits = 0;
5205 parameter inclk0_input_frequency = 10000;
5206 parameter inclk1_input_frequency = 10000;
5208 parameter gate_lock_signal = "no";
5209 parameter gate_lock_counter = 1;
5210 parameter self_reset_on_gated_loss_lock = "off";
5211 parameter valid_lock_multiplier = 1;
5212 parameter invalid_lock_multiplier = 5;
5214 parameter switch_over_type = "auto";
5215 parameter switch_over_on_lossclk = "off";
5216 parameter switch_over_on_gated_lock = "off";
5217 parameter switch_over_counter = 1;
5218 parameter enable_switch_over_counter = "on";
5220 parameter bandwidth = 0;
5221 parameter bandwidth_type = "auto";
5222 parameter down_spread = "0.0";
5223 parameter spread_frequency = 0;
5224 parameter common_rx_tx = "off";
5225 parameter rx_outclock_resource = "auto";
5226 parameter use_dc_coupling = "false";
5228 parameter clk0_output_frequency = 0;
5229 parameter clk0_multiply_by = 1;
5230 parameter clk0_divide_by = 1;
5231 parameter clk0_phase_shift = "0";
5232 parameter clk0_duty_cycle = 50;
5234 parameter clk1_output_frequency = 0;
5235 parameter clk1_multiply_by = 1;
5236 parameter clk1_divide_by = 1;
5237 parameter clk1_phase_shift = "0";
5238 parameter clk1_duty_cycle = 50;
5240 parameter clk2_output_frequency = 0;
5241 parameter clk2_multiply_by = 1;
5242 parameter clk2_divide_by = 1;
5243 parameter clk2_phase_shift = "0";
5244 parameter clk2_duty_cycle = 50;
5246 parameter clk3_output_frequency = 0;
5247 parameter clk3_multiply_by = 1;
5248 parameter clk3_divide_by = 1;
5249 parameter clk3_phase_shift = "0";
5250 parameter clk3_duty_cycle = 50;
5252 parameter clk4_output_frequency = 0;
5253 parameter clk4_multiply_by = 1;
5254 parameter clk4_divide_by = 1;
5255 parameter clk4_phase_shift = "0";
5256 parameter clk4_duty_cycle = 50;
5258 parameter clk5_output_frequency = 0;
5259 parameter clk5_multiply_by = 1;
5260 parameter clk5_divide_by = 1;
5261 parameter clk5_phase_shift = "0";
5262 parameter clk5_duty_cycle = 50;
5264 parameter pfd_min = 0;
5265 parameter pfd_max = 0;
5266 parameter vco_min = 0;
5267 parameter vco_max = 0;
5268 parameter vco_center = 0;
5270 // ADVANCED USE PARAMETERS
5271 parameter m_initial = 1;
5278 parameter c0_high = 1;
5279 parameter c0_low = 1;
5280 parameter c0_initial = 1;
5281 parameter c0_mode = "bypass";
5282 parameter c0_ph = 0;
5284 parameter c1_high = 1;
5285 parameter c1_low = 1;
5286 parameter c1_initial = 1;
5287 parameter c1_mode = "bypass";
5288 parameter c1_ph = 0;
5290 parameter c2_high = 1;
5291 parameter c2_low = 1;
5292 parameter c2_initial = 1;
5293 parameter c2_mode = "bypass";
5294 parameter c2_ph = 0;
5296 parameter c3_high = 1;
5297 parameter c3_low = 1;
5298 parameter c3_initial = 1;
5299 parameter c3_mode = "bypass";
5300 parameter c3_ph = 0;
5302 parameter c4_high = 1;
5303 parameter c4_low = 1;
5304 parameter c4_initial = 1;
5305 parameter c4_mode = "bypass";
5306 parameter c4_ph = 0;
5308 parameter c5_high = 1;
5309 parameter c5_low = 1;
5310 parameter c5_initial = 1;
5311 parameter c5_mode = "bypass";
5312 parameter c5_ph = 0;
5316 parameter clk0_counter = "c0";
5317 parameter clk1_counter = "c1";
5318 parameter clk2_counter = "c2";
5319 parameter clk3_counter = "c3";
5320 parameter clk4_counter = "c4";
5321 parameter clk5_counter = "c5";
5323 parameter c1_use_casc_in = "off";
5324 parameter c2_use_casc_in = "off";
5325 parameter c3_use_casc_in = "off";
5326 parameter c4_use_casc_in = "off";
5327 parameter c5_use_casc_in = "off";
5329 parameter m_test_source = 5;
5330 parameter c0_test_source = 5;
5331 parameter c1_test_source = 5;
5332 parameter c2_test_source = 5;
5333 parameter c3_test_source = 5;
5334 parameter c4_test_source = 5;
5335 parameter c5_test_source = 5;
5337 // LVDS mode parameters
5338 parameter enable0_counter = "c0";
5339 parameter enable1_counter = "c1";
5340 parameter sclkout0_phase_shift = "0";
5341 parameter sclkout1_phase_shift = "0";
5343 parameter vco_multiply_by = 0;
5344 parameter vco_divide_by = 0;
5345 parameter vco_post_scale = 1;
5347 parameter charge_pump_current = 0;
5348 parameter loop_filter_r = "1.0";
5349 parameter loop_filter_c = 1;
5351 parameter pll_compensation_delay = 0;
5352 parameter simulation_type = "functional";
5354 //parameter for stratixii lvds
5355 parameter clk0_phase_shift_num = 0;
5356 parameter clk1_phase_shift_num = 0;
5357 parameter clk2_phase_shift_num = 0;
5359 parameter clk0_use_even_counter_mode = "off";
5360 parameter clk1_use_even_counter_mode = "off";
5361 parameter clk2_use_even_counter_mode = "off";
5362 parameter clk3_use_even_counter_mode = "off";
5363 parameter clk4_use_even_counter_mode = "off";
5364 parameter clk5_use_even_counter_mode = "off";
5366 parameter clk0_use_even_counter_value = "off";
5367 parameter clk1_use_even_counter_value = "off";
5368 parameter clk2_use_even_counter_value = "off";
5369 parameter clk3_use_even_counter_value = "off";
5370 parameter clk4_use_even_counter_value = "off";
5371 parameter clk5_use_even_counter_value = "off";
5388 output [1:0] clkbad;
5394 // lvds specific output ports
5397 output [1:0] sclkout;
5414 buf (inclk0_ipd, inclk[0]);
5415 buf (inclk1_ipd, inclk[1]);
5417 buf (fbin_ipd, fbin);
5418 buf (clkswitch_ipd, clkswitch);
5419 buf (areset_ipd, areset);
5420 buf (pfdena_ipd, pfdena);
5421 buf (scanclk_ipd, scanclk);
5422 buf (scanread_ipd, scanread);
5423 buf (scanwrite_ipd, scanwrite);
5424 buf (scandata_ipd, scandata);
5427 // INTERNAL VARIABLES AND NETS
5428 integer scan_chain_length;
5436 integer egpp_offset;
5438 integer delay_chain;
5441 integer initial_delay;
5444 integer phase_shift[0:7];
5445 integer last_phase_shift[0:7];
5447 integer m_times_vco_period;
5448 integer new_m_times_vco_period;
5449 integer refclk_period;
5450 integer fbclk_period;
5456 integer tmp_vco_per;
5459 integer temp_offset;
5460 integer cycles_to_lock;
5461 integer cycles_to_unlock;
5463 integer c0_initial_count;
5465 integer c1_initial_count;
5466 integer loop_xplier;
5467 integer loop_initial;
5469 integer cycle_to_adjust;
5470 integer total_pull_back;
5471 integer pull_back_M;
5474 time first_fbclk_time;
5477 reg got_first_refclk;
5478 reg got_second_refclk;
5479 reg got_first_fbclk;
5480 reg refclk_last_value;
5481 reg fbclk_last_value;
5482 reg inclk_last_value;
5484 reg pll_about_to_lock;
5486 reg c0_got_first_rising_edge;
5487 reg c1_got_first_rising_edge;
5488 reg vco_c0_last_value;
5489 reg vco_c1_last_value;
5490 reg areset_ipd_last_value;
5491 reg ena_ipd_last_value;
5492 reg pfdena_ipd_last_value;
5493 reg inclk_out_of_range;
5494 reg schedule_vco_last_value;
5499 reg [31:0] m_initial_val;
5500 reg [31:0] m_val[0:1];
5501 reg [31:0] n_val[0:1];
5503 reg [8*6:1] m_mode_val[0:1];
5504 reg [8*6:1] n_mode_val[0:1];
5506 reg [31:0] c_high_val[0:5];
5507 reg [31:0] c_low_val[0:5];
5508 reg [8*6:1] c_mode_val[0:5];
5509 reg [31:0] c_initial_val[0:5];
5510 integer c_ph_val[0:5];
5512 // temporary registers for reprogramming
5513 integer c_ph_val_tmp[0:5];
5514 reg [31:0] c_high_val_tmp[0:5];
5515 reg [31:0] c_low_val_tmp[0:5];
5516 reg [8*6:1] c_mode_val_tmp[0:5];
5518 // hold registers for reprogramming
5519 integer c_ph_val_hold[0:5];
5520 reg [31:0] c_high_val_hold[0:5];
5521 reg [31:0] c_low_val_hold[0:5];
5522 reg [8*6:1] c_mode_val_hold[0:5];
5525 reg [31:0] m_val_old[0:1];
5526 reg [31:0] m_val_tmp[0:1];
5527 reg [31:0] n_val_old[0:1];
5528 reg [8*6:1] m_mode_val_old[0:1];
5529 reg [8*6:1] n_mode_val_old[0:1];
5530 reg [31:0] c_high_val_old[0:5];
5531 reg [31:0] c_low_val_old[0:5];
5532 reg [8*6:1] c_mode_val_old[0:5];
5533 integer c_ph_val_old[0:5];
5534 integer m_ph_val_old;
5535 integer m_ph_val_tmp;
5537 integer cp_curr_old;
5538 integer cp_curr_val;
5541 reg [9*8:1] lfr_val;
5542 reg [9*8:1] lfr_old;
5547 // ph tap orig values (POF)
5548 integer c_ph_val_orig[0:5];
5549 integer m_ph_val_orig;
5556 reg [7:0] vco_out_last_value;
5563 reg inclk_c0_from_vco;
5564 reg inclk_c1_from_vco;
5565 reg inclk_c2_from_vco;
5566 reg inclk_c3_from_vco;
5567 reg inclk_c4_from_vco;
5568 reg inclk_c5_from_vco;
5569 reg inclk_m_from_vco;
5570 reg inclk_sclkout0_from_vco;
5571 reg inclk_sclkout1_from_vco;
5613 reg vco_period_was_phase_adjusted;
5614 reg phase_adjust_was_scheduled;
5620 wire test_mode_inclk;
5622 // for external feedback mode
5624 reg [31:0] ext_fbk_cntr_high;
5625 reg [31:0] ext_fbk_cntr_low;
5626 reg [31:0] ext_fbk_cntr_modulus;
5627 reg [8*2:1] ext_fbk_cntr;
5628 reg [8*6:1] ext_fbk_cntr_mode;
5629 integer ext_fbk_cntr_ph;
5630 integer ext_fbk_cntr_initial;
5631 integer ext_fbk_cntr_index;
5633 // variables for clk_switch
5636 reg inclk0_last_value;
5637 reg inclk1_last_value;
5638 reg other_clock_value;
5639 reg other_clock_last_value;
5640 reg primary_clk_is_bad;
5641 reg current_clk_is_bad;
5642 reg external_switch;
5643 reg [8*6:1] current_clock;
5646 reg got_curr_clk_falling_edge_after_clkswitch;
5650 integer switch_over_count;
5652 wire scandataout_tmp;
5654 reg scandone_tmp_last_value;
5656 integer slowest_clk_old;
5657 integer slowest_clk_new;
5661 time scanclk_last_rising_edge;
5662 time scanread_active_edge;
5663 reg got_first_scanclk;
5664 reg got_first_gated_scanclk;
5666 integer scanclk_period;
5667 reg scanclk_last_value;
5670 reg scanwrite_enabled;
5671 reg scanwrite_last_value;
5672 reg [173:0] scan_data;
5673 reg [173:0] tmp_scan_data;
5674 reg c0_rising_edge_transfer_done;
5675 reg c1_rising_edge_transfer_done;
5676 reg c2_rising_edge_transfer_done;
5677 reg c3_rising_edge_transfer_done;
5678 reg c4_rising_edge_transfer_done;
5679 reg c5_rising_edge_transfer_done;
5680 reg scanread_setup_violation;
5682 integer scanclk_cycles;
5685 integer num_output_cntrs;
5688 // INTERNAL PARAMETERS
5689 parameter GPP_SCAN_CHAIN = 174;
5690 parameter FAST_SCAN_CHAIN = 75;
5691 // primary clk is always inclk0
5692 parameter primary_clock = "inclk0";
5694 // internal variables for scaling of multiply_by and divide_by values
5695 integer i_clk0_mult_by;
5696 integer i_clk0_div_by;
5697 integer i_clk1_mult_by;
5698 integer i_clk1_div_by;
5699 integer i_clk2_mult_by;
5700 integer i_clk2_div_by;
5701 integer i_clk3_mult_by;
5702 integer i_clk3_div_by;
5703 integer i_clk4_mult_by;
5704 integer i_clk4_div_by;
5705 integer i_clk5_mult_by;
5706 integer i_clk5_div_by;
5707 integer max_d_value;
5708 integer new_multiplier;
5710 // internal variables for storing the phase shift number.(used in lvds mode only)
5711 integer i_clk0_phase_shift;
5712 integer i_clk1_phase_shift;
5713 integer i_clk2_phase_shift;
5715 // user to advanced internal signals
5717 integer i_m_initial;
5723 integer i_c_high[0:5];
5724 integer i_c_low[0:5];
5725 integer i_c_initial[0:5];
5726 integer i_c_ph[0:5];
5727 reg [8*6:1] i_c_mode[0:5];
5731 integer i_vco_center;
5736 reg [8*2:1] i_clk5_counter;
5737 reg [8*2:1] i_clk4_counter;
5738 reg [8*2:1] i_clk3_counter;
5739 reg [8*2:1] i_clk2_counter;
5740 reg [8*2:1] i_clk1_counter;
5741 reg [8*2:1] i_clk0_counter;
5742 integer i_charge_pump_current;
5743 integer i_loop_filter_r;
5744 integer max_neg_abs;
5745 integer output_count;
5746 integer new_divisor;
5748 integer loop_filter_c_arr[0:3];
5749 integer fpll_loop_filter_c_arr[0:3];
5750 integer charge_pump_curr_arr[0:15];
5751 reg [9*8:1] loop_filter_r_arr[0:39];
5753 reg pll_in_test_mode;
5754 reg pll_is_in_reset;
5756 // uppercase to lowercase parameter values
5757 reg [8*`WORD_LENGTH:1] l_operation_mode;
5758 reg [8*`WORD_LENGTH:1] l_pll_type;
5759 reg [8*`WORD_LENGTH:1] l_qualify_conf_done;
5760 reg [8*`WORD_LENGTH:1] l_compensate_clock;
5761 reg [8*`WORD_LENGTH:1] l_scan_chain;
5762 reg [8*`WORD_LENGTH:1] l_primary_clock;
5763 reg [8*`WORD_LENGTH:1] l_gate_lock_signal;
5764 reg [8*`WORD_LENGTH:1] l_switch_over_on_lossclk;
5765 reg [8*`WORD_LENGTH:1] l_switch_over_type;
5766 reg [8*`WORD_LENGTH:1] l_switch_over_on_gated_lock;
5767 reg [8*`WORD_LENGTH:1] l_enable_switch_over_counter;
5768 reg [8*`WORD_LENGTH:1] l_feedback_source;
5769 reg [8*`WORD_LENGTH:1] l_bandwidth_type;
5770 reg [8*`WORD_LENGTH:1] l_simulation_type;
5771 reg [8*`WORD_LENGTH:1] l_enable0_counter;
5772 reg [8*`WORD_LENGTH:1] l_enable1_counter;
5777 // finds the closest integer fraction of a given pair of numerator and denominator.
5778 task find_simple_integer_fraction;
5782 output fraction_num;
5783 output fraction_div;
5784 parameter max_iter = 20;
5787 integer denominator;
5789 integer fraction_num;
5790 integer fraction_div;
5792 integer quotient_array[max_iter-1:0];
5793 integer int_loop_iter;
5797 integer old_m_value;
5809 i_max_iter = max_iter;
5811 while (loop_iter < i_max_iter)
5813 int_quot = num / den;
5814 quotient_array[loop_iter] = int_quot;
5815 num = num - (den*int_quot);
5816 loop_iter=loop_iter+1;
5818 if ((num == 0) || (max_denom != -1) || (loop_iter == i_max_iter))
5820 // calculate the numerator and denominator if there is a restriction on the
5821 // max denom value or if the loop is ending
5824 // get the rounded value at this stage for the remaining fraction
5827 m_value = (2*num/den);
5829 // calculate the fraction numerator and denominator at this stage
5830 for (int_loop_iter = loop_iter-1; int_loop_iter >= 0; int_loop_iter=int_loop_iter-1)
5834 m_value = quotient_array[int_loop_iter];
5839 old_m_value = m_value;
5840 m_value = quotient_array[int_loop_iter]*m_value + d_value;
5841 d_value = old_m_value;
5844 // if the denominator is less than the maximum denom_value or if there is no restriction save it
5845 if ((d_value <= max_denom) || (max_denom == -1))
5847 fraction_num = m_value;
5848 fraction_div = d_value;
5850 // end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
5851 if (((d_value > max_denom) && (max_denom != -1)) || (num == 0))
5853 i_max_iter = loop_iter;
5856 // swap the numerator and denominator for the next round
5862 endtask // find_simple_integer_fraction
5864 // get the absolute value
5865 function integer abs;
5875 // find twice the period of the slowest clock
5876 function integer slowest_clk;
5877 input C0, C0_mode, C1, C1_mode, C2, C2_mode, C3, C3_mode, C4, C4_mode, C5, C5_mode, refclk, m_mod;
5878 integer C0, C1, C2, C3, C4, C5;
5879 reg [8*6:1] C0_mode, C1_mode, C2_mode, C3_mode, C4_mode, C5_mode;
5882 integer max_modulus;
5885 if (C0_mode != "bypass" && C0_mode != " off")
5887 if (C1 > max_modulus && C1_mode != "bypass" && C1_mode != " off")
5889 if (C2 > max_modulus && C2_mode != "bypass" && C2_mode != " off")
5891 if (C3 > max_modulus && C3_mode != "bypass" && C3_mode != " off")
5893 if (C4 > max_modulus && C4_mode != "bypass" && C4_mode != " off")
5895 if (C5 > max_modulus && C5_mode != "bypass" && C5_mode != " off")
5898 slowest_clk = (refclk * max_modulus *2 / m_mod);
5902 // count the number of digits in the given integer
5903 function integer count_digit;
5906 integer count, result;
5912 result = (result / 10);
5916 count_digit = count;
5920 // reduce the given huge number(X) to Y significant digits
5921 function integer scale_num;
5925 integer fac_ten, lc;
5928 count = count_digit(X);
5930 for (lc = 0; lc < (count-Y); lc = lc + 1)
5931 fac_ten = fac_ten * 10;
5933 scale_num = (X / fac_ten);
5937 // find the greatest common denominator of X and Y
5938 function integer gcd;
5943 if (X < Y) // find which is smaller.
5959 R = S % L; // divide bigger number by smaller.
5960 // remainder becomes smaller number.
5962 if (R == 0) // if evenly divisible then L is gcd else it is 1.
5970 // find the least common multiple of A1 to A10
5971 function integer lcm;
5972 input A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
5973 integer A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
5974 integer M1, M2, M3, M4, M5 , M6, M7, M8, M9, R;
5976 M1 = (A1 * A2)/gcd(A1, A2);
5977 M2 = (M1 * A3)/gcd(M1, A3);
5978 M3 = (M2 * A4)/gcd(M2, A4);
5979 M4 = (M3 * A5)/gcd(M3, A5);
5980 M5 = (M4 * A6)/gcd(M4, A6);
5981 M6 = (M5 * A7)/gcd(M5, A7);
5982 M7 = (M6 * A8)/gcd(M6, A8);
5983 M8 = (M7 * A9)/gcd(M7, A9);
5984 M9 = (M8 * A10)/gcd(M8, A10);
5987 else if ((M9 <= 10) && (M9 >= 3))
5990 R = scale_num(M9, 3);
5997 // find the factor of division of the output clock frequency
5998 // compared to the VCO
5999 function integer output_counter_value;
6000 input clk_divide, clk_mult, M, N;
6001 integer clk_divide, clk_mult, M, N;
6004 R = (clk_divide * M)/(clk_mult * N);
6005 output_counter_value = R;
6009 // find the mode of each of the PLL counters - bypass, even or odd
6010 function [8*6:1] counter_mode;
6012 input output_counter_value;
6014 integer output_counter_value;
6015 integer half_cycle_high;
6018 half_cycle_high = (2*duty_cycle*output_counter_value)/100;
6019 if (output_counter_value == 1)
6021 else if ((half_cycle_high % 2) == 0)
6029 // find the number of VCO clock cycles to hold the output clock high
6030 function integer counter_high;
6031 input output_counter_value, duty_cycle;
6032 integer output_counter_value, duty_cycle;
6033 integer half_cycle_high;
6034 integer tmp_counter_high;
6037 half_cycle_high = (2*duty_cycle*output_counter_value)/100;
6038 mode = ((half_cycle_high % 2) == 0);
6039 tmp_counter_high = half_cycle_high/2;
6040 counter_high = tmp_counter_high + !mode;
6044 // find the number of VCO clock cycles to hold the output clock low
6045 function integer counter_low;
6046 input output_counter_value, duty_cycle;
6047 integer output_counter_value, duty_cycle, counter_h;
6048 integer half_cycle_high;
6050 integer tmp_counter_high;
6052 half_cycle_high = (2*duty_cycle*output_counter_value)/100;
6053 mode = ((half_cycle_high % 2) == 0);
6054 tmp_counter_high = half_cycle_high/2;
6055 counter_h = tmp_counter_high + !mode;
6056 counter_low = output_counter_value - counter_h;
6060 // find the smallest time delay amongst t1 to t10
6061 function integer mintimedelay;
6062 input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
6063 integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
6064 integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
6109 // find the numerically largest negative number, and return its absolute value
6110 function integer maxnegabs;
6111 input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
6112 integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
6113 integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
6115 if (t1 < t2) m1 = t1; else m1 = t2;
6116 if (m1 < t3) m2 = m1; else m2 = t3;
6117 if (m2 < t4) m3 = m2; else m3 = t4;
6118 if (m3 < t5) m4 = m3; else m4 = t5;
6119 if (m4 < t6) m5 = m4; else m5 = t6;
6120 if (m5 < t7) m6 = m5; else m6 = t7;
6121 if (m6 < t8) m7 = m6; else m7 = t8;
6122 if (m7 < t9) m8 = m7; else m8 = t9;
6123 if (m8 < t10) m9 = m8; else m9 = t10;
6124 maxnegabs = (m9 < 0) ? 0 - m9 : 0;
6128 // adjust the given tap_phase by adding the largest negative number (ph_base)
6129 function integer ph_adjust;
6130 input tap_phase, ph_base;
6131 integer tap_phase, ph_base;
6133 ph_adjust = tap_phase + ph_base;
6137 // find the number of VCO clock cycles to wait initially before the first
6138 // rising edge of the output clock
6139 function integer counter_initial;
6140 input tap_phase, m, n;
6141 integer tap_phase, m, n, phase;
6143 if (tap_phase < 0) tap_phase = 0 - tap_phase;
6144 // adding 0.5 for rounding correction (required in order to round
6145 // to the nearest integer instead of truncating)
6146 phase = ((tap_phase * m) / (360 * n)) + 0.5;
6147 counter_initial = phase;
6151 // find which VCO phase tap to align the rising edge of the output clock to
6152 function integer counter_ph;
6158 // adding 0.5 for rounding correction
6159 phase = (tap_phase * m / n) + 0.5;
6160 counter_ph = (phase % 360)/45;
6164 // convert the given string to length 6 by padding with spaces
6165 function [8*6:1] translate_string;
6167 reg [8*6:1] new_mode;
6169 if (mode == "bypass")
6170 new_mode = "bypass";
6171 else if (mode == "even")
6173 else if (mode == "odd")
6176 translate_string = new_mode;
6180 // convert string to integer with sign
6181 function integer str2int;
6187 integer m, magnitude;
6194 for (m=1; m<=16; m=m+1)
6196 tmp = reg_s[128:121];
6197 digit = tmp & 8'b00001111;
6199 // Accumulate ascii digits 0-9 only.
6200 if ((tmp>=48) && (tmp<=57))
6201 magnitude = (magnitude * 10) + digit;
6203 sign = -1; // Found a '-' character, i.e. number is negative.
6205 str2int = sign*magnitude;
6209 // this is for stratixii lvds only
6210 // convert phase delay to integer
6211 function integer get_int_phase_shift;
6213 input i_phase_shift;
6214 integer i_phase_shift;
6217 if (i_phase_shift != 0)
6219 get_int_phase_shift = i_phase_shift;
6223 get_int_phase_shift = str2int(s);
6228 // calculate the given phase shift (in ps) in terms of degrees
6229 function integer get_phase_degree;
6231 integer phase_shift, result;
6233 result = (phase_shift * 360) / inclk0_input_frequency;
6234 // this is to round up the calculation result
6236 result = result + 1;
6237 else if ( result < 0 )
6238 result = result - 1;
6242 // assign the rounded up result
6243 get_phase_degree = result;
6247 // convert uppercase parameter values to lowercase
6248 // assumes that the maximum character length of a parameter is 18
6249 function [8*`WORD_LENGTH:1] alpha_tolower;
6250 input [8*`WORD_LENGTH:1] given_string;
6252 reg [8*`WORD_LENGTH:1] return_string;
6253 reg [8*`WORD_LENGTH:1] reg_string;
6255 reg [8:1] conv_char;
6258 return_string = " "; // initialise strings to spaces
6260 reg_string = given_string;
6261 for (byte_count = `WORD_LENGTH; byte_count >= 1; byte_count = byte_count - 1)
6263 tmp = reg_string[8*`WORD_LENGTH:(8*(`WORD_LENGTH-1)+1)];
6264 reg_string = reg_string << 8;
6265 if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90
6267 conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set
6268 return_string = {return_string, conv_char};
6271 return_string = {return_string, tmp};
6274 alpha_tolower = return_string;
6278 function integer display_msg;
6279 input [8*2:1] cntr_name;
6284 $display ("Warning : %s counter switched from BYPASS mode to enabled. PLL may lose lock.", cntr_name);
6285 else if (msg_code == 2)
6286 $display ("Warning : Illegal 1 value for %s counter. Instead, the %s counter should be BYPASSED. Reconfiguration may not work.", cntr_name, cntr_name);
6287 else if (msg_code == 3)
6288 $display ("Warning : Illegal value for counter %s in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.", cntr_name);
6289 else if (msg_code == 4)
6290 $display ("Warning : %s counter switched from enabled to BYPASS mode. PLL may lose lock.", cntr_name);
6299 // convert string parameter values from uppercase to lowercase,
6300 // as expected in this model
6301 l_operation_mode = alpha_tolower(operation_mode);
6302 l_pll_type = alpha_tolower(pll_type);
6303 l_qualify_conf_done = alpha_tolower(qualify_conf_done);
6304 l_compensate_clock = alpha_tolower(compensate_clock);
6305 l_primary_clock = alpha_tolower(primary_clock);
6306 l_gate_lock_signal = alpha_tolower(gate_lock_signal);
6307 l_switch_over_on_lossclk = alpha_tolower(switch_over_on_lossclk);
6308 l_switch_over_on_gated_lock = alpha_tolower(switch_over_on_gated_lock);
6309 l_enable_switch_over_counter = alpha_tolower(enable_switch_over_counter);
6310 l_switch_over_type = alpha_tolower(switch_over_type);
6311 l_feedback_source = alpha_tolower(feedback_source);
6312 l_bandwidth_type = alpha_tolower(bandwidth_type);
6313 l_simulation_type = alpha_tolower(simulation_type);
6314 l_enable0_counter = alpha_tolower(enable0_counter);
6315 l_enable1_counter = alpha_tolower(enable1_counter);
6317 // initialize charge_pump_current, and loop_filter tables
6318 loop_filter_c_arr[0] = 57;
6319 loop_filter_c_arr[1] = 16;
6320 loop_filter_c_arr[2] = 36;
6321 loop_filter_c_arr[3] = 5;
6323 fpll_loop_filter_c_arr[0] = 18;
6324 fpll_loop_filter_c_arr[1] = 13;
6325 fpll_loop_filter_c_arr[2] = 8;
6326 fpll_loop_filter_c_arr[3] = 2;
6328 charge_pump_curr_arr[0] = 6;
6329 charge_pump_curr_arr[1] = 12;
6330 charge_pump_curr_arr[2] = 30;
6331 charge_pump_curr_arr[3] = 36;
6332 charge_pump_curr_arr[4] = 52;
6333 charge_pump_curr_arr[5] = 57;
6334 charge_pump_curr_arr[6] = 72;
6335 charge_pump_curr_arr[7] = 77;
6336 charge_pump_curr_arr[8] = 92;
6337 charge_pump_curr_arr[9] = 96;
6338 charge_pump_curr_arr[10] = 110;
6339 charge_pump_curr_arr[11] = 114;
6340 charge_pump_curr_arr[12] = 127;
6341 charge_pump_curr_arr[13] = 131;
6342 charge_pump_curr_arr[14] = 144;
6343 charge_pump_curr_arr[15] = 148;
6345 loop_filter_r_arr[0] = " 1.000000";
6346 loop_filter_r_arr[1] = " 1.500000";
6347 loop_filter_r_arr[2] = " 2.000000";
6348 loop_filter_r_arr[3] = " 2.500000";
6349 loop_filter_r_arr[4] = " 3.000000";
6350 loop_filter_r_arr[5] = " 3.500000";
6351 loop_filter_r_arr[6] = " 4.000000";
6352 loop_filter_r_arr[7] = " 4.500000";
6353 loop_filter_r_arr[8] = " 5.000000";
6354 loop_filter_r_arr[9] = " 5.500000";
6355 loop_filter_r_arr[10] = " 6.000000";
6356 loop_filter_r_arr[11] = " 6.500000";
6357 loop_filter_r_arr[12] = " 7.000000";
6358 loop_filter_r_arr[13] = " 7.500000";
6359 loop_filter_r_arr[14] = " 8.000000";
6360 loop_filter_r_arr[15] = " 8.500000";
6361 loop_filter_r_arr[16] = " 9.000000";
6362 loop_filter_r_arr[17] = " 9.500000";
6363 loop_filter_r_arr[18] = "10.000000";
6364 loop_filter_r_arr[19] = "10.500000";
6365 loop_filter_r_arr[20] = "11.000000";
6366 loop_filter_r_arr[21] = "11.500000";
6367 loop_filter_r_arr[22] = "12.000000";
6368 loop_filter_r_arr[23] = "12.500000";
6369 loop_filter_r_arr[24] = "13.000000";
6370 loop_filter_r_arr[25] = "13.500000";
6371 loop_filter_r_arr[26] = "14.000000";
6372 loop_filter_r_arr[27] = "14.500000";
6373 loop_filter_r_arr[28] = "15.000000";
6374 loop_filter_r_arr[29] = "15.500000";
6375 loop_filter_r_arr[30] = "16.000000";
6376 loop_filter_r_arr[31] = "16.500000";
6377 loop_filter_r_arr[32] = "17.000000";
6378 loop_filter_r_arr[33] = "17.500000";
6379 loop_filter_r_arr[34] = "18.000000";
6380 loop_filter_r_arr[35] = "18.500000";
6381 loop_filter_r_arr[36] = "19.000000";
6382 loop_filter_r_arr[37] = "19.500000";
6383 loop_filter_r_arr[38] = "20.000000";
6384 loop_filter_r_arr[39] = "20.500000";
6388 i_clk5_counter = "c5" ;
6389 i_clk4_counter = "c4" ;
6390 i_clk3_counter = "c3" ;
6391 i_clk2_counter = "c2" ;
6392 i_clk1_counter = "c1" ;
6393 i_clk0_counter = "c0" ;
6396 i_clk5_counter = alpha_tolower(clk5_counter);
6397 i_clk4_counter = alpha_tolower(clk4_counter);
6398 i_clk3_counter = alpha_tolower(clk3_counter);
6399 i_clk2_counter = alpha_tolower(clk2_counter);
6400 i_clk1_counter = alpha_tolower(clk1_counter);
6401 i_clk0_counter = alpha_tolower(clk0_counter);
6404 // VCO feedback loop settings for external feedback mode
6405 // first find which counter is used for feedback
6406 if (l_operation_mode == "external_feedback")
6408 if (l_feedback_source == "clk0")
6409 ext_fbk_cntr = i_clk0_counter;
6410 else if (l_feedback_source == "clk1")
6411 ext_fbk_cntr = i_clk1_counter;
6412 else if (l_feedback_source == "clk2")
6413 ext_fbk_cntr = i_clk2_counter;
6414 else if (l_feedback_source == "clk3")
6415 ext_fbk_cntr = i_clk3_counter;
6416 else if (l_feedback_source == "clk4")
6417 ext_fbk_cntr = i_clk4_counter;
6418 else if (l_feedback_source == "clk5")
6419 ext_fbk_cntr = i_clk5_counter;
6420 else ext_fbk_cntr = "c0";
6422 if (ext_fbk_cntr == "c0")
6423 ext_fbk_cntr_index = 0;
6424 else if (ext_fbk_cntr == "c1")
6425 ext_fbk_cntr_index = 1;
6426 else if (ext_fbk_cntr == "c2")
6427 ext_fbk_cntr_index = 2;
6428 else if (ext_fbk_cntr == "c3")
6429 ext_fbk_cntr_index = 3;
6430 else if (ext_fbk_cntr == "c4")
6431 ext_fbk_cntr_index = 4;
6432 else if (ext_fbk_cntr == "c5")
6433 ext_fbk_cntr_index = 5;
6439 // set the limit of the divide_by value that can be returned by
6440 // the following function.
6443 // scale down the multiply_by and divide_by values provided by the design
6444 // before attempting to use them in the calculations below
6445 find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
6446 max_d_value, i_clk0_mult_by, i_clk0_div_by);
6447 find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
6448 max_d_value, i_clk1_mult_by, i_clk1_div_by);
6449 find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
6450 max_d_value, i_clk2_mult_by, i_clk2_div_by);
6451 find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
6452 max_d_value, i_clk3_mult_by, i_clk3_div_by);
6453 find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
6454 max_d_value, i_clk4_mult_by, i_clk4_div_by);
6455 find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
6456 max_d_value, i_clk5_mult_by, i_clk5_div_by);
6458 // convert user parameters to advanced
6459 if (((l_pll_type == "fast") || (l_pll_type == "lvds")) && (vco_multiply_by != 0) && (vco_divide_by != 0))
6461 i_n = vco_divide_by;
6462 i_m = vco_multiply_by;
6466 i_m = lcm (i_clk0_mult_by, i_clk1_mult_by,
6467 i_clk2_mult_by, i_clk3_mult_by,
6468 i_clk4_mult_by, i_clk5_mult_by,
6469 1, 1, 1, 1, inclk0_input_frequency);
6472 i_c_high[0] = counter_high (output_counter_value(i_clk0_div_by,
6473 i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
6474 i_c_high[1] = counter_high (output_counter_value(i_clk1_div_by,
6475 i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
6476 i_c_high[2] = counter_high (output_counter_value(i_clk2_div_by,
6477 i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
6478 i_c_high[3] = counter_high (output_counter_value(i_clk3_div_by,
6479 i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
6480 i_c_high[4] = counter_high (output_counter_value(i_clk4_div_by,
6481 i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
6482 i_c_high[5] = counter_high (output_counter_value(i_clk5_div_by,
6483 i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
6485 i_c_low[0] = counter_low (output_counter_value(i_clk0_div_by,
6486 i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
6487 i_c_low[1] = counter_low (output_counter_value(i_clk1_div_by,
6488 i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
6489 i_c_low[2] = counter_low (output_counter_value(i_clk2_div_by,
6490 i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
6491 i_c_low[3] = counter_low (output_counter_value(i_clk3_div_by,
6492 i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
6493 i_c_low[4] = counter_low (output_counter_value(i_clk4_div_by,
6494 i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
6495 i_c_low[5] = counter_low (output_counter_value(i_clk5_div_by,
6496 i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
6498 if (l_pll_type == "flvds")
6500 // Need to readjust phase shift values when the clock multiply value has been readjusted.
6501 new_multiplier = clk0_multiply_by / i_clk0_mult_by;
6502 i_clk0_phase_shift = (clk0_phase_shift_num * new_multiplier);
6503 i_clk1_phase_shift = (clk1_phase_shift_num * new_multiplier);
6504 i_clk2_phase_shift = (clk2_phase_shift_num * new_multiplier);
6508 i_clk0_phase_shift = get_int_phase_shift(clk0_phase_shift, clk0_phase_shift_num);
6509 i_clk1_phase_shift = get_int_phase_shift(clk1_phase_shift, clk1_phase_shift_num);
6510 i_clk2_phase_shift = get_int_phase_shift(clk2_phase_shift, clk2_phase_shift_num);
6513 max_neg_abs = maxnegabs ( i_clk0_phase_shift,
6516 str2int(clk3_phase_shift),
6517 str2int(clk4_phase_shift),
6518 str2int(clk5_phase_shift),
6521 i_c_initial[0] = counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
6522 i_c_initial[1] = counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
6523 i_c_initial[2] = counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
6524 i_c_initial[3] = counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs)), i_m, i_n);
6525 i_c_initial[4] = counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs)), i_m, i_n);
6526 i_c_initial[5] = counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs)), i_m, i_n);
6528 i_c_mode[0] = counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
6529 i_c_mode[1] = counter_mode(clk1_duty_cycle,output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
6530 i_c_mode[2] = counter_mode(clk2_duty_cycle,output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
6531 i_c_mode[3] = counter_mode(clk3_duty_cycle,output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
6532 i_c_mode[4] = counter_mode(clk4_duty_cycle,output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
6533 i_c_mode[5] = counter_mode(clk5_duty_cycle,output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
6535 i_m_ph = counter_ph(get_phase_degree(max_neg_abs), i_m, i_n);
6536 i_m_initial = counter_initial(get_phase_degree(max_neg_abs), i_m, i_n);
6538 i_c_ph[0] = counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
6539 i_c_ph[1] = counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
6540 i_c_ph[2] = counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
6541 i_c_ph[3] = counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs)), i_m, i_n);
6542 i_c_ph[4] = counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs)), i_m, i_n);
6543 i_c_ph[5] = counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs)), i_m, i_n);
6545 // in external feedback mode, need to adjust M value to take
6546 // into consideration the external feedback counter value
6547 if (l_operation_mode == "external_feedback")
6549 // if there is a negative phase shift, m_initial can only be 1
6550 if (max_neg_abs > 0)
6553 if (i_c_mode[ext_fbk_cntr_index] == "bypass")
6556 output_count = i_c_high[ext_fbk_cntr_index] + i_c_low[ext_fbk_cntr_index];
6558 if (i_m > output_count)
6559 i_m = i_m / output_count;
6562 new_divisor = gcd(i_m, output_count);
6563 i_m = i_m / new_divisor;
6564 i_n = output_count / new_divisor;
6574 i_c_high[0] = c0_high;
6575 i_c_high[1] = c1_high;
6576 i_c_high[2] = c2_high;
6577 i_c_high[3] = c3_high;
6578 i_c_high[4] = c4_high;
6579 i_c_high[5] = c5_high;
6580 i_c_low[0] = c0_low;
6581 i_c_low[1] = c1_low;
6582 i_c_low[2] = c2_low;
6583 i_c_low[3] = c3_low;
6584 i_c_low[4] = c4_low;
6585 i_c_low[5] = c5_low;
6586 i_c_initial[0] = c0_initial;
6587 i_c_initial[1] = c1_initial;
6588 i_c_initial[2] = c2_initial;
6589 i_c_initial[3] = c3_initial;
6590 i_c_initial[4] = c4_initial;
6591 i_c_initial[5] = c5_initial;
6592 i_c_mode[0] = translate_string(alpha_tolower(c0_mode));
6593 i_c_mode[1] = translate_string(alpha_tolower(c1_mode));
6594 i_c_mode[2] = translate_string(alpha_tolower(c2_mode));
6595 i_c_mode[3] = translate_string(alpha_tolower(c3_mode));
6596 i_c_mode[4] = translate_string(alpha_tolower(c4_mode));
6597 i_c_mode[5] = translate_string(alpha_tolower(c5_mode));
6604 i_m_ph = m_ph; // default
6605 i_m_initial = m_initial;
6607 end // user to advanced conversion
6609 refclk_period = inclk0_input_frequency * i_n;
6611 m_times_vco_period = refclk_period;
6612 new_m_times_vco_period = refclk_period;
6618 vco_out[7:0] = 8'b0;
6619 fbclk_last_value = 0;
6622 got_first_refclk = 0;
6623 got_first_fbclk = 0;
6625 first_fbclk_time = 0;
6630 c0_got_first_rising_edge = 0;
6631 c1_got_first_rising_edge = 0;
6632 vco_c0_last_value = 0;
6634 c0_initial_count = 1;
6636 c1_initial_count = 1;
6643 for (i = 0; i <= 7; i = i + 1)
6646 last_phase_shift[i] = 0;
6650 cycle_to_adjust = 0;
6654 total_pull_back = 0;
6656 vco_period_was_phase_adjusted = 0;
6657 phase_adjust_was_scheduled = 0;
6658 ena_ipd_last_value = 0;
6659 inclk_out_of_range = 0;
6661 schedule_vco_last_value = 0;
6663 // set initial values for counter parameters
6664 m_initial_val = i_m_initial;
6668 m_ph_val_orig = i_m_ph;
6669 m_ph_val_tmp = i_m_ph;
6676 m_mode_val[0] = "bypass";
6677 else m_mode_val[0] = "";
6679 m_mode_val[1] = "bypass";
6681 n_mode_val[0] = "bypass";
6683 n_mode_val[1] = "bypass";
6685 for (i = 0; i < 6; i=i+1)
6687 c_high_val[i] = i_c_high[i];
6688 c_low_val[i] = i_c_low[i];
6689 c_initial_val[i] = i_c_initial[i];
6690 c_mode_val[i] = i_c_mode[i];
6691 c_ph_val[i] = i_c_ph[i];
6692 c_high_val_tmp[i] = i_c_high[i];
6693 c_low_val_tmp[i] = i_c_low[i];
6694 if (c_mode_val[i] == "bypass")
6696 if (l_pll_type == "fast" || l_pll_type == "lvds")
6698 c_high_val[i] = 5'b10000;
6699 c_low_val[i] = 5'b10000;
6700 c_high_val_tmp[i] = 5'b10000;
6701 c_low_val_tmp[i] = 5'b10000;
6704 c_high_val[i] = 9'b100000000;
6705 c_low_val[i] = 9'b100000000;
6706 c_high_val_tmp[i] = 9'b100000000;
6707 c_low_val_tmp[i] = 9'b100000000;
6711 c_mode_val_tmp[i] = i_c_mode[i];
6712 c_ph_val_tmp[i] = i_c_ph[i];
6714 c_ph_val_orig[i] = i_c_ph[i];
6715 c_high_val_hold[i] = i_c_high[i];
6716 c_low_val_hold[i] = i_c_low[i];
6717 c_mode_val_hold[i] = i_c_mode[i];
6720 lfc_val = loop_filter_c;
6721 lfr_val = loop_filter_r;
6722 cp_curr_val = charge_pump_current;
6726 inclk_last_value = 0;
6728 ext_fbk_cntr_ph = 0;
6729 ext_fbk_cntr_initial = 1;
6731 // initialize clkswitch variables
6735 inclk0_last_value = 0;
6736 inclk1_last_value = 0;
6737 other_clock_value = 0;
6738 other_clock_last_value = 0;
6739 primary_clk_is_bad = 0;
6740 current_clk_is_bad = 0;
6741 external_switch = 0;
6742 current_clock = l_primary_clock;
6743 active_clock = 0; // primary_clk is always inclk0
6744 if (l_pll_type == "fast")
6745 l_switch_over_type = "manual";
6747 if (l_switch_over_type == "manual" && clkswitch_ipd === 1'b1)
6749 current_clock = "inclk1";
6753 got_curr_clk_falling_edge_after_clkswitch = 0;
6756 switch_over_count = 0;
6758 // initialize reconfiguration variables
6760 quiet_time = slowest_clk ( c_high_val[0]+c_low_val[0], c_mode_val[0],
6761 c_high_val[1]+c_low_val[1], c_mode_val[1],
6762 c_high_val[2]+c_low_val[2], c_mode_val[2],
6763 c_high_val[3]+c_low_val[3], c_mode_val[3],
6764 c_high_val[4]+c_low_val[4], c_mode_val[4],
6765 c_high_val[5]+c_low_val[5], c_mode_val[5],
6766 refclk_period, m_val[0]);
6769 scanread_active_edge = 0;
6770 if ((l_pll_type == "fast") || (l_pll_type == "lvds"))
6772 scan_chain_length = FAST_SCAN_CHAIN;
6773 num_output_cntrs = 4;
6777 scan_chain_length = GPP_SCAN_CHAIN;
6778 num_output_cntrs = 6;
6782 scanwrite_enabled = 0;
6783 c0_rising_edge_transfer_done = 0;
6784 c1_rising_edge_transfer_done = 0;
6785 c2_rising_edge_transfer_done = 0;
6786 c3_rising_edge_transfer_done = 0;
6787 c4_rising_edge_transfer_done = 0;
6788 c5_rising_edge_transfer_done = 0;
6789 got_first_scanclk = 0;
6790 got_first_gated_scanclk = 0;
6792 scanread_setup_violation = 0;
6795 // initialize the scan_chain contents
6797 scan_data[11:0] = 12'b0;
6798 for (i = 0; i <= 3; i = i + 1)
6800 if ((l_pll_type == "fast") || (l_pll_type == "lvds"))
6802 if (fpll_loop_filter_c_arr[i] == loop_filter_c)
6803 scan_data[11:10] = i;
6806 if (loop_filter_c_arr[i] == loop_filter_c)
6807 scan_data[11:10] = i;
6810 for (i = 0; i <= 15; i = i + 1)
6812 if (charge_pump_curr_arr[i] == charge_pump_current)
6815 for (i = 0; i <= 39; i = i + 1)
6817 if (loop_filter_r_arr[i] == loop_filter_r)
6819 if ((i >= 16) && (i <= 23))
6820 scan_data[9:4] = i+8;
6821 else if ((i >= 24) && (i <= 31))
6822 scan_data[9:4] = i+16;
6824 scan_data[9:4] = i+24;
6830 if (l_pll_type == "fast" || l_pll_type == "lvds")
6832 scan_data[21:12] = 10'b0; // M, C3-C0 ph
6834 scan_data[25:22] = c_high_val[0];
6835 scan_data[35:32] = c_high_val[1];
6836 scan_data[45:42] = c_high_val[2];
6837 scan_data[55:52] = c_high_val[3];
6839 scan_data[30:27] = c_low_val[0];
6840 scan_data[40:37] = c_low_val[1];
6841 scan_data[50:47] = c_low_val[2];
6842 scan_data[60:57] = c_low_val[3];
6844 for (i = 0; i < 4; i = i + 1)
6846 if (c_mode_val[i] == " off" || c_mode_val[i] == "bypass")
6848 scan_data[26 + (10*i)] = 1;
6849 if (c_mode_val[i] == " off")
6850 scan_data[31 + (10*i)] = 1;
6852 scan_data[31 + (10*i)] = 0;
6855 scan_data[26 + (10*i)] = 0;
6856 if (c_mode_val[i] == " odd")
6857 scan_data[31 + (10*i)] = 1;
6859 scan_data[31 + (10*i)] = 0;
6863 if (m_mode_val[0] == "bypass")
6867 scan_data[65:62] = 4'b0;
6868 scan_data[70:67] = 4'b0;
6871 scan_data[66] = 0; // set BYPASS bit to 0
6872 scan_data[70:67] = m_val[0]/2; // set M low
6873 if (m_val[0] % 2 == 0)
6875 // M is an even no. : set M high = low,
6876 // set odd/even bit to 0
6877 scan_data[65:62] = scan_data[70:67];
6880 else begin // M is odd : M high = low + 1
6881 scan_data[65:62] = (m_val[0]/2) + 1;
6886 scan_data[73:72] = n_val[0];
6887 if (n_mode_val[0] == "bypass")
6890 scan_data[73:72] = 2'b0;
6893 else begin // PLL type is enhanced/auto
6894 scan_data[25:12] = 14'b0;
6897 scan_data[33:26] = c_high_val[5];
6898 scan_data[51:44] = c_high_val[4];
6899 scan_data[69:62] = c_high_val[3];
6900 scan_data[87:80] = c_high_val[2];
6901 scan_data[105:98] = c_high_val[1];
6902 scan_data[123:116] = c_high_val[0];
6904 scan_data[42:35] = c_low_val[5];
6905 scan_data[60:53] = c_low_val[4];
6906 scan_data[78:71] = c_low_val[3];
6907 scan_data[96:89] = c_low_val[2];
6908 scan_data[114:107] = c_low_val[1];
6909 scan_data[132:125] = c_low_val[0];
6911 for (i = 5; i >= 0; i = i - 1)
6913 if (c_mode_val[i] == " off" || c_mode_val[i] == "bypass")
6915 scan_data[124 - (18*i)] = 1;
6916 if (c_mode_val[i] == " off")
6917 scan_data[133 - (18*i)] = 1;
6919 scan_data[133 - (18*i)] = 0;
6922 scan_data[124 - (18*i)] = 0;
6923 if (c_mode_val[i] == " odd")
6924 scan_data[133 - (18*i)] = 1;
6926 scan_data[133 - (18*i)] = 0;
6930 scan_data[142:134] = m_val[0];
6932 scan_data[152:144] = m_val[1];
6934 if (m_mode_val[0] == "bypass")
6937 scan_data[142:134] = 9'b0;
6939 if (m_mode_val[1] == "bypass")
6942 scan_data[152:144] = 9'b0;
6945 scan_data[162:154] = n_val[0];
6946 scan_data[172:164] = n_val[1];
6947 if (n_mode_val[0] == "bypass")
6950 scan_data[162:154] = 9'b0;
6952 if (n_mode_val[1] == "bypass")
6955 scan_data[172:164] = 9'b0;
6959 // now save this counter's parameters
6960 ext_fbk_cntr_high = c_high_val[ext_fbk_cntr_index];
6961 ext_fbk_cntr_low = c_low_val[ext_fbk_cntr_index];
6962 ext_fbk_cntr_ph = c_ph_val[ext_fbk_cntr_index];
6963 ext_fbk_cntr_initial = c_initial_val[ext_fbk_cntr_index];
6964 ext_fbk_cntr_mode = c_mode_val[ext_fbk_cntr_index];
6966 if (ext_fbk_cntr_mode == "bypass")
6967 ext_fbk_cntr_modulus = 1;
6969 ext_fbk_cntr_modulus = ext_fbk_cntr_high + ext_fbk_cntr_low;
6974 cycles_to_unlock = 0;
6977 pll_about_to_lock = 0;
6980 // check if pll is in test mode
6981 if (m_test_source != 5 || c0_test_source != 5 || c1_test_source != 5 || c2_test_source != 5 || c3_test_source != 5 || c4_test_source != 5 || c5_test_source != 5)
6982 pll_in_test_mode = 1'b1;
6984 pll_in_test_mode = 1'b0;
6987 pll_is_in_reset = 0;
6990 always @(clkswitch_ipd)
6992 if (clkswitch_ipd === 1'b1 && l_switch_over_type == "auto")
6993 external_switch = 1;
6994 else if (l_switch_over_type == "manual")
6996 if (clkswitch_ipd === 1'b1)
6998 current_clock = "inclk1";
7000 inclk_n = inclk1_ipd;
7002 else if (clkswitch_ipd === 1'b0)
7004 current_clock = "inclk0";
7006 inclk_n = inclk0_ipd;
7011 always @(inclk0_ipd or inclk1_ipd)
7013 // save the inclk event value
7014 if (inclk0_ipd !== inclk0_last_value)
7016 if (current_clock !== "inclk0")
7017 other_clock_value = inclk0_ipd;
7019 if (inclk1_ipd !== inclk1_last_value)
7021 if (current_clock !== "inclk1")
7022 other_clock_value = inclk1_ipd;
7025 // check if either input clk is bad
7026 if (inclk0_ipd === 1'b1 && inclk0_ipd !== inclk0_last_value)
7028 clk0_count = clk0_count + 1;
7033 // no event on other clk for 2 cycles
7035 if (current_clock == "inclk1")
7036 current_clk_is_bad = 1;
7039 if (inclk1_ipd === 1'b1 && inclk1_ipd !== inclk1_last_value)
7041 clk1_count = clk1_count + 1;
7046 // no event on other clk for 2 cycles
7048 if (current_clock == "inclk0")
7049 current_clk_is_bad = 1;
7053 // check if the bad clk is the primary clock, which is always clk0
7054 if (clk0_is_bad == 1'b1)
7055 primary_clk_is_bad = 1;
7057 primary_clk_is_bad = 0;
7059 // actual switching -- manual switch
7060 if ((inclk0_ipd !== inclk0_last_value) && current_clock == "inclk0")
7062 if (external_switch == 1'b1)
7064 if (!got_curr_clk_falling_edge_after_clkswitch)
7066 if (inclk0_ipd === 1'b0)
7067 got_curr_clk_falling_edge_after_clkswitch = 1;
7068 inclk_n = inclk0_ipd;
7071 else inclk_n = inclk0_ipd;
7073 if ((inclk1_ipd !== inclk1_last_value) && current_clock == "inclk1")
7075 if (external_switch == 1'b1)
7077 if (!got_curr_clk_falling_edge_after_clkswitch)
7079 if (inclk1_ipd === 1'b0)
7080 got_curr_clk_falling_edge_after_clkswitch = 1;
7081 inclk_n = inclk1_ipd;
7084 else inclk_n = inclk1_ipd;
7087 // actual switching -- automatic switch
7088 if ((other_clock_value == 1'b1) && (other_clock_value != other_clock_last_value) && (l_switch_over_on_lossclk == "on") && l_enable_switch_over_counter == "on" && primary_clk_is_bad)
7089 switch_over_count = switch_over_count + 1;
7091 if ((other_clock_value == 1'b0) && (other_clock_value != other_clock_last_value))
7093 if ((external_switch && (got_curr_clk_falling_edge_after_clkswitch || current_clk_is_bad)) || (l_switch_over_on_lossclk == "on" && primary_clk_is_bad && l_pll_type !== "fast" && l_pll_type !== "lvds" && ((l_enable_switch_over_counter == "off" || switch_over_count == switch_over_counter))))
7095 got_curr_clk_falling_edge_after_clkswitch = 0;
7096 if (current_clock == "inclk0")
7097 current_clock = "inclk1";
7099 current_clock = "inclk0";
7100 active_clock = ~active_clock;
7101 switch_over_count = 0;
7102 external_switch = 0;
7103 current_clk_is_bad = 0;
7107 if (l_switch_over_on_lossclk == "on" && (clkswitch_ipd != 1'b1))
7109 if (primary_clk_is_bad)
7114 else clkloss_tmp = clkswitch_ipd;
7116 inclk0_last_value = inclk0_ipd;
7117 inclk1_last_value = inclk1_ipd;
7118 other_clock_last_value = other_clock_value;
7122 and (clkbad[0], clk0_is_bad, 1'b1);
7123 and (clkbad[1], clk1_is_bad, 1'b1);
7124 and (activeclock, active_clock, 1'b1);
7125 and (clkloss, clkloss_tmp, 1'b1);
7127 MF_pll_reg ena_reg ( .clk(!inclk_n),
7134 and (test_mode_inclk, inclk_n, pllena_reg);
7135 assign n_cntr_inclk = (pll_in_test_mode === 1'b1) ? test_mode_inclk : inclk_n;
7136 assign ena_pll = (pll_in_test_mode === 1'b1) ? pllena_reg : ena_ipd;
7138 assign inclk_m = (m_test_source == 0) ? n_cntr_inclk : l_operation_mode == "external_feedback" ? (l_feedback_source == "clk0" ? clk0_tmp :
7139 l_feedback_source == "clk1" ? clk1_tmp :
7140 l_feedback_source == "clk2" ? clk2_tmp :
7141 l_feedback_source == "clk3" ? clk3_tmp :
7142 l_feedback_source == "clk4" ? clk4_tmp :
7143 l_feedback_source == "clk5" ? clk5_tmp : 'b0) :
7147 arm_m_cntr m1 (.clk(inclk_m),
7148 .reset(areset_ipd || (!ena_pll) || stop_vco),
7150 .initial_value(m_initial_val),
7152 .time_delay(m_delay));
7154 arm_n_cntr n1 (.clk(n_cntr_inclk),
7157 .modulus(n_val[0]));
7163 // check which VCO TAP has event
7164 for (x = 0; x <= 7; x = x + 1)
7166 if (vco_out[x] !== vco_out_last_value[x])
7168 if (c_ph_val[0] == x)
7170 inclk_c0_from_vco <= vco_out[x];
7171 if (enable0_counter == "c0")
7172 inclk_sclkout0_from_vco <= vco_out[x];
7173 if (enable1_counter == "c0")
7174 inclk_sclkout1_from_vco <= vco_out[x];
7176 if (c_ph_val[1] == x)
7178 inclk_c1_from_vco <= vco_out[x];
7179 if (enable0_counter == "c1")
7180 inclk_sclkout0_from_vco <= vco_out[x];
7181 if (enable1_counter == "c1")
7182 inclk_sclkout1_from_vco <= vco_out[x];
7184 if (c_ph_val[2] == x)
7185 inclk_c2_from_vco <= vco_out[x];
7186 if (c_ph_val[3] == x)
7187 inclk_c3_from_vco <= vco_out[x];
7188 if (c_ph_val[4] == x)
7189 inclk_c4_from_vco <= vco_out[x];
7190 if (c_ph_val[5] == x)
7191 inclk_c5_from_vco <= vco_out[x];
7193 inclk_m_from_vco <= vco_out[x];
7196 if (scanwrite_enabled === 1'b1)
7198 for (x = 0; x <= 7; x = x + 1)
7200 if ((vco_out[x] === 1'b0) && (vco_out[x] !== vco_out_last_value[x]))
7202 for (y = 0; y <= 5; y = y + 1)
7204 if (c_ph_val[y] == x)
7205 c_ph_val[y] <= c_ph_val_tmp[y];
7208 m_ph_val <= m_ph_val_tmp;
7213 // reset all counter phase tap values to POF programmed values
7214 if (areset_ipd === 1'b1)
7216 m_ph_val <= m_ph_val_orig;
7217 m_ph_val_tmp <= m_ph_val_orig;
7218 for (i=0; i<= 5; i=i+1)
7220 c_ph_val[i] <= c_ph_val_orig[i];
7221 c_ph_val_tmp[i] <= c_ph_val_orig[i];
7225 vco_out_last_value = vco_out;
7228 always @(inclk_sclkout0_from_vco)
7230 sclkout0_tmp <= inclk_sclkout0_from_vco;
7232 always @(inclk_sclkout1_from_vco)
7234 sclkout1_tmp <= inclk_sclkout1_from_vco;
7237 assign inclk_c0 = (c0_test_source == 0) ? n_cntr_inclk : (c0_test_source == 1) ? refclk : inclk_c0_from_vco;
7239 arm_scale_cntr c0 (.clk(inclk_c0),
7240 .reset(areset_ipd || (!ena_pll) || stop_vco),
7242 .high(c_high_val[0]),
7244 .initial_value(c_initial_val[0]),
7245 .mode(c_mode_val[0]),
7246 .ph_tap(c_ph_val[0]));
7248 always @(posedge c0_clk)
7250 if (scanwrite_enabled == 1'b1)
7252 c_high_val_hold[0] <= c_high_val_tmp[0];
7253 c_mode_val_hold[0] <= c_mode_val_tmp[0];
7254 c_high_val[0] <= c_high_val_hold[0];
7255 c_mode_val[0] <= c_mode_val_hold[0];
7256 c0_rising_edge_transfer_done = 1;
7259 always @(negedge c0_clk)
7261 if (c0_rising_edge_transfer_done)
7263 c_low_val_hold[0] <= c_low_val_tmp[0];
7264 c_low_val[0] <= c_low_val_hold[0];
7268 assign inclk_c1 = (c1_test_source == 0) ? n_cntr_inclk : (c1_test_source == 2) ? fbclk : (c1_use_casc_in == "on") ? c0_clk : inclk_c1_from_vco;
7270 arm_scale_cntr c1 (.clk(inclk_c1),
7271 .reset(areset_ipd || (!ena_pll) || stop_vco),
7273 .high(c_high_val[1]),
7275 .initial_value(c_initial_val[1]),
7276 .mode(c_mode_val[1]),
7277 .ph_tap(c_ph_val[1]));
7279 always @(posedge c1_clk)
7281 if (scanwrite_enabled == 1'b1)
7283 c_high_val_hold[1] <= c_high_val_tmp[1];
7284 c_mode_val_hold[1] <= c_mode_val_tmp[1];
7285 c_high_val[1] <= c_high_val_hold[1];
7286 c_mode_val[1] <= c_mode_val_hold[1];
7287 c1_rising_edge_transfer_done = 1;
7290 always @(negedge c1_clk)
7292 if (c1_rising_edge_transfer_done)
7294 c_low_val_hold[1] <= c_low_val_tmp[1];
7295 c_low_val[1] <= c_low_val_hold[1];
7299 assign inclk_c2 = (c2_test_source == 0) ? n_cntr_inclk : (c2_use_casc_in == "on") ? c1_clk : inclk_c2_from_vco;
7301 arm_scale_cntr c2 (.clk(inclk_c2),
7302 .reset(areset_ipd || (!ena_pll) || stop_vco),
7304 .high(c_high_val[2]),
7306 .initial_value(c_initial_val[2]),
7307 .mode(c_mode_val[2]),
7308 .ph_tap(c_ph_val[2]));
7310 always @(posedge c2_clk)
7312 if (scanwrite_enabled == 1'b1)
7314 c_high_val_hold[2] <= c_high_val_tmp[2];
7315 c_mode_val_hold[2] <= c_mode_val_tmp[2];
7316 c_high_val[2] <= c_high_val_hold[2];
7317 c_mode_val[2] <= c_mode_val_hold[2];
7318 c2_rising_edge_transfer_done = 1;
7321 always @(negedge c2_clk)
7323 if (c2_rising_edge_transfer_done)
7325 c_low_val_hold[2] <= c_low_val_tmp[2];
7326 c_low_val[2] <= c_low_val_hold[2];
7330 assign inclk_c3 = (c3_test_source == 0) ? n_cntr_inclk : (c3_use_casc_in == "on") ? c2_clk : inclk_c3_from_vco;
7331 arm_scale_cntr c3 (.clk(inclk_c3),
7332 .reset(areset_ipd || (!ena_pll) || stop_vco),
7334 .high(c_high_val[3]),
7336 .initial_value(c_initial_val[3]),
7337 .mode(c_mode_val[3]),
7338 .ph_tap(c_ph_val[3]));
7340 always @(posedge c3_clk)
7342 if (scanwrite_enabled == 1'b1)
7344 c_high_val_hold[3] <= c_high_val_tmp[3];
7345 c_mode_val_hold[3] <= c_mode_val_tmp[3];
7346 c_high_val[3] <= c_high_val_hold[3];
7347 c_mode_val[3] <= c_mode_val_hold[3];
7348 c3_rising_edge_transfer_done = 1;
7351 always @(negedge c3_clk)
7353 if (c3_rising_edge_transfer_done)
7355 c_low_val_hold[3] <= c_low_val_tmp[3];
7356 c_low_val[3] <= c_low_val_hold[3];
7360 assign inclk_c4 = (c4_test_source == 0) ? n_cntr_inclk : (c4_use_casc_in == "on") ? c3_clk : inclk_c4_from_vco;
7361 arm_scale_cntr c4 (.clk(inclk_c4),
7362 .reset(areset_ipd || (!ena_pll) || stop_vco),
7364 .high(c_high_val[4]),
7366 .initial_value(c_initial_val[4]),
7367 .mode(c_mode_val[4]),
7368 .ph_tap(c_ph_val[4]));
7370 always @(posedge c4_clk)
7372 if (scanwrite_enabled == 1'b1)
7374 c_high_val_hold[4] <= c_high_val_tmp[4];
7375 c_mode_val_hold[4] <= c_mode_val_tmp[4];
7376 c_high_val[4] <= c_high_val_hold[4];
7377 c_mode_val[4] <= c_mode_val_hold[4];
7378 c4_rising_edge_transfer_done = 1;
7381 always @(negedge c4_clk)
7383 if (c4_rising_edge_transfer_done)
7385 c_low_val_hold[4] <= c_low_val_tmp[4];
7386 c_low_val[4] <= c_low_val_hold[4];
7390 assign inclk_c5 = (c5_test_source == 0) ? n_cntr_inclk : (c5_use_casc_in == "on") ? c4_clk : inclk_c5_from_vco;
7391 arm_scale_cntr c5 (.clk(inclk_c5),
7392 .reset(areset_ipd || (!ena_pll) || stop_vco),
7394 .high(c_high_val[5]),
7396 .initial_value(c_initial_val[5]),
7397 .mode(c_mode_val[5]),
7398 .ph_tap(c_ph_val[5]));
7400 always @(posedge c5_clk)
7402 if (scanwrite_enabled == 1'b1)
7404 c_high_val_hold[5] <= c_high_val_tmp[5];
7405 c_mode_val_hold[5] <= c_mode_val_tmp[5];
7406 c_high_val[5] <= c_high_val_hold[5];
7407 c_mode_val[5] <= c_mode_val_hold[5];
7408 c5_rising_edge_transfer_done = 1;
7411 always @(negedge c5_clk)
7413 if (c5_rising_edge_transfer_done)
7415 c_low_val_hold[5] <= c_low_val_tmp[5];
7416 c_low_val[5] <= c_low_val_hold[5];
7420 always @(vco_out[c_ph_val[0]] or posedge areset_ipd or negedge ena_pll or stop_vco)
7422 if (areset_ipd == 1'b1 || ena_pll == 1'b0 || stop_vco == 1'b1)
7425 c0_initial_count = 1;
7426 c0_got_first_rising_edge = 0;
7430 if (c0_got_first_rising_edge == 1'b0)
7432 if (vco_out[c_ph_val[0]] == 1'b1 && vco_out[c_ph_val[0]] != vco_c0_last_value)
7434 if (c0_initial_count == c_initial_val[0])
7435 c0_got_first_rising_edge = 1;
7437 c0_initial_count = c0_initial_count + 1;
7440 else if (vco_out[c_ph_val[0]] != vco_c0_last_value)
7442 c0_count = c0_count + 1;
7443 if (c0_count == (c_high_val[0] + c_low_val[0]) * 2)
7446 if (vco_out[c_ph_val[0]] == 1'b0 && vco_out[c_ph_val[0]] != vco_c0_last_value)
7451 c0_got_first_rising_edge = 0;
7456 vco_c0_last_value = vco_out[c_ph_val[0]];
7459 always @(vco_out[c_ph_val[1]] or posedge areset_ipd or negedge ena_pll or stop_vco)
7461 if (areset_ipd == 1'b1 || ena_pll == 1'b0 || stop_vco == 1'b1)
7464 c1_initial_count = 1;
7465 c1_got_first_rising_edge = 0;
7468 if (c1_got_first_rising_edge == 1'b0)
7470 if (vco_out[c_ph_val[1]] == 1'b1 && vco_out[c_ph_val[1]] != vco_c1_last_value)
7472 if (c1_initial_count == c_initial_val[1])
7473 c1_got_first_rising_edge = 1;
7475 c1_initial_count = c1_initial_count + 1;
7478 else if (vco_out[c_ph_val[1]] != vco_c1_last_value)
7480 c1_count = c1_count + 1;
7481 if (c1_count == (c_high_val[1] + c_low_val[1]) * 2)
7484 if (vco_out[c_ph_val[1]] == 1'b0 && vco_out[c_ph_val[1]] != vco_c1_last_value)
7489 c1_got_first_rising_edge = 0;
7494 vco_c1_last_value = vco_out[c_ph_val[1]];
7497 assign enable0_tmp = (l_enable0_counter == "c0") ? c0_tmp : c1_tmp;
7498 assign enable1_tmp = (l_enable1_counter == "c0") ? c0_tmp : c1_tmp;
7500 always @ (inclk_n or ena_pll or areset_ipd)
7502 if (areset_ipd == 1'b1 || ena_pll == 1'b0)
7507 else if (inclk_n == 'b1 && inclk_last_value != inclk_n)
7509 gate_count = gate_count + 1;
7510 if (gate_count == gate_lock_counter)
7513 inclk_last_value = inclk_n;
7516 assign locked = (l_gate_lock_signal == "yes") ? gate_out && locked_tmp : locked_tmp;
7518 always @(posedge scanread_ipd)
7520 scanread_active_edge = $time;
7523 always @ (scanclk_ipd)
7525 if (scanclk_ipd === 1'b0 && scanclk_last_value === 1'b1)
7527 // enable scanwrite on falling edge
7528 scanwrite_enabled <= scanwrite_reg;
7530 if (scanread_reg === 1'b1)
7531 gated_scanclk <= scanclk_ipd && scanread_reg;
7533 gated_scanclk <= 1'b1;
7534 if (scanclk_ipd === 1'b1 && scanclk_last_value === 1'b0)
7536 // register scanread and scanwrite
7537 scanread_reg <= scanread_ipd;
7538 scanwrite_reg <= scanwrite_ipd;
7540 if (got_first_scanclk)
7541 scanclk_period = $time - scanclk_last_rising_edge;
7543 got_first_scanclk = 1;
7545 // reset got_first_scanclk on falling edge of scanread_reg
7546 if (scanread_ipd == 1'b0 && scanread_reg == 1'b1)
7548 got_first_scanclk = 0;
7549 got_first_gated_scanclk = 0;
7552 scanclk_last_rising_edge = $time;
7554 scanclk_last_value = scanclk_ipd;
7557 always @(posedge gated_scanclk)
7561 if (!got_first_gated_scanclk)
7563 got_first_gated_scanclk = 1;
7564 // if ($time - scanread_active_edge < scanclk_period)
7566 // scanread_setup_violation = 1;
7567 // $display("Warning : SCANREAD must go high at least one cycle before SCANDATA is read in.");
7568 // $display ("Time: %0t Instance: %m", $time);
7571 for (j = scan_chain_length-1; j >= 1; j = j - 1)
7573 scan_data[j] = scan_data[j - 1];
7575 scan_data[0] <= scandata_ipd;
7579 assign scandataout_tmp = (l_pll_type == "fast" || l_pll_type == "lvds") ? scan_data[FAST_SCAN_CHAIN-1] : scan_data[GPP_SCAN_CHAIN-1];
7581 always @(posedge scandone_tmp)
7583 if (reconfig_err == 1'b0)
7585 $display("NOTE : PLL Reprogramming completed with the following values (Values in parantheses are original values) : ");
7586 $display ("Time: %0t Instance: %m", $time);
7588 $display(" N modulus = %0d (%0d) ", n_val[0], n_val_old[0]);
7589 $display(" M modulus = %0d (%0d) ", m_val[0], m_val_old[0]);
7590 $display(" M ph_tap = %0d (%0d) ", m_ph_val, m_ph_val_old);
7593 $display(" M2 modulus = %0d (%0d) ", m_val[1], m_val_old[1]);
7594 $display(" N2 modulus = %0d (%0d) ", n_val[1], n_val_old[1]);
7597 for (i = 0; i < num_output_cntrs; i=i+1)
7599 $display(" C%0d high = %0d (%0d), C%0d low = %0d (%0d), C%0d mode = %s (%s), C%0d phase tap = %0d (%0d)", i, c_high_val[i], c_high_val_old[i], i, c_low_val_tmp[i], c_low_val_old[i], i, c_mode_val[i], c_mode_val_old[i], i, c_ph_val[i], c_ph_val_old[i]);
7602 // display Charge pump and loop filter values
7603 $display (" Charge Pump Current (uA) = %0d (%0d) ", cp_curr_val, cp_curr_old);
7604 $display (" Loop Filter Capacitor (pF) = %0d (%0d) ", lfc_val, lfc_old);
7605 $display (" Loop Filter Resistor (Kohm) = %s (%s) ", lfr_val, lfr_old);
7608 $display("Warning : Errors were encountered during PLL reprogramming. Please refer to error/warning messages above.");
7609 $display ("Time: %0t Instance: %m", $time);
7613 always @(scanwrite_enabled)
7615 if (scanwrite_enabled === 1'b0 && scanwrite_last_value === 1'b1)
7617 // falling edge : deassert scandone
7618 scandone_tmp <= #(1.5*scanclk_period) 1'b0;
7619 // reset counter transfer flags
7620 c0_rising_edge_transfer_done = 0;
7621 c1_rising_edge_transfer_done = 0;
7622 c2_rising_edge_transfer_done = 0;
7623 c3_rising_edge_transfer_done = 0;
7624 c4_rising_edge_transfer_done = 0;
7625 c5_rising_edge_transfer_done = 0;
7627 if (scanwrite_enabled === 1'b1 && scanwrite_last_value !== scanwrite_enabled)
7630 $display ("NOTE : PLL Reprogramming initiated ....");
7631 $display ("Time: %0t Instance: %m", $time);
7635 scanread_setup_violation = 0;
7637 // make temp. copy of scan_data for processing
7638 tmp_scan_data = scan_data;
7641 cp_curr_old = cp_curr_val;
7646 // Bits 0-3 : all values are legal
7647 cp_curr_val = charge_pump_curr_arr[scan_data[3:0]];
7649 // LF Resistance : bits 4-9
7650 // values from 010000 - 010111, 100000 - 100111,
7651 // 110000- 110111 are illegal
7652 if (((tmp_scan_data[9:4] >= 6'b010000) && (tmp_scan_data[9:4] <= 6'b010111)) ||
7653 ((tmp_scan_data[9:4] >= 6'b100000) && (tmp_scan_data[9:4] <= 6'b100111)) ||
7654 ((tmp_scan_data[9:4] >= 6'b110000) && (tmp_scan_data[9:4] <= 6'b110111)))
7656 $display ("Illegal bit settings for Loop Filter Resistance. Legal bit values range from 000000 to 001111, 011000 to 011111, 101000 to 101111 and 111000 to 111111. Reconfiguration may not work.");
7663 else if ((i >= 40) && (i <= 47))
7665 else if ((i >= 24) && (i <= 31))
7667 lfr_val = loop_filter_r_arr[i];
7670 // LF Capacitance : bits 10,11 : all values are legal
7671 if ((l_pll_type == "fast") || (l_pll_type == "lvds"))
7672 lfc_val = fpll_loop_filter_c_arr[scan_data[11:10]];
7674 lfc_val = loop_filter_c_arr[scan_data[11:10]];
7676 // save old values for display info.
7677 for (i=0; i<=1; i=i+1)
7679 m_val_old[i] = m_val[i];
7680 n_val_old[i] = n_val[i];
7681 m_mode_val_old[i] = m_mode_val[i];
7682 n_mode_val_old[i] = n_mode_val[i];
7684 m_ph_val_old = m_ph_val;
7685 for (i=0; i<=5; i=i+1)
7687 c_high_val_old[i] = c_high_val[i];
7688 c_low_val_old[i] = c_low_val[i];
7689 c_ph_val_old[i] = c_ph_val[i];
7690 c_mode_val_old[i] = c_mode_val[i];
7693 // first the M counter phase : bit order same for fast and GPP
7694 if (scan_data[12] == 1'b0)
7698 else if (scan_data[12] === 1'b1 && scan_data[13] === 1'b1)
7700 m_ph_val_tmp = m_ph_val_tmp + 1;
7701 if (m_ph_val_tmp > 7)
7704 else if (scan_data[12] === 1'b1 && scan_data[13] === 1'b0)
7706 m_ph_val_tmp = m_ph_val_tmp - 1;
7707 if (m_ph_val_tmp < 0)
7711 $display ("Warning : Illegal bit settings for M counter phase tap. Reconfiguration may not work.");
7715 // read the fast PLL bits.
7716 if (l_pll_type == "fast" || l_pll_type == "lvds")
7719 for (i = 3; i >= 0; i=i-1)
7721 if (tmp_scan_data[14] == 1'b0)
7725 else if (tmp_scan_data[14] === 1'b1)
7727 if (tmp_scan_data[15] === 1'b1)
7729 c_ph_val_tmp[i] = c_ph_val_tmp[i] + 1;
7730 if (c_ph_val_tmp[i] > 7)
7731 c_ph_val_tmp[i] = 0;
7733 else if (tmp_scan_data[15] === 1'b0)
7735 c_ph_val_tmp[i] = c_ph_val_tmp[i] - 1;
7736 if (c_ph_val_tmp[i] < 0)
7737 c_ph_val_tmp[i] = 7;
7740 tmp_scan_data = tmp_scan_data >> 2;
7742 // C0-C3 counter moduli
7743 tmp_scan_data = scan_data;
7744 for (i = 0; i < 4; i=i+1)
7746 if (tmp_scan_data[26] == 1'b1)
7748 c_mode_val_tmp[i] = "bypass";
7749 if (tmp_scan_data[31] === 1'b1)
7751 c_mode_val_tmp[i] = " off";
7752 $display("Warning : The specified bit settings will turn OFF the C%0d counter. It cannot be turned on unless the part is re-initialized.", i);
7755 else if (tmp_scan_data[31] == 1'b1)
7756 c_mode_val_tmp[i] = " odd";
7758 c_mode_val_tmp[i] = " even";
7759 if (tmp_scan_data[25:22] === 4'b0000)
7760 c_high_val_tmp[i] = 5'b10000;
7762 c_high_val_tmp[i] = tmp_scan_data[25:22];
7763 if (tmp_scan_data[30:27] === 4'b0000)
7764 c_low_val_tmp[i] = 5'b10000;
7766 c_low_val_tmp[i] = tmp_scan_data[30:27];
7768 tmp_scan_data = tmp_scan_data >> 10;
7772 // some temporary storage
7773 if (scan_data[65:62] == 4'b0000)
7776 m_hi = scan_data[65:62];
7778 if (scan_data[70:67] == 4'b0000)
7781 m_lo = scan_data[70:67];
7783 m_val_tmp[0] = m_hi + m_lo;
7784 if (scan_data[66] === 1'b1)
7786 if (scan_data[71] === 1'b1)
7788 // this will turn off the M counter : error
7791 $display ("The specified bit settings will turn OFF the M counter. This is illegal. Reconfiguration may not work.");
7794 // M counter is being bypassed
7795 if (m_mode_val[0] !== "bypass")
7797 // Mode is switched : give warning
7798 d_msg = display_msg(" M", 4);
7800 m_val_tmp[0] = 32'b1;
7801 m_mode_val[0] = "bypass";
7805 if (m_mode_val[0] === "bypass")
7807 // Mode is switched : give warning
7808 d_msg = display_msg(" M", 1);
7811 if (scan_data[71] === 1'b1)
7813 // odd : check for duty cycle, if not 50% -- error
7814 if (m_hi - m_lo !== 1)
7817 $display ("Warning : The M counter of the StratixII Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work");
7820 else begin // even mode
7824 $display ("Warning : The M counter of the StratixII Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work");
7831 n_val[0] = scan_data[73:72];
7832 if (scan_data[74] !== 1'b1)
7834 if (scan_data[73:72] == 2'b01)
7838 // Cntr value is illegal : give warning
7839 d_msg = display_msg(" N", 2);
7841 else if (scan_data[73:72] == 2'b00)
7845 if (n_mode_val[0] === "bypass")
7847 // Mode is switched : give warning
7848 d_msg = display_msg(" N", 1);
7853 else if (scan_data[74] == 1'b1) // bypass
7855 if (scan_data[72] !== 1'b0)
7859 // Cntr value is illegal : give warning
7860 d_msg = display_msg(" N", 3);
7863 if (n_mode_val[0] != "bypass")
7865 // Mode is switched : give warning
7866 d_msg = display_msg(" N", 4);
7869 n_mode_val[0] = "bypass";
7873 else begin // pll type is auto or enhanced
7874 for (i = 0; i < 6; i=i+1)
7876 if (tmp_scan_data[124] == 1'b1)
7878 c_mode_val_tmp[i] = "bypass";
7879 if (tmp_scan_data[133] === 1'b1)
7881 c_mode_val_tmp[i] = " off";
7882 $display("Warning : The specified bit settings will turn OFF the C%0d counter. It cannot be turned on unless the part is re-initialized.", i);
7885 else if (tmp_scan_data[133] == 1'b1)
7886 c_mode_val_tmp[i] = " odd";
7888 c_mode_val_tmp[i] = " even";
7889 if (tmp_scan_data[123:116] === 8'b00000000)
7890 c_high_val_tmp[i] = 9'b100000000;
7892 c_high_val_tmp[i] = tmp_scan_data[123:116];
7893 if (tmp_scan_data[132:125] === 8'b00000000)
7894 c_low_val_tmp[i] = 9'b100000000;
7896 c_low_val_tmp[i] = tmp_scan_data[132:125];
7898 tmp_scan_data = tmp_scan_data << 18;
7902 tmp_scan_data = scan_data;
7903 for (i = 0; i < 6; i=i+1)
7905 if (tmp_scan_data[14] == 1'b0)
7909 else if (tmp_scan_data[14] === 1'b1)
7911 if (tmp_scan_data[15] === 1'b1)
7913 c_ph_val_tmp[i] = c_ph_val_tmp[i] + 1;
7914 if (c_ph_val_tmp[i] > 7)
7915 c_ph_val_tmp[i] = 0;
7917 else if (tmp_scan_data[15] === 1'b0)
7919 c_ph_val_tmp[i] = c_ph_val_tmp[i] - 1;
7920 if (c_ph_val_tmp[i] < 0)
7921 c_ph_val_tmp[i] = 7;
7924 tmp_scan_data = tmp_scan_data >> 2;
7926 ext_fbk_cntr_high = c_high_val[ext_fbk_cntr_index];
7927 ext_fbk_cntr_low = c_low_val[ext_fbk_cntr_index];
7928 ext_fbk_cntr_ph = c_ph_val[ext_fbk_cntr_index];
7929 ext_fbk_cntr_mode = c_mode_val[ext_fbk_cntr_index];
7932 tmp_scan_data = scan_data;
7933 for (i=0; i<2; i=i+1)
7935 if (i == 0 || (i == 1 && ss > 0))
7938 m_val_tmp[i] = tmp_scan_data[142:134];
7939 if (tmp_scan_data[143] !== 1'b1)
7941 if (tmp_scan_data[142:134] == 9'b000000001)
7945 // Cntr value is illegal : give warning
7947 d_msg = display_msg(" M", 2);
7949 d_msg = display_msg("M2", 2);
7951 else if (tmp_scan_data[142:134] == 9'b000000000)
7952 m_val_tmp[i] = 10'b1000000000;
7955 if (m_mode_val[i] === "bypass")
7957 // Mode is switched : give warning
7959 d_msg = display_msg(" M", 1);
7961 d_msg = display_msg("M2", 1);
7966 else if (tmp_scan_data[143] == 1'b1)
7968 if (tmp_scan_data[134] !== 1'b0)
7972 // Cntr value is illegal : give warning
7974 d_msg = display_msg(" M", 3);
7976 d_msg = display_msg("M2", 3);
7979 if (m_mode_val[i] !== "bypass")
7981 // Mode is switched: give warning
7983 d_msg = display_msg(" M", 4);
7985 d_msg = display_msg("M2", 4);
7987 m_val_tmp[i] = 10'b0000000001;
7988 m_mode_val[i] = "bypass";
7992 tmp_scan_data = tmp_scan_data >> 10;
7996 if (m_mode_val[0] != m_mode_val[1])
8000 $display ("Warning : Incompatible modes for M/M2 counters. Either both should be BYASSED or both NON-BYPASSED. Reconfiguration may not work.");
8005 tmp_scan_data = scan_data;
8006 for (i=0; i<2; i=i+1)
8008 if (i == 0 || (i == 1 && ss > 0))
8011 n_val[i] = tmp_scan_data[162:154];
8012 if (tmp_scan_data[163] !== 1'b1)
8014 if (tmp_scan_data[162:154] == 9'b000000001)
8018 // Cntr value is illegal : give warning
8020 d_msg = display_msg(" N", 2);
8022 d_msg = display_msg("N2", 2);
8024 else if (tmp_scan_data[162:154] == 9'b000000000)
8025 n_val[i] = 10'b1000000000;
8028 if (n_mode_val[i] === "bypass")
8030 // Mode is switched : give warning
8032 d_msg = display_msg(" N", 1);
8034 d_msg = display_msg("N2", 1);
8039 else if (tmp_scan_data[163] == 1'b1) // bypass
8041 if (tmp_scan_data[154] !== 1'b0)
8045 // Cntr value is illegal : give warning
8047 d_msg = display_msg(" N", 3);
8049 d_msg = display_msg("N2", 3);
8052 if (n_mode_val[i] != "bypass")
8054 // Mode is switched : give warning
8056 d_msg = display_msg(" N", 4);
8058 d_msg = display_msg("N2", 4);
8060 n_val[i] = 10'b0000000001;
8061 n_mode_val[i] = "bypass";
8065 tmp_scan_data = tmp_scan_data >> 10;
8069 if (n_mode_val[0] != n_mode_val[1])
8073 $display ("Warning : Incompatible modes for N/N2 counters. Either both should be BYASSED or both NON-BYPASSED. Reconfiguration may not work.");
8078 slowest_clk_old = slowest_clk ( c_high_val[0]+c_low_val[0], c_mode_val[0],
8079 c_high_val[1]+c_low_val[1], c_mode_val[1],
8080 c_high_val[2]+c_low_val[2], c_mode_val[2],
8081 c_high_val[3]+c_low_val[3], c_mode_val[3],
8082 c_high_val[4]+c_low_val[4], c_mode_val[4],
8083 c_high_val[5]+c_low_val[5], c_mode_val[5],
8084 refclk_period, m_val[0]);
8086 slowest_clk_new = slowest_clk ( c_high_val_tmp[0]+c_low_val[0], c_mode_val_tmp[0],
8087 c_high_val_tmp[1]+c_low_val[1], c_mode_val_tmp[1],
8088 c_high_val_tmp[2]+c_low_val[2], c_mode_val_tmp[2],
8089 c_high_val_tmp[3]+c_low_val[3], c_mode_val_tmp[3],
8090 c_high_val_tmp[4]+c_low_val[4], c_mode_val_tmp[4],
8091 c_high_val_tmp[5]+c_low_val[5], c_mode_val_tmp[5],
8092 refclk_period, m_val[0]);
8094 quiet_time = (slowest_clk_new > slowest_clk_old) ? slowest_clk_new : slowest_clk_old;
8096 // get quiet time in terms of scanclk cycles
8097 my_rem = quiet_time % scanclk_period;
8098 scanclk_cycles = quiet_time/scanclk_period;
8100 scanclk_cycles = scanclk_cycles + 1;
8102 scandone_tmp <= #((scanclk_cycles+0.5) * scanclk_period) 1'b1;
8105 scanwrite_last_value = scanwrite_enabled;
8108 always @(schedule_vco or areset_ipd or ena_pll)
8112 for (i = 0; i <= 7; i=i+1)
8113 last_phase_shift[i] = phase_shift[i];
8115 cycle_to_adjust = 0;
8117 m_times_vco_period = new_m_times_vco_period;
8119 // give appropriate messages
8120 // if areset was asserted
8121 if (areset_ipd === 1'b1 && areset_ipd_last_value !== areset_ipd)
8123 $display (" Note : PLL was reset");
8124 $display ("Time: %0t Instance: %m", $time);
8125 // reset lock parameters
8128 pll_about_to_lock = 0;
8130 cycles_to_unlock = 0;
8133 // if ena was deasserted
8134 if (ena_pll == 1'b0 && ena_ipd_last_value !== ena_pll)
8136 $display (" Note : PLL was disabled");
8137 $display ("Time: %0t Instance: %m", $time);
8140 // illegal value on areset_ipd
8141 if (areset_ipd === 1'bx && (areset_ipd_last_value === 1'b0 || areset_ipd_last_value === 1'b1))
8143 $display("Warning : Illegal value 'X' detected on ARESET input");
8144 $display ("Time: %0t Instance: %m", $time);
8147 if ((schedule_vco !== schedule_vco_last_value) && (areset_ipd == 1'b1 || ena_pll == 1'b0 || stop_vco == 1'b1))
8150 if (areset_ipd === 1'b1)
8151 pll_is_in_reset = 1;
8153 // drop VCO taps to 0
8154 for (i = 0; i <= 7; i=i+1)
8156 for (j = 0; j <= last_phase_shift[i] + 1; j=j+1)
8157 vco_out[i] <= #(j) 1'b0;
8159 last_phase_shift[i] = 0;
8162 // reset lock parameters
8165 pll_about_to_lock = 0;
8167 cycles_to_unlock = 0;
8169 got_first_refclk = 0;
8170 got_second_refclk = 0;
8172 got_first_fbclk = 0;
8174 first_fbclk_time = 0;
8179 vco_period_was_phase_adjusted = 0;
8180 phase_adjust_was_scheduled = 0;
8182 // reset all counter phase tap values to POF programmed values
8183 m_ph_val = m_ph_val_orig;
8184 for (i=0; i<= 5; i=i+1)
8185 c_ph_val[i] = c_ph_val_orig[i];
8187 end else if (ena_pll === 1'b1 && areset_ipd === 1'b0 && stop_vco === 1'b0)
8189 // else note areset deassert time
8190 // note it as refclk_time to prevent false triggering
8191 // of stop_vco after areset
8192 if (areset_ipd === 1'b0 && areset_ipd_last_value === 1'b1 && pll_is_in_reset === 1'b1)
8194 refclk_time = $time;
8195 pll_is_in_reset = 0;
8198 // calculate loop_xplier : this will be different from m_val in ext. fbk mode
8199 loop_xplier = m_val[0];
8200 loop_initial = i_m_initial - 1;
8203 if (l_operation_mode == "external_feedback")
8205 if (ext_fbk_cntr_mode == "bypass")
8206 ext_fbk_cntr_modulus = 1;
8208 ext_fbk_cntr_modulus = ext_fbk_cntr_high + ext_fbk_cntr_low;
8210 loop_xplier = m_val[0] * (ext_fbk_cntr_modulus);
8211 loop_ph = ext_fbk_cntr_ph;
8212 loop_initial = ext_fbk_cntr_initial - 1 + ((i_m_initial - 1) * ext_fbk_cntr_modulus);
8215 // convert initial value to delay
8216 initial_delay = (loop_initial * m_times_vco_period)/loop_xplier;
8218 // convert loop ph_tap to delay
8219 rem = m_times_vco_period % loop_xplier;
8220 vco_per = m_times_vco_period/loop_xplier;
8222 vco_per = vco_per + 1;
8223 fbk_phase = (loop_ph * vco_per)/8;
8225 if (l_operation_mode == "external_feedback")
8227 pull_back_M = (i_m_initial - 1) * (ext_fbk_cntr_modulus) * (m_times_vco_period/loop_xplier);
8229 while (pull_back_M > refclk_period)
8230 pull_back_M = pull_back_M - refclk_period;
8233 pull_back_M = initial_delay + fbk_phase;
8236 total_pull_back = pull_back_M;
8237 if (l_simulation_type == "timing")
8238 total_pull_back = total_pull_back + pll_compensation_delay;
8240 while (total_pull_back > refclk_period)
8241 total_pull_back = total_pull_back - refclk_period;
8243 if (total_pull_back > 0)
8244 offset = refclk_period - total_pull_back;
8248 if (l_operation_mode == "external_feedback")
8250 fbk_delay = pull_back_M;
8251 if (l_simulation_type == "timing")
8252 fbk_delay = fbk_delay + pll_compensation_delay;
8255 fbk_delay = total_pull_back - fbk_phase;
8258 offset = offset - fbk_phase;
8259 fbk_delay = total_pull_back;
8264 m_delay = fbk_delay;
8266 for (i = 1; i <= loop_xplier; i=i+1)
8269 tmp_vco_per = m_times_vco_period/loop_xplier;
8270 if (rem != 0 && l_index <= rem)
8272 tmp_rem = (loop_xplier * l_index) % rem;
8273 cycle_to_adjust = (loop_xplier * l_index) / rem;
8275 cycle_to_adjust = cycle_to_adjust + 1;
8277 if (cycle_to_adjust == i)
8279 tmp_vco_per = tmp_vco_per + 1;
8280 l_index = l_index + 1;
8283 // calculate high and low periods
8284 high_time = tmp_vco_per/2;
8285 if (tmp_vco_per % 2 != 0)
8286 high_time = high_time + 1;
8287 low_time = tmp_vco_per - high_time;
8289 // schedule the rising and falling egdes
8290 for (j=0; j<=1; j=j+1)
8293 if (vco_val == 1'b0)
8294 sched_time = sched_time + high_time;
8296 sched_time = sched_time + low_time;
8298 // schedule taps with appropriate phase shifts
8299 for (k = 0; k <= 7; k=k+1)
8301 phase_shift[k] = (k*tmp_vco_per)/8;
8303 vco_out[k] <= #(sched_time + phase_shift[k]) vco_val;
8305 vco_out[k] <= #(sched_time + last_phase_shift[k]) vco_val;
8312 if (vco_val == 1'b0)
8313 sched_time = sched_time + high_time;
8315 sched_time = sched_time + low_time;
8316 for (k = 0; k <= 7; k=k+1)
8318 phase_shift[k] = (k*tmp_vco_per)/8;
8319 vco_out[k] <= #(sched_time+phase_shift[k]) vco_val;
8324 schedule_vco <= #(sched_time) ~schedule_vco;
8325 if (vco_period_was_phase_adjusted)
8327 m_times_vco_period = refclk_period;
8328 new_m_times_vco_period = refclk_period;
8329 vco_period_was_phase_adjusted = 0;
8330 phase_adjust_was_scheduled = 1;
8332 tmp_vco_per = m_times_vco_period/loop_xplier;
8333 for (k = 0; k <= 7; k=k+1)
8334 phase_shift[k] = (k*tmp_vco_per)/8;
8338 areset_ipd_last_value = areset_ipd;
8339 ena_ipd_last_value = ena_pll;
8340 schedule_vco_last_value = schedule_vco;
8344 always @(pfdena_ipd)
8346 if (pfdena_ipd === 1'b0)
8352 $display (" Note : PFDENA was deasserted");
8353 $display ("Time: %0t Instance: %m", $time);
8355 else if (pfdena_ipd === 1'b1 && pfdena_ipd_last_value === 1'b0)
8357 // PFD was disabled, now enabled again
8358 got_first_refclk = 0;
8359 got_second_refclk = 0;
8360 refclk_time = $time;
8362 pfdena_ipd_last_value = pfdena_ipd;
8365 always @(negedge refclk or negedge fbclk)
8367 refclk_last_value = refclk;
8368 fbclk_last_value = fbclk;
8371 always @(posedge refclk or posedge fbclk)
8373 if (refclk == 1'b1 && refclk_last_value !== refclk && areset_ipd === 1'b0)
8375 if (! got_first_refclk)
8377 got_first_refclk = 1;
8380 got_second_refclk = 1;
8381 refclk_period = $time - refclk_time;
8383 // check if incoming freq. will cause VCO range to be
8385 if ((vco_max != 0 && vco_min != 0) && (pfdena_ipd === 1'b1) &&
8386 ((refclk_period/loop_xplier > vco_max) ||
8387 (refclk_period/loop_xplier < vco_min)) )
8389 if (pll_is_locked == 1'b1)
8391 $display ("Warning : Input clock freq. is not within VCO range. PLL may lose lock");
8392 $display ("Time: %0t Instance: %m", $time);
8393 if (inclk_out_of_range === 1'b1)
8398 pll_about_to_lock = 0;
8400 $display ("Note : PLL lost lock");
8401 $display ("Time: %0t Instance: %m", $time);
8402 vco_period_was_phase_adjusted = 0;
8403 phase_adjust_was_scheduled = 0;
8407 if (no_warn == 1'b0)
8409 $display ("Warning : Input clock freq. is not within VCO range. PLL may not lock");
8410 $display ("Time: %0t Instance: %m", $time);
8414 inclk_out_of_range = 1;
8417 inclk_out_of_range = 0;
8421 if (stop_vco == 1'b1)
8424 schedule_vco = ~schedule_vco;
8426 refclk_time = $time;
8429 if (fbclk == 1'b1 && fbclk_last_value !== fbclk)
8431 if (scanwrite_enabled === 1'b1)
8433 m_val[0] <= m_val_tmp[0];
8434 m_val[1] <= m_val_tmp[1];
8436 if (!got_first_fbclk)
8438 got_first_fbclk = 1;
8439 first_fbclk_time = $time;
8442 fbclk_period = $time - fbclk_time;
8444 // need refclk_period here, so initialized to proper value above
8445 if ( ( ($time - refclk_time > 1.5 * refclk_period) && pfdena_ipd === 1'b1 && pll_is_locked === 1'b1) || ( ($time - refclk_time > 5 * refclk_period) && pfdena_ipd === 1'b1) )
8449 got_first_refclk = 0;
8450 got_first_fbclk = 0;
8451 got_second_refclk = 0;
8452 if (pll_is_locked == 1'b1)
8456 $display ("Note : PLL lost lock due to loss of input clock");
8457 $display ("Time: %0t Instance: %m", $time);
8459 pll_about_to_lock = 0;
8461 cycles_to_unlock = 0;
8463 vco_period_was_phase_adjusted = 0;
8464 phase_adjust_was_scheduled = 0;
8469 if (got_second_refclk && pfdena_ipd === 1'b1 && (!inclk_out_of_range))
8471 // now we know actual incoming period
8472 if (abs(fbclk_time - refclk_time) <= 5 || (got_first_fbclk && abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5))
8474 // considered in phase
8475 if (cycles_to_lock == valid_lock_multiplier - 1)
8476 pll_about_to_lock <= 1;
8477 if (cycles_to_lock == valid_lock_multiplier)
8479 if (pll_is_locked === 1'b0)
8481 $display (" Note : PLL locked to incoming clock");
8482 $display ("Time: %0t Instance: %m", $time);
8486 cycles_to_unlock = 0;
8488 // increment lock counter only if the second part of the above
8489 // time check is not true
8490 if (!(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5))
8492 cycles_to_lock = cycles_to_lock + 1;
8495 // adjust m_times_vco_period
8496 new_m_times_vco_period = refclk_period;
8500 // if locked, begin unlock
8503 cycles_to_unlock = cycles_to_unlock + 1;
8504 if (cycles_to_unlock == invalid_lock_multiplier)
8508 pll_about_to_lock = 0;
8510 $display ("Note : PLL lost lock");
8511 $display ("Time: %0t Instance: %m", $time);
8512 vco_period_was_phase_adjusted = 0;
8513 phase_adjust_was_scheduled = 0;
8516 if (abs(refclk_period - fbclk_period) <= 2)
8518 // frequency is still good
8519 if ($time == fbclk_time && (!phase_adjust_was_scheduled))
8521 if (abs(fbclk_time - refclk_time) > refclk_period/2)
8523 new_m_times_vco_period = m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
8524 vco_period_was_phase_adjusted = 1;
8527 new_m_times_vco_period = m_times_vco_period - abs(fbclk_time - refclk_time);
8528 vco_period_was_phase_adjusted = 1;
8533 new_m_times_vco_period = refclk_period;
8534 phase_adjust_was_scheduled = 0;
8539 if (reconfig_err == 1'b1)
8544 refclk_last_value = refclk;
8545 fbclk_last_value = fbclk;
8548 assign clk0_tmp = i_clk0_counter == "c0" ? c0_clk : i_clk0_counter == "c1" ? c1_clk : i_clk0_counter == "c2" ? c2_clk : i_clk0_counter == "c3" ? c3_clk : i_clk0_counter == "c4" ? c4_clk : i_clk0_counter == "c5" ? c5_clk : 'b0;
8550 assign clk0 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk0_tmp : 'bx;
8553 assign clk1_tmp = i_clk1_counter == "c0" ? c0_clk : i_clk1_counter == "c1" ? c1_clk : i_clk1_counter == "c2" ? c2_clk : i_clk1_counter == "c3" ? c3_clk : i_clk1_counter == "c4" ? c4_clk : i_clk1_counter == "c5" ? c5_clk : 'b0;
8555 assign clk1 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk1_tmp : 'bx;
8558 assign clk2_tmp = i_clk2_counter == "c0" ? c0_clk : i_clk2_counter == "c1" ? c1_clk : i_clk2_counter == "c2" ? c2_clk : i_clk2_counter == "c3" ? c3_clk : i_clk2_counter == "c4" ? c4_clk : i_clk2_counter == "c5" ? c5_clk : 'b0;
8560 assign clk2 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk2_tmp : 'bx;
8563 assign clk3_tmp = i_clk3_counter == "c0" ? c0_clk : i_clk3_counter == "c1" ? c1_clk : i_clk3_counter == "c2" ? c2_clk : i_clk3_counter == "c3" ? c3_clk : i_clk3_counter == "c4" ? c4_clk : i_clk3_counter == "c5" ? c5_clk : 'b0;
8565 assign clk3 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk3_tmp : 'bx;
8568 assign clk4_tmp = i_clk4_counter == "c0" ? c0_clk : i_clk4_counter == "c1" ? c1_clk : i_clk4_counter == "c2" ? c2_clk : i_clk4_counter == "c3" ? c3_clk : i_clk4_counter == "c4" ? c4_clk : i_clk4_counter == "c5" ? c5_clk : 'b0;
8570 assign clk4 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk4_tmp : 'bx;
8573 assign clk5_tmp = i_clk5_counter == "c0" ? c0_clk : i_clk5_counter == "c1" ? c1_clk : i_clk5_counter == "c2" ? c2_clk : i_clk5_counter == "c3" ? c3_clk : i_clk5_counter == "c4" ? c4_clk : i_clk5_counter == "c5" ? c5_clk : 'b0;
8575 assign clk5 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk5_tmp : 'bx;
8577 assign sclkout0 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode == 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? sclkout0_tmp : 1'bx;
8579 assign sclkout1 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode == 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? sclkout1_tmp : 1'bx;
8581 assign enable_0 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode == 1'b1) || pll_about_to_lock == 1'b1 ? enable0_tmp : 'bx;
8582 assign enable_1 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode == 1'b1) || pll_about_to_lock == 1'b1 ? enable1_tmp : 'bx;
8585 // ACCELERATE OUTPUTS
8586 and (clk[0], 1'b1, clk0);
8587 and (clk[1], 1'b1, clk1);
8588 and (clk[2], 1'b1, clk2);
8589 and (clk[3], 1'b1, clk3);
8590 and (clk[4], 1'b1, clk4);
8591 and (clk[5], 1'b1, clk5);
8593 and (sclkout[0], 1'b1, sclkout0);
8594 and (sclkout[1], 1'b1, sclkout1);
8596 and (enable0, 1'b1, enable_0);
8597 and (enable1, 1'b1, enable_1);
8599 and (scandataout, 1'b1, scandataout_tmp);
8600 and (scandone, 1'b1, scandone_tmp);
8602 endmodule // MF_stratixii_pll
8604 // START MODULE NAME -----------------------------------------------------------
8606 // Module Name : ALTPLL
8608 // Description : Phase-Locked Loop (PLL) behavioral model. Model supports basic
8609 // PLL features such as clock division and multiplication,
8610 // programmable duty cycle and phase shifts, various feedback modes
8611 // and clock delays. Also supports real-time reconfiguration of
8612 // PLL "parameters" and clock switchover between the 2 input
8613 // reference clocks. Up to 10 clock outputs may be used.
8615 // Limitations : Applicable to Stratix, Stratix-GX, Stratix II and Cyclone II device families only
8616 // There is no support in the model for spread-spectrum feature
8618 // Expected results : Up to 10 output clocks, each defined by its own set of
8619 // parameters. Locked output (active high) indicates when the
8620 // PLL locks. clkbad, clkloss and activeclock are used for
8621 // clock switchover to inidicate which input clock has gone
8622 // bad, when the clock switchover initiates and which input
8623 // clock is being used as the reference, respectively.
8624 // scandataout is the data output of the serial scan chain.
8626 //END MODULE NAME --------------------------------------------------------------
8628 `timescale 1 ps / 1ps
8630 // MODULE DECLARATION
8632 inclk, // input reference clock - up to 2 can be used
8633 fbin, // external feedback input port
8634 pllena, // PLL enable signal
8635 clkswitch, // switch between inclk0 and inclk1
8636 areset, // asynchronous reset
8637 pfdena, // enable the Phase Frequency Detector (PFD)
8638 clkena, // enable clk0 to clk5 clock outputs
8639 extclkena, // enable extclk0 to extclk3 clock outputs
8640 scanclk, // clock for the serial scan chain
8641 scanaclr, // asynchronous clear the serial scan chain
8642 scanread, // determines when the scan chain can read in data from the scandata port
8643 scanwrite, // determines when the scan chain can write out data into pll
8644 scandata, // data for the scan chain
8645 clk, // internal clock outputs (feeds the core)
8646 extclk, // external clock outputs (feeds pins)
8647 clkbad, // indicates if inclk0/inclk1 has gone bad
8648 enable0, // load enable pulse 0 for lvds
8649 enable1, // load enable pulse l for lvds
8650 activeclock, // indicates which input clock is being used
8651 clkloss, // indicates when clock switchover initiates
8652 locked, // indicates when the PLL locks onto the input clock
8653 scandataout, // data output of the serial scan chain
8654 scandone, // indicates when pll reconfiguration is complete
8655 sclkout0, // serial clock output 0 for lvds
8656 sclkout1 // serial clock output 1 for lvds
8659 // GLOBAL PARAMETER DECLARATION
8660 parameter intended_device_family = "Stratix" ;
8661 parameter operation_mode = "NORMAL" ;
8662 parameter pll_type = "AUTO" ;
8663 parameter qualify_conf_done = "OFF" ;
8664 parameter compensate_clock = "CLK0" ;
8665 parameter scan_chain = "LONG";
8666 parameter primary_clock = "inclk0";
8667 parameter inclk0_input_frequency = 1000;
8668 parameter inclk1_input_frequency = 0;
8669 parameter gate_lock_signal = "NO";
8670 parameter gate_lock_counter = 0;
8671 parameter lock_high = 1;
8672 parameter lock_low = 5;
8673 parameter valid_lock_multiplier = 1;
8674 parameter invalid_lock_multiplier = 5;
8675 parameter switch_over_type = "AUTO";
8676 parameter switch_over_on_lossclk = "OFF" ;
8677 parameter switch_over_on_gated_lock = "OFF" ;
8678 parameter enable_switch_over_counter = "OFF";
8679 parameter switch_over_counter = 0;
8680 parameter feedback_source = "EXTCLK0" ;
8681 parameter bandwidth = 0;
8682 parameter bandwidth_type = "UNUSED";
8683 parameter lpm_hint = "UNUSED";
8684 parameter spread_frequency = 0;
8685 parameter down_spread = "0.0";
8686 parameter self_reset_on_gated_loss_lock = "OFF";
8688 // simulation-only parameters
8689 parameter simulation_type = "functional";
8690 parameter source_is_pll = "off";
8692 parameter skip_vco = "off";
8694 // internal clock specifications
8695 parameter clk5_multiply_by = 1;
8696 parameter clk4_multiply_by = 1;
8697 parameter clk3_multiply_by = 1;
8698 parameter clk2_multiply_by = 1;
8699 parameter clk1_multiply_by = 1;
8700 parameter clk0_multiply_by = 1;
8701 parameter clk5_divide_by = 1;
8702 parameter clk4_divide_by = 1;
8703 parameter clk3_divide_by = 1;
8704 parameter clk2_divide_by = 1;
8705 parameter clk1_divide_by = 1;
8706 parameter clk0_divide_by = 1;
8707 parameter clk5_phase_shift = "0";
8708 parameter clk4_phase_shift = "0";
8709 parameter clk3_phase_shift = "0";
8710 parameter clk2_phase_shift = "0";
8711 parameter clk1_phase_shift = "0";
8712 parameter clk0_phase_shift = "0";
8714 parameter clk5_time_delay = "0"; // For stratix pll use only
8715 parameter clk4_time_delay = "0"; // For stratix pll use only
8716 parameter clk3_time_delay = "0"; // For stratix pll use only
8717 parameter clk2_time_delay = "0"; // For stratix pll use only
8718 parameter clk1_time_delay = "0"; // For stratix pll use only
8719 parameter clk0_time_delay = "0"; // For stratix pll use only
8720 parameter clk5_duty_cycle = 50;
8721 parameter clk4_duty_cycle = 50;
8722 parameter clk3_duty_cycle = 50;
8723 parameter clk2_duty_cycle = 50;
8724 parameter clk1_duty_cycle = 50;
8725 parameter clk0_duty_cycle = 50;
8727 parameter clk2_output_frequency = 0;
8728 parameter clk1_output_frequency = 0;
8729 parameter clk0_output_frequency = 0;
8731 // external clock specifications (for stratix pll use only)
8732 parameter extclk3_multiply_by = 1;
8733 parameter extclk2_multiply_by = 1;
8734 parameter extclk1_multiply_by = 1;
8735 parameter extclk0_multiply_by = 1;
8736 parameter extclk3_divide_by = 1;
8737 parameter extclk2_divide_by = 1;
8738 parameter extclk1_divide_by = 1;
8739 parameter extclk0_divide_by = 1;
8740 parameter extclk3_phase_shift = "0";
8741 parameter extclk2_phase_shift = "0";
8742 parameter extclk1_phase_shift = "0";
8743 parameter extclk0_phase_shift = "0";
8744 parameter extclk3_time_delay = "0";
8745 parameter extclk2_time_delay = "0";
8746 parameter extclk1_time_delay = "0";
8747 parameter extclk0_time_delay = "0";
8748 parameter extclk3_duty_cycle = 50;
8749 parameter extclk2_duty_cycle = 50;
8750 parameter extclk1_duty_cycle = 50;
8751 parameter extclk0_duty_cycle = 50;
8753 // The following 4 parameters are for Stratix II pll in lvds mode only
8754 parameter vco_multiply_by = 0;
8755 parameter vco_divide_by = 0;
8756 parameter sclkout0_phase_shift = "0";
8757 parameter sclkout1_phase_shift = "0";
8759 // advanced user parameters
8760 parameter vco_min = 0;
8761 parameter vco_max = 0;
8762 parameter vco_center = 0;
8763 parameter pfd_min = 0;
8764 parameter pfd_max = 0;
8765 parameter m_initial = 1;
8766 parameter m = 0; // m must default to 0 in order for altpll to calculate advanced parameters for itself
8771 parameter l0_high = 1;
8772 parameter l1_high = 1;
8773 parameter g0_high = 1;
8774 parameter g1_high = 1;
8775 parameter g2_high = 1;
8776 parameter g3_high = 1;
8777 parameter e0_high = 1;
8778 parameter e1_high = 1;
8779 parameter e2_high = 1;
8780 parameter e3_high = 1;
8781 parameter l0_low = 1;
8782 parameter l1_low = 1;
8783 parameter g0_low = 1;
8784 parameter g1_low = 1;
8785 parameter g2_low = 1;
8786 parameter g3_low = 1;
8787 parameter e0_low = 1;
8788 parameter e1_low = 1;
8789 parameter e2_low = 1;
8790 parameter e3_low = 1;
8791 parameter l0_initial = 1;
8792 parameter l1_initial = 1;
8793 parameter g0_initial = 1;
8794 parameter g1_initial = 1;
8795 parameter g2_initial = 1;
8796 parameter g3_initial = 1;
8797 parameter e0_initial = 1;
8798 parameter e1_initial = 1;
8799 parameter e2_initial = 1;
8800 parameter e3_initial = 1;
8801 parameter l0_mode = "bypass";
8802 parameter l1_mode = "bypass";
8803 parameter g0_mode = "bypass";
8804 parameter g1_mode = "bypass";
8805 parameter g2_mode = "bypass";
8806 parameter g3_mode = "bypass";
8807 parameter e0_mode = "bypass";
8808 parameter e1_mode = "bypass";
8809 parameter e2_mode = "bypass";
8810 parameter e3_mode = "bypass";
8811 parameter l0_ph = 0;
8812 parameter l1_ph = 0;
8813 parameter g0_ph = 0;
8814 parameter g1_ph = 0;
8815 parameter g2_ph = 0;
8816 parameter g3_ph = 0;
8817 parameter e0_ph = 0;
8818 parameter e1_ph = 0;
8819 parameter e2_ph = 0;
8820 parameter e3_ph = 0;
8822 parameter l0_time_delay = 0;
8823 parameter l1_time_delay = 0;
8824 parameter g0_time_delay = 0;
8825 parameter g1_time_delay = 0;
8826 parameter g2_time_delay = 0;
8827 parameter g3_time_delay = 0;
8828 parameter e0_time_delay = 0;
8829 parameter e1_time_delay = 0;
8830 parameter e2_time_delay = 0;
8831 parameter e3_time_delay = 0;
8832 parameter m_time_delay = 0;
8833 parameter n_time_delay = 0;
8834 parameter extclk3_counter = "e3" ;
8835 parameter extclk2_counter = "e2" ;
8836 parameter extclk1_counter = "e1" ;
8837 parameter extclk0_counter = "e0" ;
8838 parameter clk5_counter = "l1" ;
8839 parameter clk4_counter = "l0" ;
8840 parameter clk3_counter = "g3" ;
8841 parameter clk2_counter = "g2" ;
8842 parameter clk1_counter = "g1" ;
8843 parameter clk0_counter = "g0" ;
8844 parameter enable0_counter = "l0";
8845 parameter enable1_counter = "l0";
8846 parameter charge_pump_current = 2;
8847 parameter loop_filter_r = "1.0";
8848 parameter loop_filter_c = 5;
8849 parameter vco_post_scale = 0;
8850 parameter lpm_type = "altpll";
8852 // The following parameter are used to define the connectivity for some of the input
8853 // and output ports.
8854 parameter port_clkena0 = "PORT_CONNECTIVITY";
8855 parameter port_clkena1 = "PORT_CONNECTIVITY";
8856 parameter port_clkena2 = "PORT_CONNECTIVITY";
8857 parameter port_clkena3 = "PORT_CONNECTIVITY";
8858 parameter port_clkena4 = "PORT_CONNECTIVITY";
8859 parameter port_clkena5 = "PORT_CONNECTIVITY";
8860 parameter port_extclkena0 = "PORT_CONNECTIVITY";
8861 parameter port_extclkena1 = "PORT_CONNECTIVITY";
8862 parameter port_extclkena2 = "PORT_CONNECTIVITY";
8863 parameter port_extclkena3 = "PORT_CONNECTIVITY";
8864 parameter port_extclk0 = "PORT_CONNECTIVITY";
8865 parameter port_extclk1 = "PORT_CONNECTIVITY";
8866 parameter port_extclk2 = "PORT_CONNECTIVITY";
8867 parameter port_extclk3 = "PORT_CONNECTIVITY";
8868 parameter port_clk0 = "PORT_CONNECTIVITY";
8869 parameter port_clk1 = "PORT_CONNECTIVITY";
8870 parameter port_clk2 = "PORT_CONNECTIVITY";
8871 parameter port_clk3 = "PORT_CONNECTIVITY";
8872 parameter port_clk4 = "PORT_CONNECTIVITY";
8873 parameter port_clk5 = "PORT_CONNECTIVITY";
8874 parameter port_scandata = "PORT_CONNECTIVITY";
8875 parameter port_scandataout = "PORT_CONNECTIVITY";
8876 parameter port_scandone = "PORT_CONNECTIVITY";
8877 parameter port_sclkout1 = "PORT_CONNECTIVITY";
8878 parameter port_sclkout0 = "PORT_CONNECTIVITY";
8879 parameter port_clkbad0 = "PORT_CONNECTIVITY";
8880 parameter port_clkbad1 = "PORT_CONNECTIVITY";
8881 parameter port_activeclock = "PORT_CONNECTIVITY";
8882 parameter port_clkloss = "PORT_CONNECTIVITY";
8883 parameter port_inclk1 = "PORT_CONNECTIVITY";
8884 parameter port_inclk0 = "PORT_CONNECTIVITY";
8885 parameter port_fbin = "PORT_CONNECTIVITY";
8886 parameter port_pllena = "PORT_CONNECTIVITY";
8887 parameter port_clkswitch = "PORT_CONNECTIVITY";
8888 parameter port_areset = "PORT_CONNECTIVITY";
8889 parameter port_pfdena = "PORT_CONNECTIVITY";
8890 parameter port_scanclk = "PORT_CONNECTIVITY";
8891 parameter port_scanaclr = "PORT_CONNECTIVITY";
8892 parameter port_scanread = "PORT_CONNECTIVITY";
8893 parameter port_scanwrite = "PORT_CONNECTIVITY";
8894 parameter port_enable0 = "PORT_CONNECTIVITY";
8895 parameter port_enable1 = "PORT_CONNECTIVITY";
8897 //For Stratixii pll use only
8898 parameter c0_high = 1;
8899 parameter c1_high = 1;
8900 parameter c2_high = 1;
8901 parameter c3_high = 1;
8902 parameter c4_high = 1;
8903 parameter c5_high = 1;
8904 parameter c0_low = 1;
8905 parameter c1_low = 1;
8906 parameter c2_low = 1;
8907 parameter c3_low = 1;
8908 parameter c4_low = 1;
8909 parameter c5_low = 1;
8910 parameter c0_initial = 1;
8911 parameter c1_initial = 1;
8912 parameter c2_initial = 1;
8913 parameter c3_initial = 1;
8914 parameter c4_initial = 1;
8915 parameter c5_initial = 1;
8916 parameter c0_mode = "bypass";
8917 parameter c1_mode = "bypass";
8918 parameter c2_mode = "bypass";
8919 parameter c3_mode = "bypass";
8920 parameter c4_mode = "bypass";
8921 parameter c5_mode = "bypass";
8922 parameter c0_ph = 0;
8923 parameter c1_ph = 0;
8924 parameter c2_ph = 0;
8925 parameter c3_ph = 0;
8926 parameter c4_ph = 0;
8927 parameter c5_ph = 0;
8928 parameter c1_use_casc_in = "off";
8929 parameter c2_use_casc_in = "off";
8930 parameter c3_use_casc_in = "off";
8931 parameter c4_use_casc_in = "off";
8932 parameter c5_use_casc_in = "off";
8933 parameter m_test_source = 5;
8934 parameter c0_test_source = 5;
8935 parameter c1_test_source = 5;
8936 parameter c2_test_source = 5;
8937 parameter c3_test_source = 5;
8938 parameter c4_test_source = 5;
8939 parameter c5_test_source = 5;
8941 // INPUT PORT DECLARATION
8949 input [3:0] extclkena;
8956 // OUTPUT PORT DECLARATION
8958 output [3:0] extclk;
8959 output [1:0] clkbad;
8974 tri1 [5:0] clkena_pullup;
8975 tri1 [3:0] extclkena_pullup;
8978 tri0 [1:0] inclk_pulldown;
8979 tri0 clkswitch_pulldown;
8980 tri0 areset_pulldown;
8981 tri0 scanclk_pulldown;
8982 tri0 scanclr_pulldown;
8983 tri0 scanread_pulldown;
8984 tri0 scanwrite_pulldown;
8985 tri0 scandata_pulldown;
8986 tri0 comparator_pulldown;
8988 // For fast mode, the stratix pll atom model will give active low signal on locked output.
8989 // Therefore, need to invert the lock signal for fast mode as in user view, locked signal is
8990 // always active high.
8992 wire [1:0] stratix_inclk;
8995 wire stratix_clkswitch;
8996 wire stratix_areset;
8997 wire stratix_pfdena;
8998 wire [5:0] stratix_clkena;
8999 wire [3:0] stratix_extclkena;
9000 wire stratix_scanclk;
9001 wire stratix_scanclr;
9002 wire stratix_scandata;
9003 wire [5:0] stratix_clk;
9004 wire [3:0] stratix_extclk;
9005 wire [1:0] stratix_clkbad;
9006 wire stratix_activeclock;
9007 wire stratix_locked;
9008 wire stratix_clkloss;
9009 wire stratix_scandataout;
9010 wire stratix_enable0;
9011 wire stratix_enable1;
9013 wire [1:0] stratixii_inclk;
9014 wire stratixii_fbin;
9016 wire stratixii_clkswitch;
9017 wire stratixii_areset;
9018 wire stratixii_pfdena;
9019 wire stratixii_scanread;
9020 wire stratixii_scanwrite;
9021 wire stratixii_scanclk;
9022 wire stratixii_scandata;
9023 wire stratixii_scandone;
9024 wire [5:0] stratixii_clk;
9025 wire [1:0] stratixii_clkbad;
9026 wire stratixii_activeclock;
9027 wire stratixii_locked;
9028 wire stratixii_clkloss;
9029 wire stratixii_scandataout;
9030 wire stratixii_enable0;
9031 wire stratixii_enable1;
9032 wire stratixii_sclkout0;
9033 wire stratixii_sclkout1;
9036 wire[1:0] clkbad_wire;
9037 wire activeclock_wire;
9039 wire scandataout_wire;
9044 ALTERA_DEVICE_FAMILIES dev ();
9050 // Begin of parameter checking
9052 if (clk5_multiply_by <= 0)
9054 $display("ERROR: The clk5_multiply_by must be greater than 0");
9058 if (clk4_multiply_by <= 0)
9060 $display("ERROR: The clk4_multiply_by must be greater than 0");
9064 if (clk3_multiply_by <= 0)
9066 $display("ERROR: The clk3_multiply_by must be greater than 0");
9071 if (clk2_multiply_by <= 0)
9073 $display("ERROR: The clk2_multiply_by must be greater than 0");
9077 if (clk1_multiply_by <= 0)
9079 $display("ERROR: The clk1_multiply_by must be greater than 0");
9083 if (clk0_multiply_by <= 0)
9085 $display("ERROR: The clk0_multiply_by must be greater than 0");
9089 if (clk5_divide_by <= 0)
9091 $display("ERROR: The clk5_divide_by must be greater than 0");
9096 if (clk4_divide_by <= 0)
9098 $display("ERROR: The clk4_divide_by must be greater than 0");
9103 if (clk3_divide_by <= 0)
9105 $display("ERROR: The clk3_divide_by must be greater than 0");
9110 if (clk2_divide_by <= 0)
9112 $display("ERROR: The clk2_divide_by must be greater than 0");
9117 if (clk1_divide_by <= 0)
9119 $display("ERROR: The clk1_divide_by must be greater than 0");
9124 if (clk0_divide_by <= 0)
9126 $display("ERROR: The clk0_divide_by must be greater than 0");
9130 if (extclk3_multiply_by <= 0)
9132 $display("ERROR: The extclk3_multiply_by must be greater than 0");
9136 if (extclk2_multiply_by <= 0)
9138 $display("ERROR: The extclk2_multiply_by must be greater than 0");
9142 if (extclk1_multiply_by <= 0)
9144 $display("ERROR: The extclk1_multiply_by must be greater than 0");
9148 if (extclk0_multiply_by <= 0)
9150 $display("ERROR: The extclk0_multiply_by must be greater than 0");
9155 if (extclk3_divide_by <= 0)
9157 $display("ERROR: The extclk3_divide_by must be greater than 0");
9162 if (extclk2_divide_by <= 0)
9164 $display("ERROR: The extclk2_divide_by must be greater than 0");
9169 if (extclk1_divide_by <= 0)
9171 $display("ERROR: The extclk1_divide_by must be greater than 0");
9176 if (extclk0_divide_by <= 0)
9178 $display("ERROR: The extclk0_divide_by must be greater than 0");
9182 if (!((primary_clock == "inclk0") || (primary_clock == "INCLK0") ||
9183 (primary_clock == "inclk1") || (primary_clock == "INCLK1")))
9185 $display("ERROR: The primary clock is set to an illegal value");
9189 if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
9191 $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
9194 // End of parameter checking
9198 // COMPONENT INSTANTIATION
9201 .inclk (stratix_inclk),
9202 .fbin (stratix_fbin),
9204 .clkswitch (stratix_clkswitch),
9205 .areset (stratix_areset),
9206 .pfdena (stratix_pfdena),
9207 .clkena (stratix_clkena),
9208 .extclkena (stratix_extclkena),
9209 .scanclk (stratix_scanclk),
9210 .scanaclr (stratix_scanclr),
9211 .scandata (stratix_scandata),
9214 .extclk (stratix_extclk),
9215 .clkbad (stratix_clkbad),
9216 .activeclock (stratix_activeclock),
9217 .locked (locked_tmp),
9218 .clkloss (stratix_clkloss),
9219 .scandataout (stratix_scandataout),
9220 .enable0 (stratix_enable0),
9221 .enable1 (stratix_enable1)
9224 pll0.operation_mode = operation_mode,
9225 pll0.pll_type = pll_type,
9226 pll0.qualify_conf_done = qualify_conf_done,
9227 pll0.compensate_clock = compensate_clock,
9228 pll0.scan_chain = scan_chain,
9229 pll0.primary_clock = primary_clock,
9230 pll0.inclk0_input_frequency = inclk0_input_frequency,
9231 pll0.inclk1_input_frequency = inclk1_input_frequency,
9232 pll0.gate_lock_signal = gate_lock_signal,
9233 pll0.gate_lock_counter = gate_lock_counter,
9234 pll0.valid_lock_multiplier = valid_lock_multiplier,
9235 pll0.invalid_lock_multiplier = invalid_lock_multiplier,
9236 pll0.switch_over_on_lossclk = switch_over_on_lossclk,
9237 pll0.switch_over_on_gated_lock = switch_over_on_gated_lock,
9238 pll0.enable_switch_over_counter = enable_switch_over_counter,
9239 pll0.switch_over_counter = switch_over_counter,
9240 pll0.feedback_source = feedback_source,
9241 pll0.bandwidth = bandwidth,
9242 pll0.bandwidth_type = bandwidth_type,
9243 pll0.spread_frequency = spread_frequency,
9244 pll0.down_spread = down_spread,
9245 pll0.simulation_type = simulation_type,
9246 pll0.skip_vco = skip_vco,
9248 // internal clock specifications
9249 pll0.clk5_multiply_by = clk5_multiply_by,
9250 pll0.clk4_multiply_by = clk4_multiply_by,
9251 pll0.clk3_multiply_by = clk3_multiply_by,
9252 pll0.clk2_multiply_by = clk2_multiply_by,
9253 pll0.clk1_multiply_by = clk1_multiply_by,
9254 pll0.clk0_multiply_by = clk0_multiply_by,
9255 pll0.clk5_divide_by = clk5_divide_by,
9256 pll0.clk4_divide_by = clk4_divide_by,
9257 pll0.clk3_divide_by = clk3_divide_by,
9258 pll0.clk2_divide_by = clk2_divide_by,
9259 pll0.clk1_divide_by = clk1_divide_by,
9260 pll0.clk0_divide_by = clk0_divide_by,
9261 pll0.clk5_phase_shift = clk5_phase_shift,
9262 pll0.clk4_phase_shift = clk4_phase_shift,
9263 pll0.clk3_phase_shift = clk3_phase_shift,
9264 pll0.clk2_phase_shift = clk2_phase_shift,
9265 pll0.clk1_phase_shift = clk1_phase_shift,
9266 pll0.clk0_phase_shift = clk0_phase_shift,
9267 pll0.clk5_time_delay = clk5_time_delay,
9268 pll0.clk4_time_delay = clk4_time_delay,
9269 pll0.clk3_time_delay = clk3_time_delay,
9270 pll0.clk2_time_delay = clk2_time_delay,
9271 pll0.clk1_time_delay = clk1_time_delay,
9272 pll0.clk0_time_delay = clk0_time_delay,
9273 pll0.clk5_duty_cycle = clk5_duty_cycle,
9274 pll0.clk4_duty_cycle = clk4_duty_cycle,
9275 pll0.clk3_duty_cycle = clk3_duty_cycle,
9276 pll0.clk2_duty_cycle = clk2_duty_cycle,
9277 pll0.clk1_duty_cycle = clk1_duty_cycle,
9278 pll0.clk0_duty_cycle = clk0_duty_cycle,
9280 // external clock specifications
9281 pll0.extclk3_multiply_by = extclk3_multiply_by,
9282 pll0.extclk2_multiply_by = extclk2_multiply_by,
9283 pll0.extclk1_multiply_by = extclk1_multiply_by,
9284 pll0.extclk0_multiply_by = extclk0_multiply_by,
9285 pll0.extclk3_divide_by = extclk3_divide_by,
9286 pll0.extclk2_divide_by = extclk2_divide_by,
9287 pll0.extclk1_divide_by = extclk1_divide_by,
9288 pll0.extclk0_divide_by = extclk0_divide_by,
9289 pll0.extclk3_phase_shift = extclk3_phase_shift,
9290 pll0.extclk2_phase_shift = extclk2_phase_shift,
9291 pll0.extclk1_phase_shift = extclk1_phase_shift,
9292 pll0.extclk0_phase_shift = extclk0_phase_shift,
9293 pll0.extclk3_time_delay = extclk3_time_delay,
9294 pll0.extclk2_time_delay = extclk2_time_delay,
9295 pll0.extclk1_time_delay = extclk1_time_delay,
9296 pll0.extclk0_time_delay = extclk0_time_delay,
9297 pll0.extclk3_duty_cycle = extclk3_duty_cycle,
9298 pll0.extclk2_duty_cycle = extclk2_duty_cycle,
9299 pll0.extclk1_duty_cycle = extclk1_duty_cycle,
9300 pll0.extclk0_duty_cycle = extclk0_duty_cycle,
9302 // advanced parameters
9303 pll0.vco_min = vco_min,
9304 pll0.vco_max = vco_max,
9305 pll0.vco_center = vco_center,
9306 pll0.pfd_min = pfd_min,
9307 pll0.pfd_max = pfd_max,
9308 pll0.m_initial = m_initial,
9314 pll0.l0_high = l0_high,
9315 pll0.l1_high = l1_high,
9316 pll0.g0_high = g0_high,
9317 pll0.g1_high = g1_high,
9318 pll0.g2_high = g2_high,
9319 pll0.g3_high = g3_high,
9320 pll0.e0_high = e0_high,
9321 pll0.e1_high = e1_high,
9322 pll0.e2_high = e2_high,
9323 pll0.e3_high = e3_high,
9324 pll0.l0_low = l0_low,
9325 pll0.l1_low = l1_low,
9326 pll0.g0_low = g0_low,
9327 pll0.g1_low = g1_low,
9328 pll0.g2_low = g2_low,
9329 pll0.g3_low = g3_low,
9330 pll0.e0_low = e0_low,
9331 pll0.e1_low = e1_low,
9332 pll0.e2_low = e2_low,
9333 pll0.e3_low = e3_low,
9334 pll0.l0_initial = l0_initial,
9335 pll0.l1_initial = l1_initial,
9336 pll0.g0_initial = g0_initial,
9337 pll0.g1_initial = g1_initial,
9338 pll0.g2_initial = g2_initial,
9339 pll0.g3_initial = g3_initial,
9340 pll0.e0_initial = e0_initial,
9341 pll0.e1_initial = e1_initial,
9342 pll0.e2_initial = e2_initial,
9343 pll0.e3_initial = e3_initial,
9344 pll0.l0_mode = l0_mode,
9345 pll0.l1_mode = l1_mode,
9346 pll0.g0_mode = g0_mode,
9347 pll0.g1_mode = g1_mode,
9348 pll0.g2_mode = g2_mode,
9349 pll0.g3_mode = g3_mode,
9350 pll0.e0_mode = e0_mode,
9351 pll0.e1_mode = e1_mode,
9352 pll0.e2_mode = e2_mode,
9353 pll0.e3_mode = e3_mode,
9365 pll0.l0_time_delay = l0_time_delay,
9366 pll0.l1_time_delay = l1_time_delay,
9367 pll0.g0_time_delay = g0_time_delay,
9368 pll0.g1_time_delay = g1_time_delay,
9369 pll0.g2_time_delay = g2_time_delay,
9370 pll0.g3_time_delay = g3_time_delay,
9371 pll0.e0_time_delay = e0_time_delay,
9372 pll0.e1_time_delay = e1_time_delay,
9373 pll0.e2_time_delay = e2_time_delay,
9374 pll0.e3_time_delay = e3_time_delay,
9375 pll0.m_time_delay = m_time_delay,
9376 pll0.n_time_delay = n_time_delay,
9377 pll0.extclk3_counter = extclk3_counter,
9378 pll0.extclk2_counter = extclk2_counter,
9379 pll0.extclk1_counter = extclk1_counter,
9380 pll0.extclk0_counter = extclk0_counter,
9381 pll0.clk5_counter = clk5_counter,
9382 pll0.clk4_counter = clk4_counter,
9383 pll0.clk3_counter = clk3_counter,
9384 pll0.clk2_counter = clk2_counter,
9385 pll0.clk1_counter = clk1_counter,
9386 pll0.clk0_counter = clk0_counter,
9387 pll0.enable0_counter = enable0_counter,
9388 pll0.enable1_counter = enable1_counter,
9389 pll0.charge_pump_current = charge_pump_current,
9390 pll0.loop_filter_r = loop_filter_r,
9391 pll0.loop_filter_c = loop_filter_c;
9393 MF_stratixii_pll pll1
9395 .inclk (stratixii_inclk),
9396 .fbin (stratixii_fbin),
9397 .ena (stratixii_ena),
9398 .clkswitch (stratixii_clkswitch),
9399 .areset (stratixii_areset),
9400 .pfdena (stratixii_pfdena),
9401 .scanclk (stratixii_scanclk),
9402 .scanread (stratixii_scanread),
9403 .scanwrite (stratixii_scanwrite),
9404 .scandata (stratixii_scandata),
9406 .scandone (stratixii_scandone),
9407 .clk (stratixii_clk),
9408 .clkbad (stratixii_clkbad),
9409 .activeclock (stratixii_activeclock),
9410 .locked (stratixii_locked),
9411 .clkloss (stratixii_clkloss),
9412 .scandataout (stratixii_scandataout),
9413 .enable0 (stratixii_enable0),
9414 .enable1 (stratixii_enable1),
9417 .sclkout({stratixii_sclkout1, stratixii_sclkout0})
9420 pll1.operation_mode = operation_mode,
9421 pll1.pll_type = pll_type,
9422 pll1.qualify_conf_done = qualify_conf_done,
9423 pll1.compensate_clock = compensate_clock,
9424 pll1.inclk0_input_frequency = inclk0_input_frequency,
9425 pll1.inclk1_input_frequency = inclk1_input_frequency,
9426 pll1.gate_lock_signal = gate_lock_signal,
9427 pll1.gate_lock_counter = gate_lock_counter,
9428 pll1.valid_lock_multiplier = valid_lock_multiplier,
9429 pll1.invalid_lock_multiplier = invalid_lock_multiplier,
9430 pll1.switch_over_type = switch_over_type,
9431 pll1.switch_over_on_lossclk = switch_over_on_lossclk,
9432 pll1.switch_over_on_gated_lock = switch_over_on_gated_lock,
9433 pll1.enable_switch_over_counter = enable_switch_over_counter,
9434 pll1.switch_over_counter = switch_over_counter,
9435 pll1.feedback_source = (feedback_source == "EXTCLK0") ? "CLK0" : feedback_source,
9436 pll1.bandwidth = bandwidth,
9437 pll1.bandwidth_type = bandwidth_type,
9438 pll1.spread_frequency = spread_frequency,
9439 pll1.down_spread = down_spread,
9440 pll1.self_reset_on_gated_loss_lock = self_reset_on_gated_loss_lock,
9441 pll1.simulation_type = simulation_type,
9443 // internal clock specifications
9444 pll1.clk5_multiply_by = clk5_multiply_by,
9445 pll1.clk4_multiply_by = clk4_multiply_by,
9446 pll1.clk3_multiply_by = clk3_multiply_by,
9447 pll1.clk2_multiply_by = clk2_multiply_by,
9448 pll1.clk1_multiply_by = clk1_multiply_by,
9449 pll1.clk0_multiply_by = clk0_multiply_by,
9450 pll1.clk5_divide_by = clk5_divide_by,
9451 pll1.clk4_divide_by = clk4_divide_by,
9452 pll1.clk3_divide_by = clk3_divide_by,
9453 pll1.clk2_divide_by = clk2_divide_by,
9454 pll1.clk1_divide_by = clk1_divide_by,
9455 pll1.clk0_divide_by = clk0_divide_by,
9456 pll1.clk5_phase_shift = clk5_phase_shift,
9457 pll1.clk4_phase_shift = clk4_phase_shift,
9458 pll1.clk3_phase_shift = clk3_phase_shift,
9459 pll1.clk2_phase_shift = clk2_phase_shift,
9460 pll1.clk1_phase_shift = clk1_phase_shift,
9461 pll1.clk0_phase_shift = clk0_phase_shift,
9462 pll1.clk5_duty_cycle = clk5_duty_cycle,
9463 pll1.clk4_duty_cycle = clk4_duty_cycle,
9464 pll1.clk3_duty_cycle = clk3_duty_cycle,
9465 pll1.clk2_duty_cycle = clk2_duty_cycle,
9466 pll1.clk1_duty_cycle = clk1_duty_cycle,
9467 pll1.clk0_duty_cycle = clk0_duty_cycle,
9468 pll1.vco_multiply_by = vco_multiply_by,
9469 pll1.vco_divide_by = vco_divide_by,
9470 pll1.clk2_output_frequency = clk2_output_frequency,
9471 pll1.clk1_output_frequency = clk1_output_frequency,
9472 pll1.clk0_output_frequency = clk0_output_frequency,
9474 // advanced parameters
9475 pll1.vco_min = vco_min,
9476 pll1.vco_max = vco_max,
9477 pll1.vco_center = vco_center,
9478 pll1.pfd_min = pfd_min,
9479 pll1.pfd_max = pfd_max,
9480 pll1.m_initial = m_initial,
9486 pll1.c0_high = c0_high,
9487 pll1.c1_high = c1_high,
9488 pll1.c2_high = c2_high,
9489 pll1.c3_high = c3_high,
9490 pll1.c4_high = c4_high,
9491 pll1.c5_high = c5_high,
9492 pll1.c0_low = c0_low,
9493 pll1.c1_low = c1_low,
9494 pll1.c2_low = c2_low,
9495 pll1.c3_low = c3_low,
9496 pll1.c4_low = c4_low,
9497 pll1.c5_low = c5_low,
9498 pll1.c0_initial = c0_initial,
9499 pll1.c1_initial = c1_initial,
9500 pll1.c2_initial = c2_initial,
9501 pll1.c3_initial = c3_initial,
9502 pll1.c4_initial = c4_initial,
9503 pll1.c5_initial = c5_initial,
9504 pll1.c0_mode = c0_mode,
9505 pll1.c1_mode = c1_mode,
9506 pll1.c2_mode = c2_mode,
9507 pll1.c3_mode = c3_mode,
9508 pll1.c4_mode = c4_mode,
9509 pll1.c5_mode = c5_mode,
9517 pll1.c1_use_casc_in = c1_use_casc_in,
9518 pll1.c2_use_casc_in = c2_use_casc_in,
9519 pll1.c3_use_casc_in = c3_use_casc_in,
9520 pll1.c4_use_casc_in = c4_use_casc_in,
9521 pll1.c5_use_casc_in = c5_use_casc_in,
9522 pll1.clk5_counter = (clk5_counter == "l1") ? "c5" : clk5_counter,
9523 pll1.clk4_counter = (clk4_counter == "l0") ? "c4" : clk4_counter,
9524 pll1.clk3_counter = (clk3_counter == "g3") ? "c3" : clk3_counter,
9525 pll1.clk2_counter = (clk2_counter == "g2") ? "c2" : clk2_counter,
9526 pll1.clk1_counter = (clk1_counter == "g1") ? "c1" : clk1_counter,
9527 pll1.clk0_counter = (clk0_counter == "g0") ? "c0" : clk0_counter,
9528 pll1.enable0_counter = (enable0_counter == "l0") ? "c0" : enable0_counter,
9529 pll1.enable1_counter = (enable1_counter == "l0") ? "c1" : enable1_counter,
9530 pll1.charge_pump_current = charge_pump_current,
9531 pll1.loop_filter_r = loop_filter_r,
9532 pll1.loop_filter_c = loop_filter_c,
9533 pll1.m_test_source = m_test_source,
9534 pll1.c0_test_source = c0_test_source,
9535 pll1.c1_test_source = c1_test_source,
9536 pll1.c2_test_source = c2_test_source,
9537 pll1.c3_test_source = c3_test_source,
9538 pll1.c4_test_source = c4_test_source,
9539 pll1.c5_test_source = c5_test_source;
9541 // CONTINOUS ASSIGNMENT
9542 assign fbin_pullup = ((port_fbin == "PORT_CONNECTIVITY") ||
9543 (port_fbin == "PORT_USED")) ? fbin : 1'b1;
9544 assign ena_pullup = ((port_pllena == "PORT_CONNECTIVITY") ||
9545 (port_pllena == "PORT_USED")) ? pllena : 1'b1;
9546 assign pfdena_pullup = ((port_pfdena == "PORT_CONNECTIVITY") ||
9547 (port_pfdena == "PORT_USED")) ? pfdena : 1'b1;
9548 assign clkena_pullup[0] = (!((pll_type == "fast") || (pll_type == "FAST")) ||
9549 (port_clkena0 == "PORT_USED")) &&
9550 (port_clkena0 != "PORT_UNUSED") ? clkena[0] : 1'b1;
9551 assign clkena_pullup[1] = (!((pll_type == "fast") || (pll_type == "FAST")) ||
9552 (port_clkena1 == "PORT_USED")) &&
9553 (port_clkena1 != "PORT_UNUSED") ? clkena[1] : 1'b1;
9554 assign clkena_pullup[2] = (!((pll_type == "fast") || (pll_type == "FAST")) ||
9555 (port_clkena2 == "PORT_USED")) &&
9556 (port_clkena2 != "PORT_UNUSED") ? clkena[2] : 1'b1;
9557 assign clkena_pullup[3] = (!((pll_type == "fast") || (pll_type == "FAST")) ||
9558 (port_clkena3 == "PORT_USED")) &&
9559 (port_clkena3 != "PORT_UNUSED") ? clkena[3] : 1'b1;
9560 assign clkena_pullup[4] = (!((pll_type == "fast") || (pll_type == "FAST")) ||
9561 (port_clkena4 == "PORT_USED")) &&
9562 (port_clkena4 != "PORT_UNUSED") ? clkena[4] : 1'b1;
9563 assign clkena_pullup[5] = (!((pll_type == "fast") || (pll_type == "FAST")) ||
9564 (port_clkena5 == "PORT_USED")) &&
9565 (port_clkena5 != "PORT_UNUSED") ? clkena[5] : 1'b1;
9567 assign extclkena_pullup[0] = (!((pll_type == "fast") || (pll_type == "FAST")) ||
9568 (port_extclkena0 == "PORT_USED")) &&
9569 (port_extclkena0 != "PORT_UNUSED") ? extclkena[0] : 1'b1;
9570 assign extclkena_pullup[1] = (!((pll_type == "fast") || (pll_type == "FAST")) ||
9571 (port_extclkena1 == "PORT_USED")) &&
9572 (port_extclkena1 != "PORT_UNUSED") ? extclkena[1] : 1'b1;
9573 assign extclkena_pullup[2] = (!((pll_type == "fast") || (pll_type == "FAST")) ||
9574 (port_extclkena2 == "PORT_USED")) &&
9575 (port_extclkena2 != "PORT_UNUSED") ? extclkena[2] : 1'b1;
9576 assign extclkena_pullup[3] = (!((pll_type == "fast") || (pll_type == "FAST")) ||
9577 (port_extclkena3 == "PORT_USED")) &&
9578 (port_extclkena3 != "PORT_UNUSED") ? extclkena[3] : 1'b1;
9579 assign scanclk_pulldown = scanclk;
9580 assign scanread_pulldown = ((port_scanread == "PORT_CONNECTIVITY") ||
9581 (port_scanread == "PORT_USED")) ? scanread : 1'b0;
9582 assign scanwrite_pulldown = ((port_scanwrite == "PORT_CONNECTIVITY") ||
9583 (port_scanwrite == "PORT_USED")) ? scanwrite : 1'b0;
9584 assign scandata_pulldown = ((port_scandata == "PORT_CONNECTIVITY") ||
9585 (port_scandata == "PORT_USED")) ? scandata : 1'b0;
9586 assign inclk_pulldown = inclk;
9587 assign clkswitch_pulldown = ((port_clkswitch == "PORT_CONNECTIVITY") ||
9588 (port_clkswitch == "PORT_USED")) ? clkswitch : 1'b0;
9589 assign areset_pulldown = ((port_areset == "PORT_CONNECTIVITY") ||
9590 (port_areset == "PORT_USED")) ? areset : 1'b0;
9591 assign scanclr_pulldown = ((port_scanaclr == "PORT_CONNECTIVITY") ||
9592 (port_scanaclr == "PORT_USED")) ? scanaclr : 1'b0;
9594 assign stratix_inclk = (!dev.FEATURE_FAMILY_STRATIXII(intended_device_family) &&
9595 !dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? inclk_pulldown : {2{1'b0}};
9596 assign stratix_fbin = (!dev.FEATURE_FAMILY_STRATIXII(intended_device_family) &&
9597 !dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? fbin_pullup : 1'b0;
9598 assign stratix_ena = (!dev.FEATURE_FAMILY_STRATIXII(intended_device_family) &&
9599 !dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? ena_pullup : 1'b0;
9600 assign stratix_clkswitch = (!dev.FEATURE_FAMILY_STRATIXII(intended_device_family) &&
9601 !dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? clkswitch_pulldown : 1'b0;
9602 assign stratix_areset = (!dev.FEATURE_FAMILY_STRATIXII(intended_device_family) &&
9603 !dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? areset_pulldown : 1'b0;
9604 assign stratix_pfdena = (!dev.FEATURE_FAMILY_STRATIXII(intended_device_family) &&
9605 !dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? pfdena_pullup : 1'b1;
9606 assign stratix_clkena = (!dev.FEATURE_FAMILY_STRATIXII(intended_device_family) &&
9607 !dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? clkena_pullup : {5{1'b0}};
9608 assign stratix_extclkena = (!dev.FEATURE_FAMILY_STRATIXII(intended_device_family) &&
9609 !dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? extclkena_pullup : {3{1'b0}};
9610 assign stratix_scanclk = (!dev.FEATURE_FAMILY_STRATIXII(intended_device_family) &&
9611 !dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? scanclk_pulldown : 1'b0;
9612 assign stratix_scanclr = (!dev.FEATURE_FAMILY_STRATIXII(intended_device_family) &&
9613 !dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? scanclr_pulldown : 1'b0;
9614 assign stratix_scandata = (!dev.FEATURE_FAMILY_STRATIXII(intended_device_family) &&
9615 !dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? scandata_pulldown : 1'b0;
9616 assign stratixii_inclk = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) ||
9617 dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? inclk_pulldown : {2{1'b0}};
9618 assign stratixii_fbin = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? fbin_pullup : 1'b0;
9619 assign stratixii_ena = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) ||
9620 dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? ena_pullup : 1'b0;
9621 assign stratixii_clkswitch = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) ||
9622 dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? clkswitch_pulldown : 1'b0;
9623 assign stratixii_areset = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) ||
9624 dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? areset_pulldown : 1'b0;
9625 assign stratixii_pfdena = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) ||
9626 dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? pfdena_pullup : 1'b1;
9627 assign stratixii_scanread = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? scanread_pulldown : 1'b0;
9628 assign stratixii_scanwrite = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? scanwrite_pulldown : 1'b0;
9629 assign stratixii_scanclk = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? scanclk_pulldown : 1'b0;
9630 assign stratixii_scandata = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? scandata_pulldown : 1'b0;
9631 assign scandone_wire = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? stratixii_scandone : 1'b0;
9632 assign scandone = (port_scandone != "PORT_UNUSED") ? scandone_wire : 1'b0;
9633 assign clk_wire = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? stratixii_clk :
9634 (dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? {3'b0, stratixii_clk[2:0]} : stratix_clk;
9635 assign clk[0] = (port_clk0 != "PORT_UNUSED") ? clk_wire[0] : 1'b0;
9636 assign clk[1] = (port_clk1 != "PORT_UNUSED") ? clk_wire[1] : 1'b0;
9637 assign clk[2] = (port_clk2 != "PORT_UNUSED") ? clk_wire[2] : 1'b0;
9638 assign clk[3] = (port_clk3 != "PORT_UNUSED") ? clk_wire[3] : 1'b0;
9639 assign clk[4] = (port_clk4 != "PORT_UNUSED") ? clk_wire[4] : 1'b0;
9640 assign clk[5] = (port_clk5 != "PORT_UNUSED") ? clk_wire[5] : 1'b0;
9641 assign extclk[0] = (port_extclk0 != "PORT_UNUSED") ? stratix_extclk[0] : 1'b0;
9642 assign extclk[1] = (port_extclk1 != "PORT_UNUSED") ? stratix_extclk[1] : 1'b0;
9643 assign extclk[2] = (port_extclk2 != "PORT_UNUSED") ? stratix_extclk[2] : 1'b0;
9644 assign extclk[3] = (port_extclk3 != "PORT_UNUSED") ? stratix_extclk[3] : 1'b0;
9645 assign clkbad_wire = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? stratixii_clkbad :
9646 (dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? 2'b0 : stratix_clkbad;
9647 assign clkbad[0] = (port_clkbad0 != "PORT_UNUSED") ? clkbad_wire[0] : 1'b0;
9648 assign clkbad[1] = (port_clkbad1 != "PORT_UNUSED") ? clkbad_wire[1] : 1'b0;
9649 assign activeclock_wire = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? stratixii_activeclock :
9650 (dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? 1'b0 : stratix_activeclock;
9651 assign activeclock = (port_activeclock != "PORT_UNUSED") ? activeclock_wire : 1'b0;
9652 assign locked = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) ||
9653 dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? stratixii_locked : stratix_locked;
9654 assign stratix_locked = ((pll_type == "fast") || (pll_type == "FAST")) ? (!locked_tmp) : locked_tmp;
9655 assign clkloss_wire = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? stratixii_clkloss :
9656 (dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? 1'b0 : stratix_clkloss;
9657 assign clkloss = (port_clkloss != "PORT_UNUSED") ? clkloss_wire : 1'b0;
9658 assign scandataout_wire = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? stratixii_scandataout :
9659 (dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? 1'b0 : stratix_scandataout;
9660 assign scandataout = (port_scandataout != "PORT_UNUSED") ? scandataout_wire : 1'b0;
9661 assign enable0 = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? stratixii_enable0 :
9662 (dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? 1'b0 : stratix_enable0;
9663 assign enable1 = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? stratixii_enable1 :
9664 (dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? 1'b0 : stratix_enable1;
9665 assign sclkout0_wire = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? stratixii_sclkout0 : 1'b0;
9666 assign sclkout0 = (port_sclkout0 != "PORT_UNUSED") ? sclkout0_wire : 1'b0;
9667 assign sclkout1_wire = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? stratixii_sclkout1 : 1'b0;
9668 assign sclkout1 = (port_sclkout1 != "PORT_UNUSED") ? sclkout1_wire : 1'b0;
9671 //START_MODULE_NAME------------------------------------------------------------
9673 // Module Name : altaccumulate
9675 // Description : Parameterized accumulator megafunction. The accumulator
9676 // performs an add function or a subtract function based on the add_sub
9677 // parameter. The input data can be signed or unsigned.
9681 // Results expected: result - The results of add or subtract operation. Output
9682 // port [width_out-1 .. 0] wide.
9683 // cout - The cout port has a physical interpretation as
9684 // the carry-out (borrow-in) of the MSB. The cout
9685 // port is most meaningful for detecting overflow
9686 // in unsigned operations. The cout port operates
9687 // in the same manner for signed and unsigned
9689 // overflow - Indicates the accumulator is overflow.
9691 //END_MODULE_NAME--------------------------------------------------------------
9693 // BEGINNING OF MODULE
9695 `timescale 1 ps / 1 ps
9697 module altaccumulate (cin, data, add_sub, clock, sload, clken, sign_data, aclr,
9698 result, cout, overflow);
9700 parameter width_in = 4; // Required
9701 parameter width_out = 8; // Required
9702 parameter lpm_representation = "UNSIGNED";
9703 parameter extra_latency = 0;
9704 parameter use_wys = "ON";
9705 parameter lpm_hint = "UNUSED";
9706 parameter lpm_type = "altaccumulate";
9708 // INPUT PORT DECLARATION
9710 input [width_in-1:0] data; // Required port
9711 input add_sub; // Default = 1
9712 input clock; // Required port
9713 input sload; // Default = 0
9714 input clken; // Default = 1
9715 input sign_data; // Default = 0
9716 input aclr; // Default = 0
9718 // OUTPUT PORT DECLARATION
9719 output [width_out-1:0] result; //Required port
9723 // INTERNAL REGISTERS DECLARATION
9724 reg [width_out:0] temp_sum;
9730 reg [width_out-1:0] result;
9731 reg [width_out+1:0] result_int;
9732 reg [(width_out - width_in) : 0] zeropad;
9737 reg [width_out-1:0] fb_int;
9738 reg [width_out -1:0] data_int;
9740 reg [width_out+1:0] result_pipe [extra_latency:0];
9741 reg [width_out+1:0] result_full;
9742 reg [width_out+1:0] result_full2;
9746 // INTERNAL WIRE DECLARATION
9747 wire [width_out:0] temp_sum_wire;
9750 wire cout_delayed_wire;
9751 wire overflow_int_wire;
9752 wire [width_out+1:0] result_int_wire;
9754 // INTERNAL TRI DECLARATION
9763 // LOCAL INTEGER DECLARATION
9767 // INITIAL CONSTRUCT BLOCK
9771 // Checking for invalid parameters
9774 $display("Error! Value of width_in parameter must be greater than 0.");
9778 if( width_out <= 0 )
9780 $display("Error! Value of width_out parameter must be greater than 0.");
9784 if( extra_latency > width_out )
9786 $display("Info: Value of extra_latency parameter should be lower than width_out parameter for better performance/utilization.");
9789 if( width_in > width_out )
9791 $display("Error! Value of width_in parameter should be lower than or equal to width_out.");
9800 for (i = 0; i <= extra_latency; i = i +1)
9802 result_pipe [i] = 0;
9806 // ALWAYS CONSTRUCT BLOCK
9807 always @(posedge clock or posedge aclr_int)
9816 for (i = 0; i <= extra_latency; i = i +1)
9818 result_pipe [i] = 0;
9826 //get result from output register
9827 if (extra_latency > 0)
9829 result_pipe [head] = {
9830 result_int [width_out+1],
9831 {cout_int_wire, result_int [width_out-1:0]}
9834 head = (head + 1) % (extra_latency);
9836 result_full = result_pipe [head];
9837 cout_delayed = result_full [width_out];
9838 result = result_full [width_out-1:0];
9839 overflow = result_full [width_out+1];
9843 result = temp_sum_wire;
9844 overflow = overflow_int_wire;
9847 result_int = {overflow_int_wire, {cout_int_wire, temp_sum_wire [width_out-1:0]}};
9853 always @ (data or cin or add_sub_int or sign_data_int or
9854 result_int_wire [width_out -1:0] or sload_int)
9857 if ((lpm_representation == "SIGNED") || (sign_data_int == 1))
9859 zeropad = (data [width_in-1] ==0) ? 0 : -1;
9866 fb_int = (sload_int == 1'b1) ? 0 : result_int_wire [width_out-1:0];
9867 data_int = {zeropad, data};
9869 if ((add_sub_int == 1) || (sload_int == 1))
9871 cin_int = ((sload_int == 1'b1) ? 0 : ((cin === 1'bz) ? 0 : cin));
9872 temp_sum = fb_int + data_int + cin_int;
9873 cout_int = temp_sum [width_out];
9877 cin_int = (cin === 1'bz) ? 1 : cin;
9880 temp_sum = fb_int - data_int - borrow;
9882 result_full2 = data_int + borrow;
9883 cout_int = (fb_int >= result_full2) ? 1 : 0;
9886 if ((lpm_representation == "SIGNED") || (sign_data_int == 1))
9888 a = (data [width_in-1] ~^ fb_int [width_out-1]) ^ (~add_sub_int);
9889 overflow_int = a & (fb_int [width_out-1] ^ temp_sum[width_out-1]);
9893 overflow_int = (add_sub_int == 1) ? cout_int : ~cout_int;
9898 cout_int = !add_sub_int;
9904 // CONTINOUS ASSIGNMENT
9906 // Get the input data and control signals.
9907 assign sign_data_int = sign_data;
9908 assign sload_int = sload;
9909 assign add_sub_int = add_sub;
9911 assign clken_int = clken;
9912 assign aclr_int = aclr;
9913 assign result_int_wire = result_int;
9914 assign temp_sum_wire = temp_sum;
9915 assign cout_int_wire = cout_int;
9916 assign overflow_int_wire = overflow_int;
9917 assign cout = (extra_latency == 0) ? cout_int_wire : cout_delayed_wire;
9918 assign cout_delayed_wire = cout_delayed;
9920 endmodule // End of altaccumulate
9924 //--------------------------------------------------------------------------
9925 // Module Name : altmult_accum
9927 // Description : a*b + x (MAC)
9929 // Limitation : Stratix DSP block
9931 // Results expected : signed & unsigned, maximum of 3 pipelines(latency) each.
9933 //--------------------------------------------------------------------------
9935 `timescale 1 ps / 1 ps
9937 module altmult_accum ( dataa,
9943 accum_sload_upper_data,
9969 accum_is_saturated);
9971 // ---------------------
9972 // PARAMETER DECLARATION
9973 // ---------------------
9974 parameter width_a = 2;
9975 parameter width_b = 2;
9976 parameter width_result = 5;
9977 parameter input_reg_a = "CLOCK0";
9978 parameter input_aclr_a = "ACLR3";
9979 parameter input_reg_b = "CLOCK0";
9980 parameter input_aclr_b = "ACLR3";
9981 parameter port_addnsub = "PORT_CONNECTIVITY";
9982 parameter addnsub_reg = "CLOCK0";
9983 parameter addnsub_aclr = "ACLR3";
9984 parameter addnsub_pipeline_reg = "CLOCK0";
9985 parameter addnsub_pipeline_aclr = "ACLR3";
9986 parameter accum_direction = "ADD";
9987 parameter accum_sload_reg = "CLOCK0";
9988 parameter accum_sload_aclr = "ACLR3";
9989 parameter accum_sload_pipeline_reg = "CLOCK0";
9990 parameter accum_sload_pipeline_aclr = "ACLR3";
9991 parameter representation_a = "UNSIGNED";
9992 parameter port_signa = "PORT_CONNECTIVITY";
9993 parameter sign_reg_a = "CLOCK0";
9994 parameter sign_aclr_a = "ACLR3";
9995 parameter sign_pipeline_reg_a = "CLOCK0";
9996 parameter sign_pipeline_aclr_a = "ACLR3";
9997 parameter port_signb = "PORT_CONNECTIVITY";
9998 parameter representation_b = "UNSIGNED";
9999 parameter sign_reg_b = "CLOCK0";
10000 parameter sign_aclr_b = "ACLR3";
10001 parameter sign_pipeline_reg_b = "CLOCK0";
10002 parameter sign_pipeline_aclr_b = "ACLR3";
10003 parameter multiplier_reg = "CLOCK0";
10004 parameter multiplier_aclr = "ACLR3";
10005 parameter output_reg = "CLOCK0";
10006 parameter output_aclr = "ACLR3";
10007 parameter lpm_type = "altmult_accum";
10008 parameter lpm_hint = "UNUSED";
10010 parameter extra_multiplier_latency = 0;
10011 parameter extra_accumulator_latency = 0;
10012 parameter dedicated_multiplier_circuitry = "AUTO";
10013 parameter dsp_block_balancing = "AUTO";
10014 parameter intended_device_family = "Stratix";
10016 // StratixII related parameter
10017 parameter accum_round_aclr = "ACLR3";
10018 parameter accum_round_pipeline_aclr = "ACLR3";
10019 parameter accum_round_pipeline_reg = "CLOCK0";
10020 parameter accum_round_reg = "CLOCK0";
10021 parameter accum_saturation_aclr = "ACLR3";
10022 parameter accum_saturation_pipeline_aclr = "ACLR3";
10023 parameter accum_saturation_pipeline_reg = "CLOCK0";
10024 parameter accum_saturation_reg = "CLOCK0";
10025 parameter accum_sload_upper_data_aclr = "ACLR3";
10026 parameter accum_sload_upper_data_pipeline_aclr = "ACLR3";
10027 parameter accum_sload_upper_data_pipeline_reg = "CLOCK0";
10028 parameter accum_sload_upper_data_reg = "CLOCK0";
10029 parameter mult_round_aclr = "ACLR3";
10030 parameter mult_round_reg = "CLOCK0";
10031 parameter mult_saturation_aclr = "ACLR3";
10032 parameter mult_saturation_reg = "CLOCK0";
10034 parameter input_source_a = "DATAA";
10035 parameter input_source_b = "DATAB";
10036 parameter width_upper_data = 1;
10037 parameter multiplier_rounding = "NO";
10038 parameter multiplier_saturation = "NO";
10039 parameter accumulator_rounding = "NO";
10040 parameter accumulator_saturation = "NO";
10041 parameter port_mult_is_saturated = "UNUSED";
10042 parameter port_accum_is_saturated = "UNUSED";
10044 // -----------------------
10045 // Local parameters
10046 // -----------------------
10047 parameter int_width_a = ((multiplier_saturation == "NO") && (multiplier_rounding == "NO") && (accumulator_saturation == "NO") && (accumulator_rounding == "NO")) ? width_a : 18;
10048 parameter int_width_b = ((multiplier_saturation == "NO") && (multiplier_rounding == "NO") && (accumulator_saturation == "NO") && (accumulator_rounding == "NO")) ? width_b : 18;
10049 parameter int_width_result = ((multiplier_saturation == "NO") && (multiplier_rounding == "NO") && (accumulator_saturation == "NO") && (accumulator_rounding == "NO")) ? width_result : 52;
10050 parameter int_extra_width = ((multiplier_saturation == "NO") && (multiplier_rounding == "NO") && (accumulator_saturation == "NO") && (accumulator_rounding == "NO")) ? 0 : (int_width_a + int_width_b - width_a - width_b);
10051 parameter diff_width_a = (int_width_a > width_a) ? int_width_a - width_a : 1;
10052 parameter diff_width_b = (int_width_b > width_b) ? int_width_b - width_b : 1;
10053 parameter sat_for_ini = ((multiplier_saturation == "NO") && (accumulator_saturation == "NO")) ? 0 : (int_width_a + int_width_b - 34);
10054 parameter mult_round_for_ini = ((multiplier_rounding == "NO")? 0 : (int_width_a + int_width_b - 18));
10055 parameter bits_to_round = (((multiplier_rounding == "NO") && (accumulator_rounding == "NO"))? 0 : int_width_a + int_width_b - 18);
10056 parameter sload_for_limit = (width_result < width_upper_data)? width_result + int_extra_width : width_upper_data ;
10057 parameter accum_sat_for_limit = ((accumulator_saturation == "NO")? int_width_result - 1 : int_width_a + int_width_b - 33 );
10058 // ----------------
10059 // PORT DECLARATION
10060 // ----------------
10062 // data input ports
10063 input [width_a -1 : 0] dataa;
10064 input [width_b -1 : 0] datab;
10065 input [width_a -1 : 0] scanina;
10066 input [width_b -1 : 0] scaninb;
10069 input [width_result -1 : width_result - width_upper_data] accum_sload_upper_data;
10083 // clock enable ports
10095 // round and saturate ports
10097 input mult_saturation;
10099 input accum_saturation;
10102 output [width_result -1 : 0] result;
10104 output [width_a -1 : 0] scanouta;
10105 output [width_b -1 : 0] scanoutb;
10107 output mult_is_saturated;
10108 output accum_is_saturated;
10114 reg [width_result -1 : 0] result;
10116 reg [int_width_result -1 : 0] mult_res_out;
10117 reg [int_width_result : 0] temp_sum;
10120 reg [width_result + 1 : 0] result_pipe [extra_accumulator_latency : 0];
10121 reg [width_result + 1 : 0] result_full ;
10123 reg [int_width_result - 1 : 0] result_int;
10125 reg [int_width_a - 1 : 0] mult_a_reg;
10126 reg [int_width_a - 1 : 0] mult_a_int;
10127 reg [int_width_a + int_width_b - 1 : 0] mult_res;
10128 reg [int_width_a + int_width_b - 1 : 0] temp_mult_1;
10129 reg [int_width_a + int_width_b - 1 : 0] temp_mult;
10132 reg [int_width_b -1 :0] mult_b_reg;
10133 reg [int_width_b -1 :0] mult_b_int;
10135 reg [5 + int_width_a + int_width_b + width_upper_data : 0] mult_pipe [extra_multiplier_latency:0];
10136 reg [5 + int_width_a + int_width_b + width_upper_data : 0] mult_full;
10138 reg [width_upper_data - 1 : 0] sload_upper_data_reg;
10140 reg [width_result - width_upper_data -1 + 4 : 0] lower_bits;
10142 reg mult_signed_out;
10143 reg [width_upper_data - 1 : 0] sload_upper_data_pipe_reg;
10147 reg zero_acc_pipe_reg;
10149 reg sign_a_pipe_reg;
10151 reg sign_b_pipe_reg;
10153 reg addsub_pipe_reg;
10156 reg temp_mult_signed;
10162 reg overflow_tmp_int;
10166 reg [int_width_a + int_width_b -1 : 0] mult_round_out;
10167 reg mult_saturate_overflow;
10168 reg [int_width_a + int_width_b -1 : 0] mult_saturate_out;
10169 reg [int_width_a + int_width_b -1 : 0] mult_result;
10170 reg [int_width_a + int_width_b -1 : 0] mult_final_out;
10172 reg [int_width_result -1 : 0] accum_round_out;
10173 reg accum_saturate_overflow;
10174 reg [int_width_result -1 : 0] accum_saturate_out;
10175 reg [int_width_result -1 : 0] accum_result;
10176 reg [int_width_result -1 : 0] accum_final_out;
10178 tri0 mult_is_saturated_latent;
10179 reg mult_is_saturated_int;
10180 reg mult_is_saturated_reg;
10182 reg accum_is_saturated_latent;
10183 reg [extra_accumulator_latency : 0] accum_saturate_pipe;
10184 reg [extra_accumulator_latency : 0] mult_is_saturated_pipe;
10186 reg mult_round_tmp;
10187 reg mult_saturation_tmp;
10188 reg accum_round_tmp1;
10189 reg accum_round_tmp2;
10190 reg accum_saturation_tmp1;
10191 reg accum_saturation_tmp2;
10193 reg [int_width_result - int_width_a - int_width_b + 2 - 1 : 0] accum_result_sign_bits;
10195 // -------------------
10196 // INTEGER DECLARATION
10197 // -------------------
10198 integer head_result;
10207 //-----------------
10209 //-----------------
10212 // Tri wire for clear signal
10214 tri0 input_a_wire_clr;
10215 tri0 input_b_wire_clr;
10217 tri0 addsub_wire_clr;
10218 tri0 addsub_pipe_wire_clr;
10220 tri0 zero_wire_clr;
10221 tri0 zero_pipe_wire_clr;
10223 tri0 sign_a_wire_clr;
10224 tri0 sign_pipe_a_wire_clr;
10226 tri0 sign_b_wire_clr;
10227 tri0 sign_pipe_b_wire_clr;
10229 tri0 multiplier_wire_clr;
10230 tri0 mult_pipe_wire_clr;
10232 tri0 output_wire_clr;
10234 tri0 mult_round_wire_clr;
10235 tri0 mult_saturation_wire_clr;
10237 tri0 accum_round_wire_clr;
10238 tri0 accum_round_pipe_wire_clr;
10240 tri0 accum_saturation_wire_clr;
10241 tri0 accum_saturation_pipe_wire_clr;
10243 tri0 accum_sload_upper_data_wire_clr;
10244 tri0 accum_sload_upper_data_pipe_wire_clr;
10247 // Tri wire for enable signal
10249 tri1 input_a_wire_en;
10250 tri1 input_b_wire_en;
10252 tri1 addsub_wire_en;
10253 tri1 addsub_pipe_wire_en;
10256 tri1 zero_pipe_wire_en;
10258 tri1 sign_a_wire_en;
10259 tri1 sign_pipe_a_wire_en;
10261 tri1 sign_b_wire_en;
10262 tri1 sign_pipe_b_wire_en;
10264 tri1 multiplier_wire_en;
10265 tri1 mult_pipe_wire_en;
10267 tri1 output_wire_en;
10269 tri1 mult_round_wire_en;
10270 tri1 mult_saturation_wire_en;
10272 tri1 accum_round_wire_en;
10273 tri1 accum_round_pipe_wire_en;
10275 tri1 accum_saturation_wire_en;
10276 tri1 accum_saturation_pipe_wire_en;
10278 tri1 accum_sload_upper_data_wire_en;
10279 tri1 accum_sload_upper_data_pipe_wire_en;
10281 // ------------------------
10282 // SUPPLY WIRE DECLARATION
10283 // ------------------------
10285 supply0 [int_width_a + int_width_b - 1 : 0] temp_mult_zero;
10288 // ----------------
10289 // WIRE DECLARATION
10290 // ----------------
10292 // Wire for Clock signals
10294 wire input_a_wire_clk;
10295 wire input_b_wire_clk;
10297 wire addsub_wire_clk;
10298 wire addsub_pipe_wire_clk;
10300 wire zero_wire_clk;
10301 wire zero_pipe_wire_clk;
10303 wire sign_a_wire_clk;
10304 wire sign_pipe_a_wire_clk;
10306 wire sign_b_wire_clk;
10307 wire sign_pipe_b_wire_clk;
10309 wire multiplier_wire_clk;
10310 wire mult_pipe_wire_clk;
10312 wire output_wire_clk;
10314 wire [width_a -1 : 0] scanouta;
10315 wire [int_width_a + int_width_b -1 : 0] mult_out_latent;
10316 wire [width_b -1 : 0] scanoutb;
10323 wire sign_a_reg_int;
10324 wire sign_b_reg_int;
10326 wire addsub_latent;
10327 wire zeroacc_latent;
10330 wire mult_signed_latent;
10332 wire [width_upper_data - 1 : 0] sload_upper_data_latent;
10333 reg [int_width_result - 1 : 0] sload_upper_data_pipe_wire;
10335 wire [int_width_a -1 :0] mult_a_wire;
10336 wire [int_width_b -1 :0] mult_b_wire;
10337 wire [width_upper_data - 1 : 0] sload_upper_data_wire;
10338 wire [int_width_a -1 : 0] mult_a_tmp;
10339 wire [int_width_b -1 : 0] mult_b_tmp;
10341 wire zero_acc_wire;
10342 wire zero_acc_pipe_wire;
10345 wire sign_a_pipe_wire;
10347 wire sign_b_pipe_wire;
10350 wire addsub_pipe_wire;
10352 wire mult_round_int;
10353 wire mult_round_wire_clk;
10354 wire mult_saturation_int;
10355 wire mult_saturation_wire_clk;
10357 wire accum_round_tmp1_wire;
10358 wire accum_round_wire_clk;
10359 wire accum_round_int;
10360 wire accum_round_pipe_wire_clk;
10362 wire accum_saturation_tmp1_wire;
10363 wire accum_saturation_wire_clk;
10364 wire accum_saturation_int;
10365 wire accum_saturation_pipe_wire_clk;
10367 wire accum_sload_upper_data_wire_clk;
10368 wire accum_sload_upper_data_pipe_wire_clk;
10369 wire [width_result -1 : width_result - width_upper_data] accum_sload_upper_data_int;
10371 tri0 mult_is_saturated_wire;
10373 // ------------------------
10374 // COMPONENT INSTANTIATIONS
10375 // ------------------------
10376 ALTERA_DEVICE_FAMILIES dev ();
10379 // --------------------
10380 // ASSIGNMENT STATEMENTS
10381 // --------------------
10384 assign addsub_int = (port_addnsub == "PORT_USED") ? addsub_pipe_wire :
10385 (port_addnsub == "PORT_UNUSED") ? ((accum_direction == "ADD") ? 1 : 0) :
10386 ((addnsub ===1'bz) ||
10387 (addsub_wire_clk ===1'bz) ||
10388 (addsub_pipe_wire_clk ===1'bz)) ?
10389 ((accum_direction == "ADD") ? 1 : 0) : addsub_pipe_wire;
10391 assign sign_a_int = (port_signa == "PORT_USED") ? sign_a_pipe_wire :
10392 (port_signa == "PORT_UNUSED") ? ((representation_a == "SIGNED") ? 1 : 0) :
10393 ((signa ===1'bz) ||
10394 (sign_a_wire_clk ===1'bz) ||
10395 (sign_pipe_a_wire_clk ===1'bz)) ?
10396 ((representation_a == "SIGNED") ? 1 : 0) : sign_a_pipe_wire;
10398 assign sign_b_int = (port_signb == "PORT_USED") ? sign_b_pipe_wire :
10399 (port_signb == "PORT_UNUSED") ? ((representation_b == "SIGNED") ? 1 : 0) :
10400 ((signb ===1'bz) ||
10401 (sign_b_wire_clk ===1'bz) ||
10402 (sign_pipe_b_wire_clk ===1'bz)) ?
10403 ((representation_b == "SIGNED") ? 1 : 0) : sign_b_pipe_wire;
10407 assign sign_a_reg_int = (port_signa == "PORT_USED") ? sign_a_wire :
10408 (port_signa == "PORT_UNUSED") ? ((representation_a == "SIGNED") ? 1 : 0) :
10409 ((signa ===1'bz) ||
10410 (sign_a_wire_clk ===1'bz) ||
10411 (sign_pipe_a_wire_clk ===1'bz)) ?
10412 ((representation_a == "SIGNED") ? 1 : 0) : sign_a_wire;
10414 assign sign_b_reg_int = (port_signb == "PORT_USED") ? sign_b_wire :
10415 (port_signb == "PORT_UNUSED") ? ((representation_b == "SIGNED") ? 1 : 0) :
10416 ((signb ===1'bz) ||
10417 (sign_b_wire_clk ===1'bz) ||
10418 (sign_pipe_b_wire_clk ===1'bz)) ?
10419 ((representation_b == "SIGNED") ? 1 : 0) : sign_b_wire;
10421 assign zero_acc_int = ((accum_sload ===1'bz) ||
10422 (zero_wire_clk===1'bz) ||
10423 (zero_pipe_wire_clk===1'bz)) ?
10424 0 : zero_acc_pipe_wire;
10426 assign accum_sload_upper_data_int = ((accum_sload_upper_data === {width_upper_data{1'bz}}) ||
10427 (accum_sload_upper_data_wire_clk === 1'bz) ||
10428 (accum_sload_upper_data_pipe_wire_clk === 1'bz)) ?
10429 {width_upper_data{1'b0}} : accum_sload_upper_data;
10431 assign scanouta = mult_a_wire[int_width_a - 1 : int_width_a - width_a];
10432 assign scanoutb = mult_b_wire[int_width_b - 1 : int_width_b - width_b];
10434 assign {addsub_latent, zeroacc_latent, signa_latent, signb_latent, mult_signed_latent, mult_out_latent, sload_upper_data_latent, mult_is_saturated_latent} = (extra_multiplier_latency > 0) ?
10435 mult_full : {addsub_wire, zero_acc_wire, sign_a_wire, sign_b_wire, temp_mult_signed, mult_final_out, sload_upper_data_wire, mult_saturate_overflow};
10437 assign mult_is_saturated = (port_mult_is_saturated != "UNUSED") ? mult_is_saturated_int : 0;
10438 assign accum_is_saturated = (port_accum_is_saturated != "UNUSED") ? accum_is_saturated_latent : 0;
10441 // ---------------------------------------------------------------------------------
10442 // Initialization block where all the internal signals and registers are initialized
10443 // ---------------------------------------------------------------------------------
10447 // Checking for invalid parameters, in case Wizard is bypassed (hand-modified).
10449 if ((dedicated_multiplier_circuitry != "AUTO") &&
10450 (dedicated_multiplier_circuitry != "YES") &&
10451 (dedicated_multiplier_circuitry != "NO"))
10453 $display("Error: The DEDICATED_MULTIPLIER_CIRCUITRY parameter is set to an illegal value.");
10458 $display("Error: width_a must be greater than 0.");
10463 $display("Error: width_b must be greater than 0.");
10466 if (width_result <= 0)
10468 $display("Error: width_result must be greater than 0.");
10472 if (( (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) &&
10473 (dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) )
10474 && (input_source_a != "DATAA"))
10476 $display("Error: The input source for port A are limited to input dataa.");
10480 if (( (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) &&
10481 (dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) )
10482 && (input_source_b != "DATAB"))
10484 $display("Error: The input source for port B are limited to input datab.");
10488 if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (multiplier_rounding != "NO"))
10490 $display("Error: There is no rounding feature for %s device.", intended_device_family);
10494 if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (accumulator_rounding != "NO"))
10496 $display("Error: There is no rounding feature for %s device.", intended_device_family);
10500 if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (multiplier_saturation != "NO"))
10502 $display("Error: There is no saturation feature for %s device.", intended_device_family);
10506 if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (accumulator_saturation != "NO"))
10508 $display("Error: There is no saturation feature for %s device.", intended_device_family);
10522 zero_acc_pipe_reg = 0;
10523 sload_upper_data_reg = 0;
10525 sload_upper_data_pipe_reg = 0;
10527 sign_a_reg = (signa ===1'bz) ? ((representation_a == "SIGNED") ? 1 : 0) : 0;
10528 sign_a_pipe_reg = (signa ===1'bz) ? ((representation_a == "SIGNED") ? 1 : 0) : 0;
10529 sign_b_reg = (signb ===1'bz) ? ((representation_b == "SIGNED") ? 1 : 0) : 0;
10530 sign_b_pipe_reg = (signb ===1'bz) ? ((representation_b == "SIGNED") ? 1 : 0) : 0;
10531 addsub_reg = (addnsub ===1'bz) ? ((accum_direction == "ADD") ? 1 : 0) : 0;
10532 addsub_pipe_reg = (addnsub ===1'bz) ? ((accum_direction == "ADD") ? 1 : 0) : 0;
10539 mult_signed_out = 0;
10542 mult_is_saturated_int = 0;
10543 mult_is_saturated_reg = 0;
10544 mult_saturation_tmp = 0;
10545 mult_saturate_overflow = 0;
10548 accum_saturate_overflow = 0;
10549 accum_is_saturated_latent = 0;
10551 for (i=0; i<=extra_accumulator_latency; i=i+1)
10553 result_pipe [i] = 0;
10554 accum_saturate_pipe[i] = 0;
10555 mult_is_saturated_pipe[i] = 0;
10558 for (i=0; i<= extra_multiplier_latency; i=i+1)
10566 // ---------------------------------------------------------
10567 // This block updates the internal clock signals accordingly
10568 // every time the global clock signal changes state
10569 // ---------------------------------------------------------
10571 assign input_a_wire_clk = (input_reg_a == "CLOCK0")? clock0:
10572 (input_reg_a == "UNREGISTERED")? 0:
10573 (input_reg_a == "CLOCK1")? clock1:
10574 (input_reg_a == "CLOCK2")? clock2:
10575 (input_reg_a == "CLOCK3")? clock3:0;
10577 assign input_b_wire_clk = (input_reg_b == "CLOCK0")? clock0:
10578 (input_reg_b == "UNREGISTERED")? 0:
10579 (input_reg_b == "CLOCK1")? clock1:
10580 (input_reg_b == "CLOCK2")? clock2:
10581 (input_reg_b == "CLOCK3")? clock3:0;
10584 assign addsub_wire_clk = (addnsub_reg == "CLOCK0")? clock0:
10585 (addnsub_reg == "UNREGISTERED")? 0:
10586 (addnsub_reg == "CLOCK1")? clock1:
10587 (addnsub_reg == "CLOCK2")? clock2:
10588 (addnsub_reg == "CLOCK3")? clock3:0;
10591 assign addsub_pipe_wire_clk = (addnsub_pipeline_reg == "CLOCK0")? clock0:
10592 (addnsub_pipeline_reg == "UNREGISTERED")? 0:
10593 (addnsub_pipeline_reg == "CLOCK1")? clock1:
10594 (addnsub_pipeline_reg == "CLOCK2")? clock2:
10595 (addnsub_pipeline_reg == "CLOCK3")? clock3:0;
10598 assign zero_wire_clk = (accum_sload_reg == "CLOCK0")? clock0:
10599 (accum_sload_reg == "UNREGISTERED")? 0:
10600 (accum_sload_reg == "CLOCK1")? clock1:
10601 (accum_sload_reg == "CLOCK2")? clock2:
10602 (accum_sload_reg == "CLOCK3")? clock3:0;
10604 assign accum_sload_upper_data_wire_clk = (accum_sload_upper_data_reg == "CLOCK0")? clock0:
10605 (accum_sload_upper_data_reg == "UNREGISTERED")? 0:
10606 (accum_sload_upper_data_reg == "CLOCK1")? clock1:
10607 (accum_sload_upper_data_reg == "CLOCK2")? clock2:
10608 (accum_sload_upper_data_reg == "CLOCK3")? clock3:0;
10610 assign zero_pipe_wire_clk = (accum_sload_pipeline_reg == "CLOCK0")? clock0:
10611 (accum_sload_pipeline_reg == "UNREGISTERED")? 0:
10612 (accum_sload_pipeline_reg == "CLOCK1")? clock1:
10613 (accum_sload_pipeline_reg == "CLOCK2")? clock2:
10614 (accum_sload_pipeline_reg == "CLOCK3")? clock3:0;
10616 assign accum_sload_upper_data_pipe_wire_clk = (accum_sload_upper_data_pipeline_reg == "CLOCK0")? clock0:
10617 (accum_sload_upper_data_pipeline_reg == "UNREGISTERED")? 0:
10618 (accum_sload_upper_data_pipeline_reg == "CLOCK1")? clock1:
10619 (accum_sload_upper_data_pipeline_reg == "CLOCK2")? clock2:
10620 (accum_sload_upper_data_pipeline_reg == "CLOCK3")? clock3:0;
10622 assign sign_a_wire_clk =(sign_reg_a == "CLOCK0")? clock0:
10623 (sign_reg_a == "UNREGISTERED")? 0:
10624 (sign_reg_a == "CLOCK1")? clock1:
10625 (sign_reg_a == "CLOCK2")? clock2:
10626 (sign_reg_a == "CLOCK3")? clock3:0;
10629 assign sign_b_wire_clk =(sign_reg_b == "CLOCK0")? clock0:
10630 (sign_reg_b == "UNREGISTERED")? 0:
10631 (sign_reg_b == "CLOCK1")? clock1:
10632 (sign_reg_b == "CLOCK2")? clock2:
10633 (sign_reg_b == "CLOCK3")? clock3:0;
10637 assign sign_pipe_a_wire_clk = (sign_pipeline_reg_a == "CLOCK0")? clock0:
10638 (sign_pipeline_reg_a == "UNREGISTERED")? 0:
10639 (sign_pipeline_reg_a == "CLOCK1")? clock1:
10640 (sign_pipeline_reg_a == "CLOCK2")? clock2:
10641 (sign_pipeline_reg_a == "CLOCK3")? clock3:0;
10644 assign sign_pipe_b_wire_clk = (sign_pipeline_reg_b == "CLOCK0")? clock0:
10645 (sign_pipeline_reg_b == "UNREGISTERED")? 0:
10646 (sign_pipeline_reg_b == "CLOCK1")? clock1:
10647 (sign_pipeline_reg_b == "CLOCK2")? clock2:
10648 (sign_pipeline_reg_b == "CLOCK3")? clock3:0;
10651 assign multiplier_wire_clk =(multiplier_reg == "CLOCK0")? clock0:
10652 (multiplier_reg == "UNREGISTERED")? 0:
10653 (multiplier_reg == "CLOCK1")? clock1:
10654 (multiplier_reg == "CLOCK2")? clock2:
10655 (multiplier_reg == "CLOCK3")? clock3:0;
10657 assign output_wire_clk = (output_reg == "CLOCK0")? clock0:
10658 (output_reg == "UNREGISTERED")? 0:
10659 (output_reg == "CLOCK1")? clock1:
10660 (output_reg == "CLOCK2")? clock2:
10661 (output_reg == "CLOCK3")? clock3:0;
10664 assign mult_pipe_wire_clk = (multiplier_reg == "UNREGISTERED")? clock0:
10665 multiplier_wire_clk;
10667 assign mult_round_wire_clk =(mult_round_reg == "CLOCK0")? clock0:
10668 (mult_round_reg == "UNREGISTERED")? 0:
10669 (mult_round_reg == "CLOCK1")? clock1:
10670 (mult_round_reg == "CLOCK2")? clock2:
10671 (mult_round_reg == "CLOCK3")? clock3:0;
10673 assign mult_saturation_wire_clk = (mult_saturation_reg == "CLOCK0")? clock0:
10674 (mult_saturation_reg == "UNREGISTERED")? 0:
10675 (mult_saturation_reg == "CLOCK1")? clock1:
10676 (mult_saturation_reg == "CLOCK2")? clock2:
10677 (mult_saturation_reg == "CLOCK3")? clock3:0;
10679 assign accum_round_wire_clk = (accum_round_reg == "CLOCK0")? clock0:
10680 (accum_round_reg == "UNREGISTERED")? 0:
10681 (accum_round_reg == "CLOCK1")? clock1:
10682 (accum_round_reg == "CLOCK2")? clock2:
10683 (accum_round_reg == "CLOCK3")? clock3:0;
10685 assign accum_round_pipe_wire_clk = (accum_round_pipeline_reg == "CLOCK0")? clock0:
10686 (accum_round_pipeline_reg == "UNREGISTERED")? 0:
10687 (accum_round_pipeline_reg == "CLOCK1")? clock1:
10688 (accum_round_pipeline_reg == "CLOCK2")? clock2:
10689 (accum_round_pipeline_reg == "CLOCK3")? clock3:0;
10691 assign accum_saturation_wire_clk = (accum_saturation_reg == "CLOCK0")? clock0:
10692 (accum_saturation_reg == "UNREGISTERED")? 0:
10693 (accum_saturation_reg == "CLOCK1")? clock1:
10694 (accum_saturation_reg == "CLOCK2")? clock2:
10695 (accum_saturation_reg == "CLOCK3")? clock3:0;
10697 assign accum_saturation_pipe_wire_clk = (accum_saturation_pipeline_reg == "CLOCK0")? clock0:
10698 (accum_saturation_pipeline_reg == "UNREGISTERED")? 0:
10699 (accum_saturation_pipeline_reg == "CLOCK1")? clock1:
10700 (accum_saturation_pipeline_reg == "CLOCK2")? clock2:
10701 (accum_saturation_pipeline_reg == "CLOCK3")? clock3:0;
10704 // ----------------------------------------------------------------
10705 // This block updates the internal clock enable signals accordingly
10706 // every time the global clock enable signal changes state
10707 // ----------------------------------------------------------------
10711 assign input_a_wire_en =(input_reg_a == "CLOCK0")? ena0:
10712 (input_reg_a == "UNREGISTERED")? 1:
10713 (input_reg_a == "CLOCK1")? ena1:
10714 (input_reg_a == "CLOCK2")? ena2:
10715 (input_reg_a == "CLOCK3")? ena3:1;
10717 assign input_b_wire_en =(input_reg_b == "CLOCK0")? ena0:
10718 (input_reg_b == "UNREGISTERED")? 1:
10719 (input_reg_b == "CLOCK1")? ena1:
10720 (input_reg_b == "CLOCK2")? ena2:
10721 (input_reg_b == "CLOCK3")? ena3:1;
10724 assign addsub_wire_en = (addnsub_reg == "CLOCK0")? ena0:
10725 (addnsub_reg == "UNREGISTERED")? 1:
10726 (addnsub_reg == "CLOCK1")? ena1:
10727 (addnsub_reg == "CLOCK2")? ena2:
10728 (addnsub_reg == "CLOCK3")? ena3:1;
10731 assign addsub_pipe_wire_en =(addnsub_pipeline_reg == "CLOCK0")? ena0:
10732 (addnsub_pipeline_reg == "UNREGISTERED")? 1:
10733 (addnsub_pipeline_reg == "CLOCK1")? ena1:
10734 (addnsub_pipeline_reg == "CLOCK2")? ena2:
10735 (addnsub_pipeline_reg == "CLOCK3")? ena3:1;
10738 assign zero_wire_en = (accum_sload_reg == "CLOCK0")? ena0:
10739 (accum_sload_reg == "UNREGISTERED")? 1:
10740 (accum_sload_reg == "CLOCK1")? ena1:
10741 (accum_sload_reg == "CLOCK2")? ena2:
10742 (accum_sload_reg == "CLOCK3")? ena3:1;
10744 assign accum_sload_upper_data_wire_en = (accum_sload_upper_data_reg == "CLOCK0")? ena0:
10745 (accum_sload_upper_data_reg == "UNREGISTERED")? 1:
10746 (accum_sload_upper_data_reg == "CLOCK1")? ena1:
10747 (accum_sload_upper_data_reg == "CLOCK2")? ena2:
10748 (accum_sload_upper_data_reg == "CLOCK3")? ena3:1;
10750 assign zero_pipe_wire_en = (accum_sload_pipeline_reg == "CLOCK0")? ena0:
10751 (accum_sload_pipeline_reg == "UNREGISTERED")? 1:
10752 (accum_sload_pipeline_reg == "CLOCK1")? ena1:
10753 (accum_sload_pipeline_reg == "CLOCK2")? ena2:
10754 (accum_sload_pipeline_reg == "CLOCK3")? ena3:1;
10756 assign accum_sload_upper_data_pipe_wire_en = (accum_sload_upper_data_pipeline_reg == "CLOCK0")? ena0:
10757 (accum_sload_upper_data_pipeline_reg == "UNREGISTERED")? 1:
10758 (accum_sload_upper_data_pipeline_reg == "CLOCK1")? ena1:
10759 (accum_sload_upper_data_pipeline_reg == "CLOCK2")? ena2:
10760 (accum_sload_upper_data_pipeline_reg == "CLOCK3")? ena3:1;
10762 assign sign_a_wire_en = (sign_reg_a == "CLOCK0")? ena0:
10763 (sign_reg_a == "UNREGISTERED")? 1:
10764 (sign_reg_a == "CLOCK1")? ena1:
10765 (sign_reg_a == "CLOCK2")? ena2:
10766 (sign_reg_a == "CLOCK3")? ena3:1;
10769 assign sign_b_wire_en = (sign_reg_b == "CLOCK0")? ena0:
10770 (sign_reg_b == "UNREGISTERED")? 1:
10771 (sign_reg_b == "CLOCK1")? ena1:
10772 (sign_reg_b == "CLOCK2")? ena2:
10773 (sign_reg_b == "CLOCK3")? ena3:1;
10777 assign sign_pipe_a_wire_en = (sign_pipeline_reg_a == "CLOCK0")? ena0:
10778 (sign_pipeline_reg_a == "UNREGISTERED")? 1:
10779 (sign_pipeline_reg_a == "CLOCK1")? ena1:
10780 (sign_pipeline_reg_a == "CLOCK2")? ena2:
10781 (sign_pipeline_reg_a == "CLOCK3")? ena3:1;
10784 assign sign_pipe_b_wire_en = (sign_pipeline_reg_b == "CLOCK0")? ena0:
10785 (sign_pipeline_reg_b == "UNREGISTERED")? 1:
10786 (sign_pipeline_reg_b == "CLOCK1")? ena1:
10787 (sign_pipeline_reg_b == "CLOCK2")? ena2:
10788 (sign_pipeline_reg_b == "CLOCK3")? ena3:1;
10791 assign multiplier_wire_en = (multiplier_reg == "CLOCK0")? ena0:
10792 (multiplier_reg == "UNREGISTERED")? 1:
10793 (multiplier_reg == "CLOCK1")? ena1:
10794 (multiplier_reg == "CLOCK2")? ena2:
10795 (multiplier_reg == "CLOCK3")? ena3:1;
10797 assign output_wire_en = (output_reg == "CLOCK0")? ena0:
10798 (output_reg == "UNREGISTERED")? 1:
10799 (output_reg == "CLOCK1")? ena1:
10800 (output_reg == "CLOCK2")? ena2:
10801 (output_reg == "CLOCK3")? ena3:1;
10804 assign mult_pipe_wire_en = (multiplier_reg == "UNREGISTERED")? ena0:
10805 multiplier_wire_en;
10808 assign mult_round_wire_en = (mult_round_reg == "CLOCK0")? ena0:
10809 (mult_round_reg == "UNREGISTERED")? 1:
10810 (mult_round_reg == "CLOCK1")? ena1:
10811 (mult_round_reg == "CLOCK2")? ena2:
10812 (mult_round_reg == "CLOCK3")? ena3:1;
10815 assign mult_saturation_wire_en = (mult_saturation_reg == "CLOCK0")? ena0:
10816 (mult_saturation_reg == "UNREGISTERED")? 1:
10817 (mult_saturation_reg == "CLOCK1")? ena1:
10818 (mult_saturation_reg == "CLOCK2")? ena2:
10819 (mult_saturation_reg == "CLOCK3")? ena3:1;
10821 assign accum_round_wire_en = (accum_round_reg == "CLOCK0")? ena0:
10822 (accum_round_reg == "UNREGISTERED")? 1:
10823 (accum_round_reg == "CLOCK1")? ena1:
10824 (accum_round_reg == "CLOCK2")? ena2:
10825 (accum_round_reg == "CLOCK3")? ena3:1;
10827 assign accum_round_pipe_wire_en = (accum_round_pipeline_reg == "CLOCK0")? ena0:
10828 (accum_round_pipeline_reg == "UNREGISTERED")? 1:
10829 (accum_round_pipeline_reg == "CLOCK1")? ena1:
10830 (accum_round_pipeline_reg == "CLOCK2")? ena2:
10831 (accum_round_pipeline_reg == "CLOCK3")? ena3:1;
10833 assign accum_saturation_wire_en = (accum_saturation_reg == "CLOCK0")? ena0:
10834 (accum_saturation_reg == "UNREGISTERED")? 1:
10835 (accum_saturation_reg == "CLOCK1")? ena1:
10836 (accum_saturation_reg == "CLOCK2")? ena2:
10837 (accum_saturation_reg == "CLOCK3")? ena3:1;
10839 assign accum_saturation_pipe_wire_en = (accum_saturation_pipeline_reg == "CLOCK0")? ena0:
10840 (accum_saturation_pipeline_reg == "UNREGISTERED")? 1:
10841 (accum_saturation_pipeline_reg == "CLOCK1")? ena1:
10842 (accum_saturation_pipeline_reg == "CLOCK2")? ena2:
10843 (accum_saturation_pipeline_reg == "CLOCK3")? ena3:1;
10845 // ---------------------------------------------------------
10846 // This block updates the internal clear signals accordingly
10847 // every time the global clear signal changes state
10848 // ---------------------------------------------------------
10850 assign input_a_wire_clr =(input_aclr_a == "ACLR3")? aclr3:
10851 (input_aclr_a == "UNUSED")? 0:
10852 (input_aclr_a == "ACLR0")? aclr0:
10853 (input_aclr_a == "ACLR1")? aclr1:
10854 (input_aclr_a == "ACLR2")? aclr2: 0;
10856 assign input_b_wire_clr = (input_aclr_b == "ACLR3")? aclr3:
10857 (input_aclr_b == "UNUSED")? 0:
10858 (input_aclr_b == "ACLR0")? aclr0:
10859 (input_aclr_b == "ACLR1")? aclr1:
10860 (input_aclr_b == "ACLR2")? aclr2: 0;
10863 assign addsub_wire_clr =(addnsub_aclr == "ACLR3")? aclr3:
10864 (addnsub_aclr == "UNUSED")? 0:
10865 (addnsub_aclr == "ACLR0")? aclr0:
10866 (addnsub_aclr == "ACLR1")? aclr1:
10867 (addnsub_aclr == "ACLR2")? aclr2: 0;
10870 assign addsub_pipe_wire_clr = (addnsub_pipeline_aclr == "ACLR3")? aclr3:
10871 (addnsub_pipeline_aclr == "UNUSED")? 0:
10872 (addnsub_pipeline_aclr == "ACLR0")? aclr0:
10873 (addnsub_pipeline_aclr == "ACLR1")? aclr1:
10874 (addnsub_pipeline_aclr == "ACLR2")? aclr2: 0;
10877 assign zero_wire_clr = (accum_sload_aclr == "ACLR3")? aclr3:
10878 (accum_sload_aclr == "UNUSED")? 0:
10879 (accum_sload_aclr == "ACLR0")? aclr0:
10880 (accum_sload_aclr == "ACLR1")? aclr1:
10881 (accum_sload_aclr == "ACLR2")? aclr2: 0;
10883 assign accum_sload_upper_data_wire_clr = (accum_sload_upper_data_aclr == "ACLR3")? aclr3:
10884 (accum_sload_upper_data_aclr == "UNUSED")? 0:
10885 (accum_sload_upper_data_aclr == "ACLR0")? aclr0:
10886 (accum_sload_upper_data_aclr == "ACLR1")? aclr1:
10887 (accum_sload_upper_data_aclr == "ACLR2")? aclr2: 0;
10889 assign zero_pipe_wire_clr = (accum_sload_pipeline_aclr == "ACLR3")? aclr3:
10890 (accum_sload_pipeline_aclr == "UNUSED")? 0:
10891 (accum_sload_pipeline_aclr == "ACLR0")? aclr0:
10892 (accum_sload_pipeline_aclr == "ACLR1")? aclr1:
10893 (accum_sload_pipeline_aclr == "ACLR2")? aclr2: 0;
10895 assign accum_sload_upper_data_pipe_wire_clr = (accum_sload_upper_data_pipeline_aclr == "ACLR3")? aclr3:
10896 (accum_sload_upper_data_pipeline_aclr == "UNUSED")? 0:
10897 (accum_sload_upper_data_pipeline_aclr == "ACLR0")? aclr0:
10898 (accum_sload_upper_data_pipeline_aclr == "ACLR1")? aclr1:
10899 (accum_sload_upper_data_pipeline_aclr == "ACLR2")? aclr2: 0;
10901 assign sign_a_wire_clr =(sign_aclr_a == "ACLR3")? aclr3:
10902 (sign_aclr_a == "UNUSED")? 0:
10903 (sign_aclr_a == "ACLR0")? aclr0:
10904 (sign_aclr_a == "ACLR1")? aclr1:
10905 (sign_aclr_a == "ACLR2")? aclr2: 0;
10908 assign sign_b_wire_clr = (sign_aclr_b == "ACLR3")? aclr3:
10909 (sign_aclr_b == "UNUSED")? 0:
10910 (sign_aclr_b == "ACLR0")? aclr0:
10911 (sign_aclr_b == "ACLR1")? aclr1:
10912 (sign_aclr_b == "ACLR2")? aclr2: 0;
10917 assign sign_pipe_a_wire_clr = (sign_pipeline_aclr_a == "ACLR3")? aclr3:
10918 (sign_pipeline_aclr_a == "UNUSED")? 0:
10919 (sign_pipeline_aclr_a == "ACLR0")? aclr0:
10920 (sign_pipeline_aclr_a == "ACLR1")? aclr1:
10921 (sign_pipeline_aclr_a == "ACLR2")? aclr2: 0;
10924 assign sign_pipe_b_wire_clr = (sign_pipeline_aclr_b == "ACLR3")? aclr3:
10925 (sign_pipeline_aclr_b == "UNUSED")? 0:
10926 (sign_pipeline_aclr_b == "ACLR0")? aclr0:
10927 (sign_pipeline_aclr_b == "ACLR1")? aclr1:
10928 (sign_pipeline_aclr_b == "ACLR2")? aclr2: 0;
10931 assign multiplier_wire_clr = (multiplier_aclr == "ACLR3")? aclr3:
10932 (multiplier_aclr == "UNUSED")? 0:
10933 (multiplier_aclr == "ACLR0")? aclr0:
10934 (multiplier_aclr == "ACLR1")? aclr1:
10935 (multiplier_aclr == "ACLR2")? aclr2: 0;
10937 assign output_wire_clr =(output_aclr == "ACLR3")? aclr3:
10938 (output_aclr == "UNUSED")? 0:
10939 (output_aclr == "ACLR0")? aclr0:
10940 (output_aclr == "ACLR1")? aclr1:
10941 (output_aclr == "ACLR2")? aclr2: 0;
10944 assign mult_pipe_wire_clr = (multiplier_reg == "UNREGISTERED")? aclr0:
10945 multiplier_wire_clr;
10947 assign mult_round_wire_clr = (mult_round_aclr == "ACLR3")? aclr3:
10948 (mult_round_aclr == "UNUSED")? 0:
10949 (mult_round_aclr == "ACLR0")? aclr0:
10950 (mult_round_aclr == "ACLR1")? aclr1:
10951 (mult_round_aclr == "ACLR2")? aclr2: 0;
10953 assign mult_saturation_wire_clr = (mult_saturation_aclr == "ACLR3")? aclr3:
10954 (mult_saturation_aclr == "UNUSED")? 0:
10955 (mult_saturation_aclr == "ACLR0")? aclr0:
10956 (mult_saturation_aclr == "ACLR1")? aclr1:
10957 (mult_saturation_aclr == "ACLR2")? aclr2: 0;
10959 assign accum_round_wire_clr = (accum_round_aclr == "ACLR3")? aclr3:
10960 (accum_round_aclr == "UNUSED")? 0:
10961 (accum_round_aclr == "ACLR0")? aclr0:
10962 (accum_round_aclr == "ACLR1")? aclr1:
10963 (accum_round_aclr == "ACLR2")? aclr2: 0;
10965 assign accum_round_pipe_wire_clr = (accum_round_pipeline_aclr == "ACLR3")? aclr3:
10966 (accum_round_pipeline_aclr == "UNUSED")? 0:
10967 (accum_round_pipeline_aclr == "ACLR0")? aclr0:
10968 (accum_round_pipeline_aclr == "ACLR1")? aclr1:
10969 (accum_round_pipeline_aclr == "ACLR2")? aclr2: 0;
10971 assign accum_saturation_wire_clr = (accum_saturation_aclr == "ACLR3")? aclr3:
10972 (accum_saturation_aclr == "UNUSED")? 0:
10973 (accum_saturation_aclr == "ACLR0")? aclr0:
10974 (accum_saturation_aclr == "ACLR1")? aclr1:
10975 (accum_saturation_aclr == "ACLR2")? aclr2: 0;
10977 assign accum_saturation_pipe_wire_clr = (accum_saturation_pipeline_aclr == "ACLR3")? aclr3:
10978 (accum_saturation_pipeline_aclr == "UNUSED")? 0:
10979 (accum_saturation_pipeline_aclr == "ACLR0")? aclr0:
10980 (accum_saturation_pipeline_aclr == "ACLR1")? aclr1:
10981 (accum_saturation_pipeline_aclr == "ACLR2")? aclr2: 0;
10983 // ------------------------------------------------------------------------
10984 // This block contains 1 register and 1 combinatorial block (to set mult_a)
10985 // Signal Registered : dataa
10987 // Register is controlled by posedge input_wire_a_clk
10988 // Register has an asynchronous clear signal, input_reg_a_wire_clr
10989 // NOTE : The combinatorial block will be executed if
10990 // input_reg_a is unregistered and dataa changes value
10991 // ------------------------------------------------------------------------
10992 assign mult_a_wire = (input_reg_a == "UNREGISTERED")? mult_a_tmp : mult_a_reg;
10994 assign mult_a_tmp = (int_width_a == width_a) ? ((input_source_a == "DATAA")? dataa :
10995 (input_source_a == "SCANA")? scanina :
10996 (sourcea == 1)? scanina : dataa)
10997 : ((input_source_a == "DATAA")? {dataa, {(diff_width_a){1'b0}}} :
10998 (input_source_a == "SCANA")? {scanina, {(diff_width_a){1'b0}}} :
10999 (sourcea == 1)? {scanina, {(diff_width_a){1'b0}}} : {dataa, {(diff_width_a){1'b0}}});
11001 always @(posedge input_a_wire_clk or posedge input_a_wire_clr)
11003 if (input_a_wire_clr == 1)
11005 else if ((input_a_wire_clk == 1) && (input_a_wire_en == 1))
11007 if (input_source_a == "DATAA")
11008 mult_a_reg <= (int_width_a == width_a) ? dataa : {dataa, {(diff_width_a){1'b0}}};
11009 else if (input_source_a == "SCANA")
11010 mult_a_reg <= (int_width_a == width_a) ? scanina : {scanina,{(diff_width_a){1'b0}}};
11011 else if (input_source_a == "VARIABLE")
11014 mult_a_reg <= (int_width_a == width_a) ? scanina : {scanina, {(diff_width_a){1'b0}}};
11016 mult_a_reg <= (int_width_a == width_a) ? dataa : {dataa, {(diff_width_a){1'b0}}};
11022 // ------------------------------------------------------------------------
11023 // This block contains 1 register and 1 combinatorial block (to set mult_b)
11024 // Signal Registered : datab
11026 // Register is controlled by posedge input_wire_b_clk
11027 // Register has an asynchronous clear signal, input_reg_b_wire_clr
11028 // NOTE : The combinatorial block will be executed if
11029 // input_reg_b is unregistered and datab changes value
11030 // ------------------------------------------------------------------------
11031 assign mult_b_wire = (input_reg_b == "UNREGISTERED")? mult_b_tmp : mult_b_reg;
11032 assign mult_b_tmp = (int_width_b == width_b) ? ((input_source_b == "DATAB")? datab :
11033 (input_source_b == "SCANB")? scaninb :
11034 (sourceb == 1)? scaninb : datab)
11035 : ((input_source_b == "DATAB")? {datab, {(diff_width_b){1'b0}}} :
11036 (input_source_b == "SCANB")? {scaninb, {(diff_width_b){1'b0}}} :
11037 (sourceb == 1)? {scaninb, {(diff_width_b){1'b0}}} : {datab, {(diff_width_b){1'b0}}});
11039 always @(posedge input_b_wire_clk or posedge input_b_wire_clr )
11041 if (input_b_wire_clr == 1)
11043 else if ((input_b_wire_clk == 1) && (input_b_wire_en == 1))
11045 if (input_source_b == "DATAB")
11046 mult_b_reg <= (int_width_b == width_b) ? datab : {datab, {(diff_width_b){1'b0}}};
11047 else if (input_source_b == "SCANB")
11048 mult_b_reg <= (int_width_b == width_b) ? scaninb : {scaninb, {(diff_width_b){1'b0}}};
11049 else if (input_source_b == "VARIABLE")
11052 mult_b_reg <= (int_width_b == width_b) ? scaninb : {scaninb, {(diff_width_b){1'b0}}};
11054 mult_b_reg <= (int_width_b == width_b) ? datab : {datab, {(diff_width_b){1'b0}}};
11060 // -----------------------------------------------------------------------------
11061 // This block contains 1 register and 1 combinatorial block (to set addnsub_reg)
11062 // Signal Registered : addnsub
11064 // Register is controlled by posedge addsub_wire_clk
11065 // Register has an asynchronous clear signal, addsub_wire_clr
11066 // NOTE : The combinatorial block will be executed if
11067 // addnsub_reg is unregistered and addnsub changes value
11068 // -----------------------------------------------------------------------------
11069 assign addsub_wire = ((addnsub_reg == "UNREGISTERED") )? addnsub : addsub_reg;
11071 always @(posedge addsub_wire_clk or posedge addsub_wire_clr)
11073 if (addsub_wire_clr == 1)
11075 else if ((addsub_wire_clk == 1) && (addsub_wire_en == 1))
11076 addsub_reg <= addnsub;
11080 // -----------------------------------------------------------------------------
11081 // This block contains 1 register and 1 combinatorial block (to set addsub_pipe)
11082 // Signal Registered : addsub_latent
11084 // Register is controlled by posedge addsub_pipe_wire_clk
11085 // Register has an asynchronous clear signal, addsub_pipe_wire_clr
11086 // NOTE : The combinatorial block will be executed if
11087 // addsub_pipeline_reg is unregistered and addsub_latent changes value
11088 // -----------------------------------------------------------------------------
11089 assign addsub_pipe_wire = (addnsub_pipeline_reg == "UNREGISTERED")?addsub_latent : addsub_pipe_reg;
11091 always @(posedge addsub_pipe_wire_clk or posedge addsub_pipe_wire_clr )
11093 if (addsub_pipe_wire_clr == 1)
11094 addsub_pipe_reg <= 0;
11095 else if ((addsub_pipe_wire_clk == 1) && (addsub_pipe_wire_en == 1))
11096 addsub_pipe_reg <= addsub_latent;
11101 // ------------------------------------------------------------------------------
11102 // This block contains 1 register and 1 combinatorial block (to set zero_acc_reg)
11103 // Signal Registered : accum_sload
11105 // Register is controlled by posedge zero_wire_clk
11106 // Register has an asynchronous clear signal, zero_wire_clr
11107 // NOTE : The combinatorial block will be executed if
11108 // accum_sload_reg is unregistered and accum_sload changes value
11109 // ------------------------------------------------------------------------------
11110 assign zero_acc_wire = (accum_sload_reg == "UNREGISTERED")?accum_sload : zero_acc_reg;
11112 always @(posedge zero_wire_clk or posedge zero_wire_clr)
11114 if (zero_wire_clr == 1)
11118 else if ((zero_wire_clk == 1) && (zero_wire_en == 1))
11120 zero_acc_reg <= accum_sload;
11124 assign sload_upper_data_wire = (accum_sload_upper_data_reg == "UNREGISTERED")? accum_sload_upper_data_int : sload_upper_data_reg;
11127 always @(posedge accum_sload_upper_data_wire_clk or posedge accum_sload_upper_data_wire_clr)
11129 if (accum_sload_upper_data_wire_clr == 1)
11131 sload_upper_data_reg <= 0;
11133 else if ((accum_sload_upper_data_wire_clk == 1) && (accum_sload_upper_data_wire_en == 1))
11135 sload_upper_data_reg <= accum_sload_upper_data_int;
11139 // --------------------------------------------------------------------------------
11140 // This block contains 1 register and 1 combinatorial block (to set zero_acc_pipe)
11141 // Signal Registered : zeroacc_latent
11143 // Register is controlled by posedge zero_pipe_wire_clk
11144 // Register has an asynchronous clear signal, zero_pipe_wire_clr
11145 // NOTE : The combinatorial block will be executed if
11146 // accum_sload_pipeline_reg is unregistered and zeroacc_latent changes value
11147 // --------------------------------------------------------------------------------
11148 assign zero_acc_pipe_wire = (accum_sload_pipeline_reg == "UNREGISTERED")?zeroacc_latent : zero_acc_pipe_reg;
11150 always @(posedge zero_pipe_wire_clk or posedge zero_pipe_wire_clr)
11152 if (zero_pipe_wire_clr == 1)
11154 zero_acc_pipe_reg <= 0;
11156 else if ((zero_pipe_wire_clk == 1) && (zero_pipe_wire_en == 1))
11158 zero_acc_pipe_reg <= zeroacc_latent;
11164 always @(posedge accum_sload_upper_data_pipe_wire_clk or posedge accum_sload_upper_data_pipe_wire_clr)
11166 if (accum_sload_upper_data_pipe_wire_clr == 1)
11168 sload_upper_data_pipe_reg <= 0;
11170 else if ((accum_sload_upper_data_pipe_wire_clk == 1) && (accum_sload_upper_data_pipe_wire_en == 1))
11172 sload_upper_data_pipe_reg <= sload_upper_data_latent;
11177 always @(sload_upper_data_latent or sload_upper_data_pipe_reg or sign_a_int or sign_b_int )
11179 if (accum_sload_upper_data_pipeline_reg == "UNREGISTERED")
11181 if(int_width_result > width_result)
11184 if(sign_a_int | sign_b_int)
11186 sload_upper_data_pipe_wire[int_width_result - 1 : 0] = {int_width_result{sload_upper_data_latent[width_upper_data-1]}};
11190 sload_upper_data_pipe_wire[int_width_result - 1 : 0] = {int_width_result{1'b0}};
11193 if(width_result > width_upper_data)
11195 for(i4 = 0; i4 < width_result - width_upper_data + int_extra_width; i4 = i4 + 1)
11197 sload_upper_data_pipe_wire[i4] = 1'b0;
11199 sload_upper_data_pipe_wire[width_result - 1 + int_extra_width : width_result - width_upper_data + int_extra_width] = sload_upper_data_latent;
11201 else if(width_result == width_upper_data)
11203 for(i4 = 0; i4 < int_extra_width; i4 = i4 + 1)
11205 sload_upper_data_pipe_wire[i4] = 1'b0;
11207 sload_upper_data_pipe_wire[width_result - 1 + int_extra_width: 0 + int_extra_width] = sload_upper_data_latent;
11211 for(i4 = int_extra_width; i4 < sload_for_limit; i4 = i4 + 1)
11213 sload_upper_data_pipe_wire[i4] = sload_upper_data_latent[i4];
11215 for(i4 = 0; i4 < int_extra_width; i4 = i4 + 1)
11217 sload_upper_data_pipe_wire[i4] = 1'b0;
11223 if(width_result > width_upper_data)
11225 for(i4 = 0; i4 < width_result - width_upper_data + int_extra_width; i4 = i4 + 1)
11227 sload_upper_data_pipe_wire[i4] = 1'b0;
11229 sload_upper_data_pipe_wire[width_result - 1 + int_extra_width : width_result - width_upper_data + int_extra_width] = sload_upper_data_latent;
11231 else if(width_result == width_upper_data)
11233 for(i4 = 0; i4 < int_extra_width; i4 = i4 + 1)
11235 sload_upper_data_pipe_wire[i4] = 1'b0;
11237 sload_upper_data_pipe_wire[width_result - 1 + int_extra_width : 0 + int_extra_width] = sload_upper_data_latent;
11241 for(i4 = int_extra_width; i4 < sload_for_limit; i4 = i4 + 1)
11243 sload_upper_data_pipe_wire[i4] = sload_upper_data_latent[i4];
11245 for(i4 = 0; i4 < int_extra_width; i4 = i4 + 1)
11247 sload_upper_data_pipe_wire[i4] = 1'b0;
11254 if(int_width_result > width_result)
11257 if(sign_a_int | sign_b_int)
11259 sload_upper_data_pipe_wire[int_width_result - 1 : 0] = {int_width_result{sload_upper_data_pipe_reg[width_upper_data-1]}};
11263 sload_upper_data_pipe_wire[int_width_result - 1 : 0] = {int_width_result{1'b0}};
11266 if(width_result > width_upper_data)
11268 for(i4 = 0; i4 < width_result - width_upper_data + int_extra_width; i4 = i4 + 1)
11270 sload_upper_data_pipe_wire[i4] = 1'b0;
11272 sload_upper_data_pipe_wire[width_result - 1 + int_extra_width : width_result - width_upper_data + int_extra_width] = sload_upper_data_pipe_reg;
11274 else if(width_result == width_upper_data)
11276 for(i4 = 0; i4 < int_extra_width; i4 = i4 + 1)
11278 sload_upper_data_pipe_wire[i4] = 1'b0;
11280 sload_upper_data_pipe_wire[width_result - 1 + int_extra_width: 0 + int_extra_width] = sload_upper_data_pipe_reg;
11284 for(i4 = int_extra_width; i4 < sload_for_limit; i4 = i4 + 1)
11286 sload_upper_data_pipe_wire[i4] = sload_upper_data_pipe_reg[i4];
11288 for(i4 = 0; i4 < int_extra_width; i4 = i4 + 1)
11290 sload_upper_data_pipe_wire[i4] = 1'b0;
11296 if(width_result > width_upper_data)
11298 for(i4 = 0; i4 < width_result - width_upper_data + int_extra_width; i4 = i4 + 1)
11300 sload_upper_data_pipe_wire[i4] = 1'b0;
11302 sload_upper_data_pipe_wire[width_result - 1 + int_extra_width : width_result - width_upper_data + int_extra_width] = sload_upper_data_pipe_reg;
11304 else if(width_result == width_upper_data)
11306 for(i4 = 0; i4 < int_extra_width; i4 = i4 + 1)
11308 sload_upper_data_pipe_wire[i4] = 1'b0;
11310 sload_upper_data_pipe_wire[width_result - 1 + int_extra_width : 0 + int_extra_width] = sload_upper_data_pipe_reg;
11314 for(i4 = int_extra_width; i4 < sload_for_limit; i4 = i4 + 1)
11316 sload_upper_data_pipe_wire[i4] = sload_upper_data_pipe_reg[i4];
11318 for(i4 = 0; i4 < int_extra_width; i4 = i4 + 1)
11320 sload_upper_data_pipe_wire[i4] = 1'b0;
11327 // ----------------------------------------------------------------------------
11328 // This block contains 1 register and 1 combinatorial block (to set sign_a_reg)
11329 // Signal Registered : signa
11331 // Register is controlled by posedge sign_a_wire_clk
11332 // Register has an asynchronous clear signal, sign_a_wire_clr
11333 // NOTE : The combinatorial block will be executed if
11334 // sign_reg_a is unregistered and signa changes value
11335 // ----------------------------------------------------------------------------
11336 assign sign_a_wire = (sign_reg_a == "UNREGISTERED")? signa : sign_a_reg;
11338 always @(posedge sign_a_wire_clk or posedge sign_a_wire_clr)
11340 if (sign_a_wire_clr == 1)
11342 else if ((sign_a_wire_clk == 1) && (sign_a_wire_en == 1))
11343 sign_a_reg <= signa;
11347 // -----------------------------------------------------------------------------
11348 // This block contains 1 register and 1 combinatorial block (to set sign_a_pipe)
11349 // Signal Registered : signa_latent
11351 // Register is controlled by posedge sign_pipe_a_wire_clk
11352 // Register has an asynchronous clear signal, sign_pipe_a_wire_clr
11353 // NOTE : The combinatorial block will be executed if
11354 // sign_pipeline_reg_a is unregistered and signa_latent changes value
11355 // -----------------------------------------------------------------------------
11356 assign sign_a_pipe_wire = (sign_pipeline_reg_a == "UNREGISTERED")? signa_latent : sign_a_pipe_reg;
11358 always @(posedge sign_pipe_a_wire_clk or posedge sign_pipe_a_wire_clr)
11360 if (sign_pipe_a_wire_clr == 1)
11361 sign_a_pipe_reg <= 0;
11362 else if ((sign_pipe_a_wire_clk == 1) && (sign_pipe_a_wire_en == 1))
11363 sign_a_pipe_reg <= signa_latent;
11367 // ----------------------------------------------------------------------------
11368 // This block contains 1 register and 1 combinatorial block (to set sign_b_reg)
11369 // Signal Registered : signb
11371 // Register is controlled by posedge sign_b_wire_clk
11372 // Register has an asynchronous clear signal, sign_b_wire_clr
11373 // NOTE : The combinatorial block will be executed if
11374 // sign_reg_b is unregistered and signb changes value
11375 // ----------------------------------------------------------------------------
11376 assign sign_b_wire = (sign_reg_b == "UNREGISTERED") ? signb : sign_b_reg;
11378 always @(posedge sign_b_wire_clk or posedge sign_b_wire_clr)
11380 if (sign_b_wire_clr == 1)
11382 else if ((sign_b_wire_clk == 1) && (sign_b_wire_en == 1))
11383 sign_b_reg <= signb;
11387 // -----------------------------------------------------------------------------
11388 // This block contains 1 register and 1 combinatorial block (to set sign_b_pipe)
11389 // Signal Registered : signb_latent
11391 // Register is controlled by posedge sign_pipe_b_wire_clk
11392 // Register has an asynchronous clear signal, sign_pipe_b_wire_clr
11393 // NOTE : The combinatorial block will be executed if
11394 // sign_pipeline_reg_b is unregistered and signb_latent changes value
11395 // -----------------------------------------------------------------------------
11396 assign sign_b_pipe_wire = (sign_pipeline_reg_b == "UNREGISTERED" )? signb_latent : sign_b_pipe_reg;
11398 always @(posedge sign_pipe_b_wire_clk or posedge sign_pipe_b_wire_clr )
11400 if (sign_pipe_b_wire_clr == 1)
11401 sign_b_pipe_reg <= 0;
11402 else if ((sign_pipe_b_wire_clk == 1) && (sign_pipe_b_wire_en == 1))
11403 sign_b_pipe_reg <= signb_latent;
11407 // ----------------------------------------------------------------------------
11408 // This block contains 1 register and 1 combinatorial block (to set mult_round)
11409 // Signal Registered : mult_round
11411 // Register is controlled by posedge mult_round_wire_clk
11412 // Register has an asynchronous clear signal, mult_round_wire_clr
11413 // NOTE : The combinatorial block will be executed if
11414 // mult_round_reg is unregistered and mult_round changes value
11415 // ----------------------------------------------------------------------------
11417 assign mult_round_int = (mult_round_reg == "UNREGISTERED")? mult_round : mult_round_tmp;
11419 always @(posedge mult_round_wire_clk or posedge mult_round_wire_clr)
11421 if (mult_round_wire_clr == 1)
11422 mult_round_tmp <= 0;
11423 else if ((mult_round_wire_clk == 1) && (mult_round_wire_en == 1))
11424 mult_round_tmp <= mult_round;
11427 // ----------------------------------------------------------------------------
11428 // This block contains 1 register and 1 combinatorial block (to set mult_saturation)
11429 // Signal Registered : mult_saturation
11431 // Register is controlled by posedge mult_saturation_wire_clk
11432 // Register has an asynchronous clear signal, mult_saturation_wire_clr
11433 // NOTE : The combinatorial block will be executed if
11434 // mult_saturation_reg is unregistered and mult_saturation changes value
11435 // ----------------------------------------------------------------------------
11437 assign mult_saturation_int = (mult_saturation_reg == "UNREGISTERED")? mult_saturation : mult_saturation_tmp;
11439 always @(posedge mult_saturation_wire_clk or posedge mult_saturation_wire_clr)
11441 if (mult_saturation_wire_clr == 1)
11442 mult_saturation_tmp <= 0;
11443 else if ((mult_saturation_wire_clk == 1) && (mult_saturation_wire_en == 1))
11444 mult_saturation_tmp <= mult_saturation;
11447 // ----------------------------------------------------------------------------
11448 // This block contains 1 register and 1 combinatorial block (to set accum_round)
11449 // Signal Registered : accum_round
11451 // Register is controlled by posedge accum_round_wire_clk
11452 // Register has an asynchronous clear signal, accum_round_wire_clr
11453 // NOTE : The combinatorial block will be executed if
11454 // accum_round_reg is unregistered and accum_round changes value
11455 // ----------------------------------------------------------------------------
11457 assign accum_round_tmp1_wire = (accum_round_reg == "UNREGISTERED")? accum_round : accum_round_tmp1;
11459 always @(posedge accum_round_wire_clk or posedge accum_round_wire_clr)
11461 if (accum_round_wire_clr == 1)
11462 accum_round_tmp1 <= 0;
11463 else if ((accum_round_wire_clk == 1) && (accum_round_wire_en == 1))
11464 accum_round_tmp1 <= accum_round;
11467 // ----------------------------------------------------------------------------
11468 // This block contains 1 register and 1 combinatorial block (to set accum_round_tmp1)
11469 // Signal Registered : accum_round_tmp1
11471 // Register is controlled by posedge accum_round_pipe_wire_clk
11472 // Register has an asynchronous clear signal, accum_round_pipe_wire_clr
11473 // NOTE : The combinatorial block will be executed if
11474 // accum_round_pipeline_reg is unregistered and accum_round_tmp1_wire changes value
11475 // ----------------------------------------------------------------------------
11477 assign accum_round_int = (accum_round_pipeline_reg == "UNREGISTERED")? accum_round_tmp1_wire : accum_round_tmp2;
11479 always @(posedge accum_round_pipe_wire_clk or posedge accum_round_pipe_wire_clr)
11481 if (accum_round_pipe_wire_clr == 1)
11482 accum_round_tmp2 <= 0;
11483 else if ((accum_round_pipe_wire_clk == 1) && (accum_round_pipe_wire_en == 1))
11484 accum_round_tmp2 <= accum_round_tmp1_wire;
11488 // ----------------------------------------------------------------------------
11489 // This block contains 1 register and 1 combinatorial block (to set accum_saturation)
11490 // Signal Registered : accum_saturation
11492 // Register is controlled by posedge accum_saturation_wire_clk
11493 // Register has an asynchronous clear signal, accum_saturation_wire_clr
11494 // NOTE : The combinatorial block will be executed if
11495 // accum_saturation_reg is unregistered and accum_saturation changes value
11496 // ----------------------------------------------------------------------------
11498 assign accum_saturation_tmp1_wire = (accum_saturation_reg == "UNREGISTERED")? accum_saturation : accum_saturation_tmp1;
11500 always @(posedge accum_saturation_wire_clk or posedge accum_saturation_wire_clr)
11502 if (accum_saturation_wire_clr == 1)
11503 accum_saturation_tmp1 <= 0;
11504 else if ((accum_saturation_wire_clk == 1) && (accum_saturation_wire_en == 1))
11505 accum_saturation_tmp1 <= accum_saturation;
11508 // ----------------------------------------------------------------------------
11509 // This block contains 1 register and 1 combinatorial block (to set accum_saturation_tmp1)
11510 // Signal Registered : accum_saturation_tmp1
11512 // Register is controlled by posedge accum_saturation_pipe_wire_clk
11513 // Register has an asynchronous clear signal, accum_saturation_pipe_wire_clr
11514 // NOTE : The combinatorial block will be executed if
11515 // accum_saturation_pipeline_reg is unregistered and accum_saturation_tmp1_wire changes value
11516 // ----------------------------------------------------------------------------
11518 assign accum_saturation_int = (accum_saturation_pipeline_reg == "UNREGISTERED")? accum_saturation_tmp1_wire : accum_saturation_tmp2;
11520 always @(posedge accum_saturation_pipe_wire_clk or posedge accum_saturation_pipe_wire_clr)
11522 if (accum_saturation_pipe_wire_clr == 1)
11523 accum_saturation_tmp2 <= 0;
11524 else if ((accum_saturation_pipe_wire_clk == 1) && (accum_saturation_pipe_wire_en == 1))
11525 accum_saturation_tmp2 <= accum_saturation_tmp1_wire;
11529 // ------------------------------------------------------------------------------------------------------
11530 // This block checks if the two numbers to be multiplied (mult_a/mult_b) is to be interpreted
11531 // as a negative number or not. If so, then two's complement is performed.
11532 // The numbers are then multipled
11533 // The sign of the result (positive or negative) is determined based on the sign of the two input numbers
11534 // ------------------------------------------------------------------------------------------------------
11536 always @(mult_a_wire or mult_b_wire or sign_a_reg_int or sign_b_reg_int or temp_mult_zero)
11538 neg_a = mult_a_wire [int_width_a-1] & (sign_a_reg_int);
11539 neg_b = mult_b_wire [int_width_b-1] & (sign_b_reg_int);
11541 mult_a_int = (neg_a == 1) ? ~mult_a_wire + 1 : mult_a_wire;
11542 mult_b_int = (neg_b == 1) ? ~mult_b_wire + 1 : mult_b_wire;
11544 temp_mult_1 = mult_a_int * mult_b_int;
11545 temp_mult_signed = sign_a_reg_int | sign_b_reg_int;
11546 temp_mult = (neg_a ^ neg_b) ? (temp_mult_zero - temp_mult_1) : temp_mult_1;
11550 always @(temp_mult or mult_saturation_int or mult_round_int)
11553 if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 1)
11555 // StratixII rounding support
11557 // This is based on both input is in Q1.15 format
11559 if ((multiplier_rounding == "YES") ||
11560 ((multiplier_rounding == "VARIABLE") && (mult_round_int == 1)))
11562 mult_round_out = temp_mult + ( 1 << (bits_to_round));
11567 mult_round_out = temp_mult;
11570 // StratixII saturation support
11572 if ((multiplier_saturation == "YES") ||
11573 (( multiplier_saturation == "VARIABLE") && (mult_saturation_int == 1)))
11575 mult_saturate_overflow = (mult_round_out[int_width_a + int_width_b - 1] == 0 && mult_round_out[int_width_a + int_width_b - 2] == 1);
11576 if (mult_saturate_overflow == 0)
11578 mult_saturate_out = mult_round_out;
11582 for (i = (int_width_a + int_width_b - 1); i >= (int_width_a + int_width_b - 2); i = i - 1)
11584 mult_saturate_out[i] = mult_round_out[int_width_a + int_width_b - 1];
11587 for (i = (int_width_a + int_width_b - 3); i >= 0; i = i - 1)
11589 mult_saturate_out[i] = ~mult_round_out[int_width_a + int_width_b - 1];
11592 for (i= sat_for_ini; i >=0; i = i - 1)
11594 mult_saturate_out[i] = 1'b0;
11601 mult_saturate_out = mult_round_out;
11602 mult_saturate_overflow = 0;
11605 if ((multiplier_rounding == "YES") ||
11606 ((multiplier_rounding == "VARIABLE") && (mult_round_int == 1)))
11608 mult_result = mult_saturate_out;
11610 for (i = mult_round_for_ini; i >= 0; i = i - 1)
11612 mult_result[i] = 1'b0;
11617 mult_result = mult_saturate_out;
11621 mult_final_out = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) ?
11622 temp_mult : mult_result;
11627 // ---------------------------------------------------------------------------------------
11628 // This block contains 2 register (to set mult_res and mult_signed)
11629 // Signals Registered : mult_out_latent, mult_signed_latent
11631 // Both the registers are controlled by the same clock signal, posedge multiplier_wire_clk
11632 // Both registers share the same clock enable signal multipler_wire_en
11633 // Both registers have the same asynchronous signal, posedge multiplier_wire_clr
11634 // ---------------------------------------------------------------------------------------
11635 assign mult_is_saturated_wire = (multiplier_reg == "UNREGISTERED")? mult_is_saturated_latent : mult_is_saturated_reg;
11637 always @(posedge multiplier_wire_clk or posedge multiplier_wire_clr)
11639 if (multiplier_wire_clr == 1)
11643 mult_is_saturated_reg <=0;
11645 else if ((multiplier_wire_clk == 1) && (multiplier_wire_en == 1))
11647 mult_res <= mult_out_latent;
11648 mult_signed <= mult_signed_latent;
11649 mult_is_saturated_reg <= mult_is_saturated_latent;
11654 // --------------------------------------------------------------------
11655 // This block contains 1 register (to set mult_full)
11656 // Signal Registered : mult_pipe
11658 // Register is controlled by posedge mult_pipe_wire_clk
11659 // Register also has an asynchronous clear signal posedge mult_pipe_wire_clr
11660 // --------------------------------------------------------------------
11661 always @(posedge mult_pipe_wire_clk or posedge mult_pipe_wire_clr )
11663 if (mult_pipe_wire_clr ==1)
11665 // clear the pipeline
11666 for (i2=0; i2<=extra_multiplier_latency; i2=i2+1)
11668 mult_pipe [i2] = 0;
11672 else if ((mult_pipe_wire_clk == 1) && (mult_pipe_wire_en == 1))
11674 mult_pipe [head_mult] = {addsub_wire, zero_acc_wire, sign_a_wire, sign_b_wire, temp_mult_signed, mult_final_out, sload_upper_data_wire, mult_saturate_overflow};
11675 head_mult = (head_mult +1) % (extra_multiplier_latency);
11676 mult_full = mult_pipe[head_mult];
11681 // -------------------------------------------------------------
11682 // This is the main process block that performs the accumulation
11683 // -------------------------------------------------------------
11684 always @(posedge output_wire_clk or posedge output_wire_clr)
11686 if (output_wire_clr == 1)
11691 result_int = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) ?
11692 temp_sum[int_width_result -1 : 0] : accum_result;
11695 accum_saturate_overflow = 0;
11696 mult_is_saturated_int = 0;
11697 for (i3=0; i3<=extra_accumulator_latency; i3=i3+1)
11699 result_pipe [i3] = 0;
11700 accum_saturate_pipe[i3] = 0;
11701 mult_is_saturated_pipe[i3] = 0;
11707 else if (output_wire_clk ==1)
11710 if (output_wire_en ==1)
11712 if (extra_accumulator_latency == 0)
11714 mult_is_saturated_int = mult_is_saturated_wire;
11717 if (multiplier_reg == "UNREGISTERED")
11719 mult_res_out = {{int_width_result - int_width_a - int_width_b {(sign_a_int | sign_b_int) & mult_out_latent [int_width_a+int_width_b -1]}}, mult_out_latent};
11720 mult_signed_out = (sign_a_int | sign_b_int);
11724 mult_res_out = {{int_width_result - int_width_a - int_width_b {(sign_a_int | sign_b_int) & mult_res [int_width_a+int_width_b -1]}}, mult_res};
11725 mult_signed_out = (sign_a_int | sign_b_int);
11731 if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0 &&
11732 dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0)
11734 temp_sum = ( (zero_acc_int==0) ? result_int : 0) + mult_res_out;
11738 temp_sum = ( (zero_acc_int==0) ? result_int : sload_upper_data_pipe_wire) + mult_res_out;
11741 cout_int = temp_sum [int_width_result];
11746 if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0 &&
11747 dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0)
11749 temp_sum = ( (zero_acc_int==0) ? result_int : 0) - (mult_res_out);
11750 cout_int = (( (zero_acc_int==0) ? result_int : 0) >= mult_res_out) ? 1 : 0;
11754 temp_sum = ( (zero_acc_int==0) ? result_int : sload_upper_data_pipe_wire) - mult_res_out;
11755 cout_int = (( (zero_acc_int==0) ? result_int : sload_upper_data_pipe_wire) >= mult_res_out) ? 1 : 0;
11760 if ((mult_signed_out==1) && (mult_res_out != 0))
11762 if (zero_acc_int == 0)
11764 overflow_tmp_int = (mult_res_out [int_width_a+int_width_b -1] ~^ result_int [int_width_result-1]) ^ (~addsub_int);
11765 overflow_int = overflow_tmp_int & (result_int [int_width_result -1] ^ temp_sum[int_width_result -1]);
11769 overflow_tmp_int = (mult_res_out [int_width_a+int_width_b -1] ~^ sload_upper_data_pipe_wire [int_width_result-1]) ^ (~addsub_int);
11770 overflow_int = overflow_tmp_int & (sload_upper_data_pipe_wire [int_width_result -1] ^ temp_sum[int_width_result -1]);
11775 overflow_int = (addsub_int ==1)? cout_int : ~cout_int;
11778 if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 1)
11780 // StratixII rounding support
11782 // This is based on both input is in Q1.15 format
11784 if ((accumulator_rounding == "YES") ||
11785 ((accumulator_rounding == "VARIABLE") && (accum_round_int == 1)))
11787 accum_round_out = temp_sum[int_width_result -1 : 0] + ( 1 << (bits_to_round));
11791 accum_round_out = temp_sum[int_width_result - 1 : 0];
11794 // StratixII saturation support
11796 if ((accumulator_saturation == "YES") ||
11797 ((accumulator_saturation == "VARIABLE") && (accum_saturation_int == 1)))
11799 accum_result_sign_bits = accum_round_out[int_width_result-1 : int_width_a + int_width_b - 2];
11801 if ( (((&accum_result_sign_bits) | (|accum_result_sign_bits) | (^accum_result_sign_bits)) == 0) ||
11802 (((&accum_result_sign_bits) & (|accum_result_sign_bits) & !(^accum_result_sign_bits)) == 1))
11804 accum_saturate_overflow = 1'b0;
11808 accum_saturate_overflow = 1'b1;
11811 if (accum_saturate_overflow == 0)
11813 accum_saturate_out = accum_round_out;
11818 for (i = (int_width_result - 1); i >= (int_width_a + int_width_b - 2); i = i - 1)
11820 accum_saturate_out[i] = accum_round_out[int_width_result-1];
11824 for (i = (int_width_a + int_width_b - 3); i >= accum_sat_for_limit; i = i - 1)
11826 accum_saturate_out[i] = ~accum_round_out[int_width_result -1];
11829 for (i = sat_for_ini; i >= 0; i = i - 1)
11831 accum_saturate_out[i] = 1'b0;
11838 accum_saturate_out = accum_round_out;
11839 accum_saturate_overflow = 0;
11842 if ((accumulator_rounding == "YES") ||
11843 ((accumulator_rounding == "VARIABLE") && (accum_round_int == 1)))
11845 accum_result = accum_saturate_out;
11847 for (i = bits_to_round; i >= 0; i = i - 1)
11849 accum_result[i] = 1'b0;
11854 accum_result = accum_saturate_out;
11858 result_int = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) ?
11859 temp_sum[int_width_result -1 : 0] : accum_result;
11867 always @ (posedge flag or negedge flag)
11869 if (extra_accumulator_latency == 0)
11871 result = result_int[width_result - 1 + int_extra_width : int_extra_width];
11872 overflow = overflow_int;
11873 accum_is_saturated_latent = accum_saturate_overflow;
11877 result_pipe [head_result] = {overflow_int, result_int[width_result - 1 + int_extra_width : int_extra_width]};
11878 //mult_is_saturated_pipe[head_result] = mult_is_saturated_wire;
11879 accum_saturate_pipe[head_result] = accum_saturate_overflow;
11880 head_result = (head_result +1) % (extra_accumulator_latency + 1);
11881 result_full = result_pipe[head_result];
11882 result = result_full [width_result-1:0];
11883 overflow = result_full [width_result];
11884 mult_is_saturated_int = mult_is_saturated_wire;
11885 accum_is_saturated_latent = accum_saturate_pipe[head_result];
11890 endmodule // end of ALTMULT_ACCUM
11892 //--------------------------------------------------------------------------
11893 // Module Name : altmult_add
11895 // Description : a*b + c*d
11897 // Limitation : Stratix DSP block
11899 // Results expected : signed & unsigned, maximum of 3 pipelines(latency) each.
11900 // possible of zero pipeline.
11902 //--------------------------------------------------------------------------
11903 `timescale 1 ps / 1 ps
11905 module altmult_add ( dataa,
11936 mult0_is_saturated,
11937 mult1_is_saturated,
11938 mult2_is_saturated,
11939 mult3_is_saturated);
11941 // ---------------------
11942 // PARAMETER DECLARATION
11943 // ---------------------
11945 parameter width_a = 1;
11946 parameter width_b = 1;
11947 parameter width_result = 3;
11948 parameter number_of_multipliers = 1;
11949 parameter lpm_type = "altmult_add";
11950 parameter lpm_hint = "UNUSED";
11954 parameter multiplier1_direction = "UNUSED";
11955 parameter multiplier3_direction = "UNUSED";
11957 parameter input_register_a0 = "CLOCK0";
11958 parameter input_aclr_a0 = "ACLR3";
11959 parameter input_source_a0 = "DATAA";
11961 parameter input_register_a1 = "CLOCK0";
11962 parameter input_aclr_a1 = "ACLR3";
11963 parameter input_source_a1 = "DATAA";
11965 parameter input_register_a2 = "CLOCK0";
11966 parameter input_aclr_a2 = "ACLR3";
11967 parameter input_source_a2 = "DATAA";
11969 parameter input_register_a3 = "CLOCK0";
11970 parameter input_aclr_a3 = "ACLR3";
11971 parameter input_source_a3 = "DATAA";
11973 parameter port_signa = "PORT_CONNECTIVITY";
11974 parameter representation_a = "UNUSED";
11975 parameter signed_register_a = "CLOCK0";
11976 parameter signed_aclr_a = "ACLR3";
11977 parameter signed_pipeline_register_a = "CLOCK0";
11978 parameter signed_pipeline_aclr_a = "ACLR3";
11982 parameter input_register_b0 = "CLOCK0";
11983 parameter input_aclr_b0 = "ACLR3";
11984 parameter input_source_b0 = "DATAB";
11986 parameter input_register_b1 = "CLOCK0";
11987 parameter input_aclr_b1 = "ACLR3";
11988 parameter input_source_b1 = "DATAB";
11990 parameter input_register_b2 = "CLOCK0";
11991 parameter input_aclr_b2 = "ACLR3";
11992 parameter input_source_b2 = "DATAB";
11994 parameter input_register_b3 = "CLOCK0";
11995 parameter input_aclr_b3 = "ACLR3";
11996 parameter input_source_b3 = "DATAB";
11998 parameter port_signb = "PORT_CONNECTIVITY";
11999 parameter representation_b = "UNUSED";
12000 parameter signed_register_b = "CLOCK0";
12001 parameter signed_aclr_b = "ACLR3";
12002 parameter signed_pipeline_register_b = "CLOCK0";
12003 parameter signed_pipeline_aclr_b = "ACLR3";
12005 // multiplier parameters
12007 parameter multiplier_register0 = "CLOCK0";
12008 parameter multiplier_aclr0 = "ACLR3";
12009 parameter multiplier_register1 = "CLOCK0";
12010 parameter multiplier_aclr1 = "ACLR3";
12011 parameter multiplier_register2 = "CLOCK0";
12012 parameter multiplier_aclr2 = "ACLR3";
12013 parameter multiplier_register3 = "CLOCK0";
12014 parameter multiplier_aclr3 = "ACLR3";
12016 parameter port_addnsub1 = "PORT_CONNECTIVITY";
12017 parameter addnsub_multiplier_register1 = "CLOCK0";
12018 parameter addnsub_multiplier_aclr1 = "ACLR3";
12019 parameter addnsub_multiplier_pipeline_register1 = "CLOCK0";
12020 parameter addnsub_multiplier_pipeline_aclr1 = "ACLR3";
12022 parameter port_addnsub3 = "PORT_CONNECTIVITY";
12023 parameter addnsub_multiplier_register3 = "CLOCK0";
12024 parameter addnsub_multiplier_aclr3 = "ACLR3";
12025 parameter addnsub_multiplier_pipeline_register3 = "CLOCK0";
12026 parameter addnsub_multiplier_pipeline_aclr3 = "ACLR3";
12028 parameter addnsub1_round_aclr = "ACLR3";
12029 parameter addnsub1_round_pipeline_aclr = "ACLR3";
12030 parameter addnsub1_round_register = "CLOCK0";
12031 parameter addnsub1_round_pipeline_register = "CLOCK0";
12032 parameter addnsub3_round_aclr = "ACLR3";
12033 parameter addnsub3_round_pipeline_aclr = "ACLR3";
12034 parameter addnsub3_round_register = "CLOCK0";
12035 parameter addnsub3_round_pipeline_register = "CLOCK0";
12037 parameter mult01_round_aclr = "ACLR3";
12038 parameter mult01_round_register = "CLOCK0";
12039 parameter mult01_saturation_register = "CLOCK0";
12040 parameter mult01_saturation_aclr = "ACLR3";
12041 parameter mult23_round_register = "CLOCK0";
12042 parameter mult23_round_aclr = "ACLR3";
12043 parameter mult23_saturation_register = "CLOCK0";
12044 parameter mult23_saturation_aclr = "ACLR3";
12046 // StratixII parameters
12047 parameter multiplier01_rounding = "NO";
12048 parameter multiplier01_saturation = "NO";
12049 parameter multiplier23_rounding = "NO";
12050 parameter multiplier23_saturation = "NO";
12051 parameter adder1_rounding = "NO";
12052 parameter adder3_rounding = "NO";
12053 parameter port_mult0_is_saturated = "UNUSED";
12054 parameter port_mult1_is_saturated = "UNUSED";
12055 parameter port_mult2_is_saturated = "UNUSED";
12056 parameter port_mult3_is_saturated = "UNUSED";
12058 // output parameters
12060 parameter output_register = "CLOCK0";
12061 parameter output_aclr = "ACLR0";
12063 // general setting parameters
12065 parameter extra_latency = 0;
12066 parameter dedicated_multiplier_circuitry = "AUTO";
12067 parameter dsp_block_balancing = "AUTO";
12068 parameter intended_device_family = "Stratix";
12070 // ----------------
12071 // PORT DECLARATION
12072 // ----------------
12074 // data input ports
12075 input [number_of_multipliers * width_a -1 : 0] dataa;
12076 input [number_of_multipliers * width_b -1 : 0] datab;
12078 input [width_a -1 : 0] scanina;
12079 input [width_b -1 : 0] scaninb;
12081 input [number_of_multipliers -1 : 0] sourcea;
12082 input [number_of_multipliers -1 : 0] sourceb;
12096 // clock enable ports
12108 // StratixII only input ports
12109 input mult01_round;
12110 input mult23_round;
12111 input mult01_saturation;
12112 input mult23_saturation;
12113 input addnsub1_round;
12114 input addnsub3_round;
12118 output [width_result -1 : 0] result;
12119 output [width_a -1 : 0] scanouta;
12120 output [width_b -1 : 0] scanoutb;
12122 // StratixII only output ports
12123 output mult0_is_saturated;
12124 output mult1_is_saturated;
12125 output mult2_is_saturated;
12126 output mult3_is_saturated;
12128 // -----------------------------------
12129 // Parameters internally used
12130 // -----------------------------------
12131 // Represent the internal used width_a
12132 parameter int_width_a = (((multiplier01_saturation == "NO") && (multiplier23_saturation == "NO") &&
12133 (multiplier01_rounding == "NO") && (multiplier23_rounding == "NO"))? width_a:
12134 (width_a < 18)? 18 : width_a);
12135 // Represent the internal used width_b
12136 parameter int_width_b = (((multiplier01_saturation == "NO") && (multiplier23_saturation == "NO") &&
12137 (multiplier01_rounding == "NO") && (multiplier23_rounding == "NO"))? width_b:
12138 (width_b < 18)? 18 : width_b);
12140 //Represent the internally used width_result
12141 parameter int_width_result = (((multiplier01_saturation == "NO") && (multiplier23_saturation == "NO") &&
12142 (multiplier01_rounding == "NO") && (multiplier23_rounding == "NO"))? width_result:
12143 (width_result > (int_width_a + int_width_b))? width_result + width_result - int_width_a - int_width_b:
12144 int_width_a + int_width_b);
12146 // Represent the internally used width_result
12147 parameter int_mult_diff_bit = (((multiplier01_saturation == "NO") && (multiplier23_saturation == "NO") &&
12148 (multiplier01_rounding == "NO") && (multiplier23_rounding == "NO"))? 0:
12149 (int_width_a - width_a + int_width_b - width_b));
12151 parameter sat_ini_value = (((multiplier01_saturation == "NO") && (multiplier23_saturation == "NO"))? 3:
12152 int_width_a + int_width_b - 3);
12154 // -----------------------------------
12155 // Constants internally used
12156 // -----------------------------------
12157 // Represent the number of bits needed to be rounded in multiplier where the
12158 // value 17 here refers to the 2 sign bits and the 15 wanted bits for rounding
12159 `define MULT_ROUND_BITS (((multiplier01_rounding == "NO") && (multiplier23_rounding == "NO"))? 1 : (int_width_a + int_width_b) - 17)
12161 // Represent the number of bits needed to be rounded in adder where the
12162 // value 18 here refers to the 3 sign bits and the 15 wanted bits for rounding.
12163 `define ADDER_ROUND_BITS (((multiplier01_rounding == "NO") && (multiplier23_rounding == "NO"))? 1 :(int_width_a + int_width_b) - 17)
12171 reg [int_width_result :0] temp_sum;
12172 reg [int_width_result : 0] mult_res_ext;
12173 reg [int_width_result : 0] temp_sum_reg;
12175 reg [4 * int_width_a -1 : 0] mult_a_reg;
12176 reg [4 * int_width_b -1 : 0] mult_b_reg;
12179 reg [(int_width_a + int_width_b) -1:0] mult_res_0;
12180 reg [(int_width_a + int_width_b) -1:0] mult_res_1;
12181 reg [(int_width_a + int_width_b) -1:0] mult_res_2;
12182 reg [(int_width_a + int_width_b) -1:0] mult_res_3;
12185 reg [4 * (int_width_a + int_width_b) -1:0] mult_res_reg;
12186 reg [(int_width_a + int_width_b - 1) :0] mult_res_temp;
12189 reg sign_a_pipe_reg;
12191 reg sign_b_pipe_reg;
12195 reg addsub1_pipe_reg;
12198 reg addsub3_pipe_reg;
12201 // StratixII features related internal reg type
12203 reg [(int_width_a + int_width_b + 3) -1 : 0] mult0_round_out;
12204 reg [(int_width_a + int_width_b + 3) -1 : 0] mult0_saturate_out;
12205 reg [(int_width_a + int_width_b + 3) -1 : 0] mult0_result;
12206 reg mult0_saturate_overflow;
12207 reg mult0_saturate_overflow_stat;
12209 reg [(int_width_a + int_width_b + 3) -1 : 0] mult1_round_out;
12210 reg [(int_width_a + int_width_b + 3) -1 : 0] mult1_saturate_out;
12211 reg [(int_width_a + int_width_b) -1 : 0] mult1_result;
12212 reg mult1_saturate_overflow;
12213 reg mult1_saturate_overflow_stat;
12215 reg [(int_width_a + int_width_b + 3) -1 : 0] mult2_round_out;
12216 reg [(int_width_a + int_width_b + 3) -1 : 0] mult2_saturate_out;
12217 reg [(int_width_a + int_width_b) -1 : 0] mult2_result;
12218 reg mult2_saturate_overflow;
12219 reg mult2_saturate_overflow_stat;
12221 reg [(int_width_a + int_width_b + 3) -1 : 0] mult3_round_out;
12222 reg [(int_width_a + int_width_b + 3) -1 : 0] mult3_saturate_out;
12223 reg [(int_width_a + int_width_b) -1 : 0] mult3_result;
12224 reg mult3_saturate_overflow;
12225 reg mult3_saturate_overflow_stat;
12227 reg mult01_round_reg;
12228 reg mult01_saturate_reg;
12229 reg mult23_round_reg;
12230 reg mult23_saturate_reg;
12231 reg [3 : 0] mult_saturate_overflow_reg;
12232 reg [3 : 0] mult_saturate_overflow_pipe_reg;
12234 reg [int_width_result : 0] adder1_round_out;
12235 reg [int_width_result : 0] adder1_result;
12236 reg addnsub1_round_reg;
12237 reg addnsub1_round_pipe_reg;
12239 reg [int_width_result : 0] adder3_round_out;
12240 reg [int_width_result : 0] adder3_result;
12241 reg addnsub3_round_reg;
12242 reg addnsub3_round_pipe_reg;
12246 //-----------------
12248 //-----------------
12253 tri0 [4 * int_width_a -1 : 0] dataa_int;
12254 tri0 [4 * int_width_b -1 : 0] datab_int;
12255 tri0 [4 * int_width_a -1 : 0] new_dataa_int;
12256 tri0 [4 * int_width_b -1 : 0] new_datab_int;
12257 reg [4 * int_width_a -1 : 0] dataa_reg;
12258 reg [4 * int_width_b -1 : 0] datab_reg;
12259 tri0 [int_width_a - 1 : 0] scanina_z;
12260 tri0 [int_width_b - 1 : 0] scaninb_z;
12262 // Tri wire for clear signal
12263 tri0 input_reg_a0_wire_clr;
12264 tri0 input_reg_a1_wire_clr;
12265 tri0 input_reg_a2_wire_clr;
12266 tri0 input_reg_a3_wire_clr;
12268 tri0 input_reg_b0_wire_clr;
12269 tri0 input_reg_b1_wire_clr;
12270 tri0 input_reg_b2_wire_clr;
12271 tri0 input_reg_b3_wire_clr;
12273 tri0 sign_reg_a_wire_clr;
12274 tri0 sign_pipe_a_wire_clr;
12276 tri0 sign_reg_b_wire_clr;
12277 tri0 sign_pipe_b_wire_clr;
12279 tri0 addsub1_reg_wire_clr;
12280 tri0 addsub1_pipe_wire_clr;
12282 tri0 addsub3_reg_wire_clr;
12283 tri0 addsub3_pipe_wire_clr;
12285 tri0 multiplier_reg0_wire_clr;
12286 tri0 multiplier_reg1_wire_clr;
12287 tri0 multiplier_reg2_wire_clr;
12288 tri0 multiplier_reg3_wire_clr;
12290 tri0 addnsub1_round_wire_clr;
12291 tri0 addnsub1_round_pipe_wire_clr;
12293 tri0 addnsub3_round_wire_clr;
12294 tri0 addnsub3_round_pipe_wire_clr;
12296 tri0 mult01_round_wire_clr;
12297 tri0 mult01_saturate_wire_clr;
12299 tri0 mult23_round_wire_clr;
12300 tri0 mult23_saturate_wire_clr;
12302 tri0 output_reg_wire_clr;
12304 tri0 [3 : 0] sourcea_wire;
12305 tri0 [3 : 0] sourceb_wire;
12309 // Tri wire for enable signal
12311 tri1 input_reg_a0_wire_en;
12312 tri1 input_reg_a1_wire_en;
12313 tri1 input_reg_a2_wire_en;
12314 tri1 input_reg_a3_wire_en;
12316 tri1 input_reg_b0_wire_en;
12317 tri1 input_reg_b1_wire_en;
12318 tri1 input_reg_b2_wire_en;
12319 tri1 input_reg_b3_wire_en;
12322 tri1 sign_reg_a_wire_en;
12323 tri1 sign_pipe_a_wire_en;
12325 tri1 sign_reg_b_wire_en;
12326 tri1 sign_pipe_b_wire_en;
12328 tri1 addsub1_reg_wire_en;
12329 tri1 addsub1_pipe_wire_en;
12331 tri1 addsub3_reg_wire_en;
12332 tri1 addsub3_pipe_wire_en;
12334 tri1 multiplier_reg0_wire_en;
12335 tri1 multiplier_reg1_wire_en;
12336 tri1 multiplier_reg2_wire_en;
12337 tri1 multiplier_reg3_wire_en;
12339 tri1 addnsub1_round_wire_en;
12340 tri1 addnsub1_round_pipe_wire_en;
12342 tri1 addnsub3_round_wire_en;
12343 tri1 addnsub3_round_pipe_wire_en;
12345 tri1 mult01_round_wire_en;
12346 tri1 mult01_saturate_wire_en;
12348 tri1 mult23_round_wire_en;
12349 tri1 mult23_saturate_wire_en;
12351 tri1 output_reg_wire_en;
12357 // ----------------
12358 // WIRE DECLARATION
12359 // ----------------
12361 // Wire for Clock signals
12362 wire input_reg_a0_wire_clk;
12363 wire input_reg_a1_wire_clk;
12364 wire input_reg_a2_wire_clk;
12365 wire input_reg_a3_wire_clk;
12367 wire input_reg_b0_wire_clk;
12368 wire input_reg_b1_wire_clk;
12369 wire input_reg_b2_wire_clk;
12370 wire input_reg_b3_wire_clk;
12372 wire sign_reg_a_wire_clk;
12373 wire sign_pipe_a_wire_clk;
12375 wire sign_reg_b_wire_clk;
12376 wire sign_pipe_b_wire_clk;
12378 wire addsub1_reg_wire_clk;
12379 wire addsub1_pipe_wire_clk;
12381 wire addsub3_reg_wire_clk;
12382 wire addsub3_pipe_wire_clk;
12384 wire multiplier_reg0_wire_clk;
12385 wire multiplier_reg1_wire_clk;
12386 wire multiplier_reg2_wire_clk;
12387 wire multiplier_reg3_wire_clk;
12389 wire output_reg_wire_clk;
12391 wire addnsub1_round_wire_clk;
12392 wire addnsub1_round_pipe_wire_clk;
12393 wire addnsub1_round_wire;
12394 wire addnsub1_round_pipe_wire;
12395 wire addnsub1_round_pre;
12396 wire addnsub3_round_wire_clk;
12397 wire addnsub3_round_pipe_wire_clk;
12398 wire addnsub3_round_wire;
12399 wire addnsub3_round_pipe_wire;
12400 wire addnsub3_round_pre;
12402 wire mult01_round_wire_clk;
12403 wire mult01_saturate_wire_clk;
12404 wire mult23_round_wire_clk;
12405 wire mult23_saturate_wire_clk;
12406 wire mult01_round_pre;
12407 wire mult01_saturate_pre;
12408 wire mult01_round_wire;
12409 wire mult01_saturate_wire;
12410 wire mult23_round_pre;
12411 wire mult23_saturate_pre;
12412 wire mult23_round_wire;
12413 wire mult23_saturate_wire;
12414 wire [3 : 0] mult_is_saturate_vec;
12415 wire [3 : 0] mult_saturate_overflow_vec;
12417 wire [4 * int_width_a -1 : 0] mult_a_pre;
12418 wire [4 * int_width_b -1 : 0] mult_b_pre;
12420 wire [int_width_a -1 : 0] scanouta;
12421 wire [int_width_b -1 : 0] scanoutb;
12429 wire [4 * int_width_a -1 : 0] mult_a_wire;
12430 wire [4 * int_width_b -1 : 0] mult_b_wire;
12431 wire [4 * (int_width_a + int_width_b) -1:0] mult_res_wire;
12432 wire sign_a_pipe_wire;
12434 wire sign_b_pipe_wire;
12437 wire addsub1_pipe_wire;
12439 wire addsub3_pipe_wire;
12441 wire [int_width_a -1 : 0] i_scanina;
12442 wire [int_width_b -1 : 0] i_scaninb;
12444 wire [(int_width_result - 1): 0] output_reg_wire_result;
12445 wire [31:0] head_result_wire;
12446 reg [(int_width_result - 1): 0] output_laten_result;
12447 reg [(int_width_result - 1): 0] result_pipe [extra_latency : 0];
12448 reg [31:0] head_result;
12449 integer head_result_int;
12452 // -------------------
12453 // INTEGER DECLARATION
12454 // -------------------
12455 integer num_bit_mult0;
12456 integer num_bit_mult1;
12457 integer num_bit_mult2;
12458 integer num_bit_mult3;
12465 // ------------------------
12466 // COMPONENT INSTANTIATIONS
12467 // ------------------------
12468 ALTERA_DEVICE_FAMILIES dev ();
12471 // -----------------------------------------------------------------------------
12472 // This block checks if the two numbers to be multiplied (mult_a/mult_b) is to
12473 // be interpreted as a negative number or not. If so, then two's complement is
12475 // The numbers are then multipled. The sign of the result (positive or negative)
12476 // is determined based on the sign of the two input numbers
12477 // ------------------------------------------------------------------------------
12479 function [(int_width_a + int_width_b - 1):0] do_multiply;
12480 input [32 : 0] multiplier;
12485 reg [int_width_a + int_width_b -1 :0] temp_mult_zero;
12486 reg [int_width_a + int_width_b -1 :0] temp_mult;
12487 reg [int_width_a -1 :0] op_a;
12488 reg [int_width_b -1 :0] op_b;
12489 reg [int_width_a -1 :0] op_a_int;
12490 reg [int_width_b -1 :0] op_b_int;
12493 reg temp_mult_signed;
12495 temp_mult_zero = 0;
12498 op_a = mult_a_wire >> (multiplier * int_width_a);
12499 op_b = mult_b_wire >> (multiplier * int_width_b);
12501 neg_a = op_a[int_width_a-1] & (signa_wire);
12502 neg_b = op_b[int_width_b-1] & (signb_wire);
12504 op_a_int = (neg_a == 1) ? (~op_a + 1) : op_a;
12505 op_b_int = (neg_b == 1) ? (~op_b + 1) : op_b;
12507 temp_mult = op_a_int * op_b_int;
12508 temp_mult = (neg_a ^ neg_b) ? (temp_mult_zero - temp_mult) : temp_mult;
12510 do_multiply = temp_mult;
12517 // --------------------------------------------------------------
12518 // initialization block of all the internal signals and registers
12519 // --------------------------------------------------------------
12523 // Checking for invalid parameters, in case Wizard is bypassed (hand-modified).
12524 if (number_of_multipliers > 4)
12526 $display("Altmult_add does not currently support NUMBER_OF_MULTIPLIERS > 4");
12529 if (number_of_multipliers <= 0)
12531 $display("NUMBER_OF_MULTIPLIERS must be greater than 0.");
12538 $display("Error: width_a must be greater than 0.");
12543 $display("Error: width_b must be greater than 0.");
12546 if (width_result <= 0)
12548 $display("Error: width_result must be greater than 0.");
12552 if ((input_source_a0 != "DATAA") &&
12553 (input_source_a0 != "SCANA") &&
12554 (input_source_a0 != "VARIABLE"))
12556 $display("Error: The INPUT_SOURCE_A0 parameter is set to an illegal value.");
12560 if ((input_source_a1 != "DATAA") &&
12561 (input_source_a1 != "SCANA") &&
12562 (input_source_a1 != "VARIABLE"))
12564 $display("Error: The INPUT_SOURCE_A1 parameter is set to an illegal value.");
12568 if ((input_source_a2 != "DATAA") &&
12569 (input_source_a2 != "SCANA") &&
12570 (input_source_a2 != "VARIABLE"))
12572 $display("Error: The INPUT_SOURCE_A2 parameter is set to an illegal value.");
12576 if ((input_source_a3 != "DATAA") &&
12577 (input_source_a3 != "SCANA") &&
12578 (input_source_a3 != "VARIABLE"))
12580 $display("Error: The INPUT_SOURCE_A3 parameter is set to an illegal value.");
12584 if ((input_source_b0 != "DATAB") &&
12585 (input_source_b0 != "SCANB") &&
12586 (input_source_b0 != "VARIABLE"))
12588 $display("Error: The INPUT_SOURCE_B0 parameter is set to an illegal value.");
12592 if ((input_source_b1 != "DATAB") &&
12593 (input_source_b1 != "SCANB") &&
12594 (input_source_b1 != "VARIABLE"))
12596 $display("Error: The INPUT_SOURCE_B1 parameter is set to an illegal value.");
12600 if ((input_source_b2 != "DATAB") &&
12601 (input_source_b2 != "SCANB") &&
12602 (input_source_b2 != "VARIABLE"))
12604 $display("Error: The INPUT_SOURCE_B2 parameter is set to an illegal value.");
12608 if ((input_source_b3 != "DATAB") &&
12609 (input_source_b3 != "SCANB") &&
12610 (input_source_b3 != "VARIABLE"))
12612 $display("Error: The INPUT_SOURCE_B3 parameter is set to an illegal value.");
12616 if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) &&
12617 (input_source_a0 == "VARIABLE"))
12619 $display("Error: Input source as VARIABLE is not supported in %s device family", intended_device_family);
12623 if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) &&
12624 (input_source_a1 == "VARIABLE"))
12626 $display("Error: Input source as VARIABLE is not supported in %s device family", intended_device_family);
12630 if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) &&
12631 (input_source_a2 == "VARIABLE"))
12633 $display("Error: Input source as VARIABLE is not supported in %s device family", intended_device_family);
12637 if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) &&
12638 (input_source_a3 == "VARIABLE"))
12640 $display("Error: Input source as VARIABLE is not supported in %s device family", intended_device_family);
12644 if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) &&
12645 (input_source_b0 == "VARIABLE"))
12647 $display("Error: Input source as VARIABLE is not supported in %s device family", intended_device_family);
12651 if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) &&
12652 (input_source_b1 == "VARIABLE"))
12654 $display("Error: Input source as VARIABLE is not supported in %s device family", intended_device_family);
12658 if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) &&
12659 (input_source_b2 == "VARIABLE"))
12661 $display("Error: Input source as VARIABLE is not supported in %s device family", intended_device_family);
12665 if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) &&
12666 (input_source_b3 == "VARIABLE"))
12668 $display("Error: Input source as VARIABLE is not supported in %s device family", intended_device_family);
12672 if ((dedicated_multiplier_circuitry != "AUTO") &&
12673 (dedicated_multiplier_circuitry != "YES") &&
12674 (dedicated_multiplier_circuitry != "NO"))
12676 $display("Error: The DEDICATED_MULTIPLIER_CIRCUITRY parameter is set to an illegal value.");
12680 if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) &&
12681 ((multiplier01_rounding == "YES") || (multiplier23_rounding == "YES") ||
12682 (multiplier01_rounding == "VARIABLE") || (multiplier23_rounding == "VARIABLE")))
12684 $display("Error: Rounding for multiplier is not supported in %s device family", intended_device_family);
12688 if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) &&
12689 ((adder1_rounding == "YES") || (adder3_rounding == "YES") ||
12690 (adder1_rounding == "VARIABLE") || (adder3_rounding == "VARIABLE")))
12692 $display("Error: Rounding for adder is not supported in %s device family", intended_device_family);
12696 if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) &&
12697 ((multiplier01_saturation == "YES") || (multiplier23_saturation == "YES") ||
12698 (multiplier01_saturation == "VARIABLE") || (multiplier23_saturation == "VARIABLE")))
12700 $display("Error: Saturation for multiplier is not supported in %s device family", intended_device_family);
12704 if ((multiplier01_saturation == "NO") && (multiplier23_saturation == "NO") &&
12705 (multiplier01_rounding == "NO") && (multiplier23_rounding == "NO"))
12707 if (int_width_result != width_result)
12709 $display ("Error: Internal parameter setting of int_width_result is illegal");
12713 if (int_mult_diff_bit != 0)
12715 $display ("Error: Internal parameter setting of int_mult_diff_bit is illegal");
12722 if (((width_a < 18) && (int_width_a != 18)) ||
12723 ((width_a >= 18) && (int_width_a != width_a)))
12725 $display ("Error: Internal parameter setting of int_width_a is illegal");
12730 if (((width_b < 18) && (int_width_b != 18)) ||
12731 ((width_b >= 18) && (int_width_b != width_b)))
12733 $display ("Error: Internal parameter setting of int_width_b is illegal");
12738 if (int_width_result > (int_width_a + int_width_b))
12740 if (int_width_result != (width_result + width_result - int_width_a - int_width_b))
12742 $display ("Error: Internal parameter setting for int_width_result is illegal");
12747 if (int_width_result != (int_width_a + int_width_b))
12749 $display ("Error: Internal parameter setting for int_width_result is illegal");
12753 if (int_mult_diff_bit != (int_width_a - width_a + int_width_b - width_b))
12755 $display ("Error: Internal parameter setting of int_mult_diff_bit is illegal");
12768 sign_a_reg = ((port_signa == "PORT_CONNECTIVITY")?
12769 (representation_a != "UNUSED" ? (representation_a == "SIGNED" ? 1 : 0) : 0) :
12770 (port_signa == "PORT_USED")? 0 :
12771 (port_signa == "PORT_UNUSED")? (representation_a == "SIGNED" ? 1 : 0) : 0);
12773 sign_a_pipe_reg = ((port_signa == "PORT_CONNECTIVITY")?
12774 (representation_a != "UNUSED" ? (representation_a == "SIGNED" ? 1 : 0) : 0) :
12775 (port_signa == "PORT_USED")? 0 :
12776 (port_signa == "PORT_UNUSED")? (representation_a == "SIGNED" ? 1 : 0) : 0);
12778 sign_b_reg = ((port_signb == "PORT_CONNECTIVITY")?
12779 (representation_b != "UNUSED" ? (representation_b == "SIGNED" ? 1 : 0) : 0) :
12780 (port_signb == "PORT_USED")? 0 :
12781 (port_signb == "PORT_UNUSED")? (representation_b == "SIGNED" ? 1 : 0) : 0);
12783 sign_b_pipe_reg = ((port_signb == "PORT_CONNECTIVITY")?
12784 (representation_b != "UNUSED" ? (representation_b == "SIGNED" ? 1 : 0) : 0) :
12785 (port_signb == "PORT_USED")? 0 :
12786 (port_signb == "PORT_UNUSED")? (representation_b == "SIGNED" ? 1 : 0) : 0);
12788 addsub1_reg = ((port_addnsub1 == "PORT_CONNECTIVITY")?
12789 (multiplier1_direction != "UNUSED" ? (multiplier1_direction == "ADD" ? 1 : 0) : 0) :
12790 (port_addnsub1 == "PORT_USED")? 0 :
12791 (port_addnsub1 == "PORT_UNUSED")? (multiplier1_direction == "ADD" ? 1 : 0) : 0);
12793 addsub1_pipe_reg = addsub1_reg;
12795 addsub3_reg = ((port_addnsub3 == "PORT_CONNECTIVITY")?
12796 (multiplier3_direction != "UNUSED" ? (multiplier3_direction == "ADD" ? 1 : 0) : 0) :
12797 (port_addnsub3 == "PORT_USED")? 0 :
12798 (port_addnsub3 == "PORT_UNUSED")? (multiplier3_direction == "ADD" ? 1 : 0) : 0);
12800 addsub3_pipe_reg = addsub3_reg;
12802 // StratixII related reg type initialization
12804 mult0_round_out = 0;
12805 mult0_saturate_out = 0;
12807 mult0_saturate_overflow = 0;
12809 mult1_round_out = 0;
12810 mult1_saturate_out = 0;
12812 mult1_saturate_overflow = 0;
12814 mult_saturate_overflow_reg [3] = 0;
12815 mult_saturate_overflow_reg [2] = 0;
12816 mult_saturate_overflow_reg [1] = 0;
12817 mult_saturate_overflow_reg [0] = 0;
12819 mult_saturate_overflow_pipe_reg [3] = 0;
12820 mult_saturate_overflow_pipe_reg [2] = 0;
12821 mult_saturate_overflow_pipe_reg [1] = 0;
12822 mult_saturate_overflow_pipe_reg [0] = 0;
12826 for ( num_stor = extra_latency; num_stor >= 0; num_stor = num_stor - 1 )
12828 result_pipe[num_stor] = {int_width_result{1'b0}};
12831 end // end initialization block
12833 assign signa_z = signa;
12834 assign signb_z = signb;
12835 assign addnsub1_z = addnsub1;
12836 assign addnsub3_z = addnsub3;
12837 assign scanina_z[width_a - 1 : 0] = scanina[width_a - 1 : 0];
12838 assign scaninb_z[width_b - 1 : 0] = scaninb[width_b - 1 : 0];
12840 always @(dataa or datab)
12842 dataa_reg[(number_of_multipliers * width_a) - 1:0] = dataa[(number_of_multipliers* width_a) -1:0];
12843 datab_reg[(number_of_multipliers * width_b) - 1: 0] = datab[(number_of_multipliers * width_b) - 1:0];
12846 assign new_dataa_int[int_width_a - 1:int_width_a - width_a] = (number_of_multipliers >= 1) ? dataa_reg[width_a - 1:0]: {width_a{1'b0}};
12848 assign new_dataa_int[(2 * int_width_a) - 1: (2 * int_width_a) - width_a] = (number_of_multipliers >= 2)? dataa_reg[(2 * width_a) - 1: width_a] : {width_a{1'b0}};
12850 assign new_dataa_int[(3 * int_width_a) - 1: (3 * int_width_a) - width_a] = (number_of_multipliers >= 3)? dataa_reg[(3 * width_a) - 1:(2 * width_a)] : {width_a{1'b0}};
12852 assign new_dataa_int[(4 * int_width_a) - 1: (4 * int_width_a) - width_a] = (number_of_multipliers >= 4) ? dataa_reg[(4 * width_a) - 1:(3 * width_a)] : {width_a{1'b0}};
12854 assign new_datab_int[int_width_b - 1:int_width_b - width_b] = (number_of_multipliers >= 1) ? datab_reg[width_b - 1:0]: {width_b{1'b0}};
12856 assign new_datab_int[(2 * int_width_b) - 1: (2 * int_width_b) - width_b] = (number_of_multipliers >= 2)? datab_reg[(2 * width_b) - 1:width_b]:{width_b{1'b0}};
12858 assign new_datab_int[(3 * int_width_b) - 1: (3 * int_width_b) - width_b] = (number_of_multipliers >= 3)? datab_reg[(3 * width_b) - 1:(2 * width_b)] : {width_b{1'b0}};
12860 assign new_datab_int[(4 * int_width_b) - 1: (4 * int_width_b) - width_b] = (number_of_multipliers >= 4) ? datab_reg[(4 * width_b) - 1:(3 * width_b)] : {width_b{1'b0}};
12864 assign dataa_int[number_of_multipliers * int_width_a-1:0] = (((multiplier01_saturation == "NO") && (multiplier23_saturation == "NO") &&
12865 (multiplier01_rounding == "NO") && (multiplier23_rounding == "NO"))? dataa[number_of_multipliers * width_a - 1:0]:
12866 (width_a < 18)? new_dataa_int[number_of_multipliers * int_width_a-1:0] : dataa[number_of_multipliers * width_a - 1:0]);
12868 assign datab_int[number_of_multipliers * int_width_b-1:0] = (((multiplier01_saturation == "NO") && (multiplier23_saturation == "NO") &&
12869 (multiplier01_rounding == "NO") && (multiplier23_rounding == "NO"))? datab[number_of_multipliers * width_b - 1:0]:
12870 (width_b < 18)? new_datab_int[number_of_multipliers * int_width_b - 1:0] : datab[number_of_multipliers * width_b - 1:0]);
12873 assign addnsub1_round_pre = addnsub1_round;
12874 assign addnsub3_round_pre = addnsub3_round;
12875 assign mult01_round_pre = mult01_round;
12876 assign mult01_saturate_pre = mult01_saturation;
12877 assign mult23_round_pre = mult23_round;
12878 assign mult23_saturate_pre = mult23_saturation;
12880 // ---------------------------------------------------------
12881 // This block updates the output port for each multiplier's
12882 // saturation port only if port_mult0_is_saturated is set to used
12883 // ---------------------------------------------------------
12886 assign mult0_is_saturated = (port_mult0_is_saturated == "UNUSED")? 1'bz:
12887 (port_mult0_is_saturated == "USED")? mult_is_saturate_vec[0]: 1'bz;
12889 assign mult1_is_saturated = (port_mult1_is_saturated == "UNUSED")? 1'bz:
12890 (port_mult1_is_saturated == "USED")? mult_is_saturate_vec[1]: 1'bz;
12892 assign mult2_is_saturated = (port_mult2_is_saturated == "UNUSED")? 1'bz:
12893 (port_mult2_is_saturated == "USED")? mult_is_saturate_vec[2]: 1'bz;
12895 assign mult3_is_saturated = (port_mult3_is_saturated == "UNUSED")? 1'bz:
12896 (port_mult3_is_saturated == "USED")? mult_is_saturate_vec[3]: 1'bz;
12898 assign sourcea_wire[number_of_multipliers - 1 : 0] = sourcea[number_of_multipliers - 1 : 0];
12900 assign sourceb_wire[number_of_multipliers - 1 : 0] = sourceb[number_of_multipliers - 1 : 0];
12904 // ---------------------------------------------------------
12905 // This block updates the internal clock signals accordingly
12906 // every time the global clock signal changes state
12907 // ---------------------------------------------------------
12909 assign input_reg_a0_wire_clk = (input_register_a0 == "CLOCK0")? clock0:
12910 (input_register_a0 == "UNREGISTERED")? 0:
12911 (input_register_a0 == "CLOCK1")? clock1:
12912 (input_register_a0 == "CLOCK2")? clock2:
12913 (input_register_a0 == "CLOCK3")? clock3: 0;
12916 assign input_reg_a1_wire_clk = (input_register_a1 == "CLOCK0")? clock0:
12917 (input_register_a1 == "UNREGISTERED")? 0:
12918 (input_register_a1 == "CLOCK1")? clock1:
12919 (input_register_a1 == "CLOCK2")? clock2:
12920 (input_register_a1 == "CLOCK3")? clock3: 0;
12923 assign input_reg_a2_wire_clk = (input_register_a2 == "CLOCK0")? clock0:
12924 (input_register_a2 == "UNREGISTERED")? 0:
12925 (input_register_a2 == "CLOCK1")? clock1:
12926 (input_register_a2 == "CLOCK2")? clock2:
12927 (input_register_a2 == "CLOCK3")? clock3: 0;
12931 assign input_reg_a3_wire_clk = (input_register_a3 == "CLOCK0")? clock0:
12932 (input_register_a3 == "UNREGISTERED")? 0:
12933 (input_register_a3 == "CLOCK1")? clock1:
12934 (input_register_a3 == "CLOCK2")? clock2:
12935 (input_register_a3 == "CLOCK3")? clock3: 0;
12938 assign input_reg_b0_wire_clk = (input_register_b0 == "CLOCK0")? clock0:
12939 (input_register_b0 == "UNREGISTERED")? 0:
12940 (input_register_b0 == "CLOCK1")? clock1:
12941 (input_register_b0 == "CLOCK2")? clock2:
12942 (input_register_b0 == "CLOCK3")? clock3: 0;
12945 assign input_reg_b1_wire_clk = (input_register_b1 == "CLOCK0")? clock0:
12946 (input_register_b1 == "UNREGISTERED")? 0:
12947 (input_register_b1 == "CLOCK1")? clock1:
12948 (input_register_b1 == "CLOCK2")? clock2:
12949 (input_register_b1 == "CLOCK3")? clock3: 0;
12952 assign input_reg_b2_wire_clk = (input_register_b2 == "CLOCK0")? clock0:
12953 (input_register_b2 == "UNREGISTERED")? 0:
12954 (input_register_b2 == "CLOCK1")? clock1:
12955 (input_register_b2 == "CLOCK2")? clock2:
12956 (input_register_b2 == "CLOCK3")? clock3: 0;
12959 assign input_reg_b3_wire_clk = (input_register_b3 == "CLOCK0")? clock0:
12960 (input_register_b3 == "UNREGISTERED")? 0:
12961 (input_register_b3 == "CLOCK1")? clock1:
12962 (input_register_b3 == "CLOCK2")? clock2:
12963 (input_register_b3 == "CLOCK3")? clock3: 0;
12966 assign addsub1_reg_wire_clk = (addnsub_multiplier_register1 == "CLOCK0")? clock0:
12967 (addnsub_multiplier_register1 == "UNREGISTERED")? 0:
12968 (addnsub_multiplier_register1 == "CLOCK1")? clock1:
12969 (addnsub_multiplier_register1 == "CLOCK2")? clock2:
12970 (addnsub_multiplier_register1 == "CLOCK3")? clock3: 0;
12973 assign addsub1_pipe_wire_clk = (addnsub_multiplier_pipeline_register1 == "CLOCK0")? clock0:
12974 (addnsub_multiplier_pipeline_register1 == "UNREGISTERED")? 0:
12975 (addnsub_multiplier_pipeline_register1 == "CLOCK1")? clock1:
12976 (addnsub_multiplier_pipeline_register1 == "CLOCK2")? clock2:
12977 (addnsub_multiplier_pipeline_register1 == "CLOCK3")? clock3: 0;
12981 assign addsub3_reg_wire_clk = (addnsub_multiplier_register3 == "CLOCK0")? clock0:
12982 (addnsub_multiplier_register3 == "UNREGISTERED")? 0:
12983 (addnsub_multiplier_register3 == "CLOCK1")? clock1:
12984 (addnsub_multiplier_register3 == "CLOCK2")? clock2:
12985 (addnsub_multiplier_register3 == "CLOCK3")? clock3: 0;
12989 assign addsub3_pipe_wire_clk = (addnsub_multiplier_pipeline_register3 == "CLOCK0")? clock0:
12990 (addnsub_multiplier_pipeline_register3 == "UNREGISTERED")? 0:
12991 (addnsub_multiplier_pipeline_register3 == "CLOCK1")? clock1:
12992 (addnsub_multiplier_pipeline_register3 == "CLOCK2")? clock2:
12993 (addnsub_multiplier_pipeline_register3 == "CLOCK3")? clock3: 0;
12998 assign sign_reg_a_wire_clk = (signed_register_a == "CLOCK0")? clock0:
12999 (signed_register_a == "UNREGISTERED")? 0:
13000 (signed_register_a == "CLOCK1")? clock1:
13001 (signed_register_a == "CLOCK2")? clock2:
13002 (signed_register_a == "CLOCK3")? clock3: 0;
13006 assign sign_pipe_a_wire_clk = (signed_pipeline_register_a == "CLOCK0")? clock0:
13007 (signed_pipeline_register_a == "UNREGISTERED")? 0:
13008 (signed_pipeline_register_a == "CLOCK1")? clock1:
13009 (signed_pipeline_register_a == "CLOCK2")? clock2:
13010 (signed_pipeline_register_a == "CLOCK3")? clock3: 0;
13014 assign sign_reg_b_wire_clk = (signed_register_b == "CLOCK0")? clock0:
13015 (signed_register_b == "UNREGISTERED")? 0:
13016 (signed_register_b == "CLOCK1")? clock1:
13017 (signed_register_b == "CLOCK2")? clock2:
13018 (signed_register_b == "CLOCK3")? clock3: 0;
13022 assign sign_pipe_b_wire_clk = (signed_pipeline_register_b == "CLOCK0")? clock0:
13023 (signed_pipeline_register_b == "UNREGISTERED")? 0:
13024 (signed_pipeline_register_b == "CLOCK1")? clock1:
13025 (signed_pipeline_register_b == "CLOCK2")? clock2:
13026 (signed_pipeline_register_b == "CLOCK3")? clock3: 0;
13030 assign multiplier_reg0_wire_clk = (multiplier_register0 == "CLOCK0")? clock0:
13031 (multiplier_register0 == "UNREGISTERED")? 0:
13032 (multiplier_register0 == "CLOCK1")? clock1:
13033 (multiplier_register0 == "CLOCK2")? clock2:
13034 (multiplier_register0 == "CLOCK3")? clock3: 0;
13038 assign multiplier_reg1_wire_clk = (multiplier_register1 == "CLOCK0")? clock0:
13039 (multiplier_register1 == "UNREGISTERED")? 0:
13040 (multiplier_register1 == "CLOCK1")? clock1:
13041 (multiplier_register1 == "CLOCK2")? clock2:
13042 (multiplier_register1 == "CLOCK3")? clock3: 0;
13045 assign multiplier_reg2_wire_clk = (multiplier_register2 == "CLOCK0")? clock0:
13046 (multiplier_register2 == "UNREGISTERED")? 0:
13047 (multiplier_register2 == "CLOCK1")? clock1:
13048 (multiplier_register2 == "CLOCK2")? clock2:
13049 (multiplier_register2 == "CLOCK3")? clock3: 0;
13053 assign multiplier_reg3_wire_clk = (multiplier_register3 == "CLOCK0")? clock0:
13054 (multiplier_register3 == "UNREGISTERED")? 0:
13055 (multiplier_register3 == "CLOCK1")? clock1:
13056 (multiplier_register3 == "CLOCK2")? clock2:
13057 (multiplier_register3 == "CLOCK3")? clock3: 0;
13061 assign output_reg_wire_clk = (output_register == "CLOCK0")? clock0:
13062 (output_register == "UNREGISTERED")? 0:
13063 (output_register == "CLOCK1")? clock1:
13064 (output_register == "CLOCK2")? clock2:
13065 (output_register == "CLOCK3")? clock3: 0;
13068 assign addnsub1_round_wire_clk = (addnsub1_round_register == "CLOCK0")? clock0:
13069 (addnsub1_round_register == "UNREGISTERED")? 0:
13070 (addnsub1_round_register == "CLOCK1")? clock1:
13071 (addnsub1_round_register == "CLOCK2")? clock2:
13072 (addnsub1_round_register == "CLOCK3")? clock3: 0;
13075 assign addnsub1_round_pipe_wire_clk = (addnsub1_round_pipeline_register == "CLOCK0")? clock0:
13076 (addnsub1_round_pipeline_register == "UNREGISTERED")? 0:
13077 (addnsub1_round_pipeline_register == "CLOCK1")? clock1:
13078 (addnsub1_round_pipeline_register == "CLOCK2")? clock2:
13079 (addnsub1_round_pipeline_register == "CLOCK3")? clock3: 0;
13082 assign addnsub3_round_wire_clk = (addnsub3_round_register == "CLOCK0")? clock0:
13083 (addnsub3_round_register == "UNREGISTERED")? 0:
13084 (addnsub3_round_register == "CLOCK1")? clock1:
13085 (addnsub3_round_register == "CLOCK2")? clock2:
13086 (addnsub3_round_register == "CLOCK3")? clock3: 0;
13088 assign addnsub3_round_pipe_wire_clk = (addnsub3_round_pipeline_register == "CLOCK0")? clock0:
13089 (addnsub3_round_pipeline_register == "UNREGISTERED")? 0:
13090 (addnsub3_round_pipeline_register == "CLOCK1")? clock1:
13091 (addnsub3_round_pipeline_register == "CLOCK2")? clock2:
13092 (addnsub3_round_pipeline_register == "CLOCK3")? clock3: 0;
13094 assign mult01_round_wire_clk = (mult01_round_register == "CLOCK0")? clock0:
13095 (mult01_round_register == "UNREGISTERED")? 0:
13096 (mult01_round_register == "CLOCK1")? clock1:
13097 (mult01_round_register == "CLOCK2")? clock2:
13098 (mult01_round_register == "CLOCK3")? clock3: 0;
13101 assign mult01_saturate_wire_clk = (mult01_saturation_register == "CLOCK0")? clock0:
13102 (mult01_saturation_register == "UNREGISTERED")? 0:
13103 (mult01_saturation_register == "CLOCK1")? clock1:
13104 (mult01_saturation_register == "CLOCK2")? clock2:
13105 (mult01_saturation_register == "CLOCK3")? clock3: 0;
13108 assign mult23_round_wire_clk = (mult23_round_register == "CLOCK0")? clock0:
13109 (mult23_round_register == "UNREGISTERED")? 0:
13110 (mult23_round_register == "CLOCK1")? clock1:
13111 (mult23_round_register == "CLOCK2")? clock2:
13112 (mult23_round_register == "CLOCK3")? clock3: 0;
13114 assign mult23_saturate_wire_clk = (mult23_saturation_register == "CLOCK0")? clock0:
13115 (mult23_saturation_register == "UNREGISTERED")? 0:
13116 (mult23_saturation_register == "CLOCK1")? clock1:
13117 (mult23_saturation_register == "CLOCK2")? clock2:
13118 (mult23_saturation_register == "CLOCK3")? clock3: 0;
13122 // ----------------------------------------------------------------
13123 // This block updates the internal clock enable signals accordingly
13124 // every time the global clock enable signal changes state
13125 // ----------------------------------------------------------------
13128 assign input_reg_a0_wire_en = (input_register_a0 == "CLOCK0")? ena0:
13129 (input_register_a0 == "UNREGISTERED")? 1:
13130 (input_register_a0 == "CLOCK1")? ena1:
13131 (input_register_a0 == "CLOCK2")? ena2:
13132 (input_register_a0 == "CLOCK3")? ena3: 1;
13136 assign input_reg_a1_wire_en = (input_register_a1 == "CLOCK0")? ena0:
13137 (input_register_a1 == "UNREGISTERED")? 1:
13138 (input_register_a1 == "CLOCK1")? ena1:
13139 (input_register_a1 == "CLOCK2")? ena2:
13140 (input_register_a1 == "CLOCK3")? ena3: 1;
13143 assign input_reg_a2_wire_en = (input_register_a2 == "CLOCK0")? ena0:
13144 (input_register_a2 == "UNREGISTERED")? 1:
13145 (input_register_a2 == "CLOCK1")? ena1:
13146 (input_register_a2 == "CLOCK2")? ena2:
13147 (input_register_a2 == "CLOCK3")? ena3: 1;
13150 assign input_reg_a3_wire_en = (input_register_a3 == "CLOCK0")? ena0:
13151 (input_register_a3 == "UNREGISTERED")? 1:
13152 (input_register_a3 == "CLOCK1")? ena1:
13153 (input_register_a3 == "CLOCK2")? ena2:
13154 (input_register_a3 == "CLOCK3")? ena3: 1;
13157 assign input_reg_b0_wire_en = (input_register_b0 == "CLOCK0")? ena0:
13158 (input_register_b0 == "UNREGISTERED")? 1:
13159 (input_register_b0 == "CLOCK1")? ena1:
13160 (input_register_b0 == "CLOCK2")? ena2:
13161 (input_register_b0 == "CLOCK3")? ena3: 1;
13165 assign input_reg_b1_wire_en = (input_register_b1 == "CLOCK0")? ena0:
13166 (input_register_b1 == "UNREGISTERED")? 1:
13167 (input_register_b1 == "CLOCK1")? ena1:
13168 (input_register_b1 == "CLOCK2")? ena2:
13169 (input_register_b1 == "CLOCK3")? ena3: 1;
13172 assign input_reg_b2_wire_en = (input_register_b2 == "CLOCK0")? ena0:
13173 (input_register_b2 == "UNREGISTERED")? 1:
13174 (input_register_b2 == "CLOCK1")? ena1:
13175 (input_register_b2 == "CLOCK2")? ena2:
13176 (input_register_b2 == "CLOCK3")? ena3: 1;
13178 assign input_reg_b3_wire_en = (input_register_b3 == "CLOCK0")? ena0:
13179 (input_register_b3 == "UNREGISTERED")? 1:
13180 (input_register_b3 == "CLOCK1")? ena1:
13181 (input_register_b3 == "CLOCK2")? ena2:
13182 (input_register_b3 == "CLOCK3")? ena3: 1;
13185 assign addsub1_reg_wire_en = (addnsub_multiplier_register1 == "CLOCK0")? ena0:
13186 (addnsub_multiplier_register1 == "UNREGISTERED")? 1:
13187 (addnsub_multiplier_register1 == "CLOCK1")? ena1:
13188 (addnsub_multiplier_register1 == "CLOCK2")? ena2:
13189 (addnsub_multiplier_register1 == "CLOCK3")? ena3: 1;
13193 assign addsub1_pipe_wire_en = (addnsub_multiplier_pipeline_register1 == "CLOCK0")? ena0:
13194 (addnsub_multiplier_pipeline_register1 == "UNREGISTERED")? 1:
13195 (addnsub_multiplier_pipeline_register1 == "CLOCK1")? ena1:
13196 (addnsub_multiplier_pipeline_register1 == "CLOCK2")? ena2:
13197 (addnsub_multiplier_pipeline_register1 == "CLOCK3")? ena3: 1;
13200 assign addsub3_reg_wire_en = (addnsub_multiplier_register3 == "CLOCK0")? ena0:
13201 (addnsub_multiplier_register3 == "UNREGISTERED")? 1:
13202 (addnsub_multiplier_register3 == "CLOCK1")? ena1:
13203 (addnsub_multiplier_register3 == "CLOCK2")? ena2:
13204 (addnsub_multiplier_register3 == "CLOCK3")? ena3: 1;
13208 assign addsub3_pipe_wire_en = (addnsub_multiplier_pipeline_register3 == "CLOCK0")? ena0:
13209 (addnsub_multiplier_pipeline_register3 == "UNREGISTERED")? 1:
13210 (addnsub_multiplier_pipeline_register3 == "CLOCK1")? ena1:
13211 (addnsub_multiplier_pipeline_register3 == "CLOCK2")? ena2:
13212 (addnsub_multiplier_pipeline_register3 == "CLOCK3")? ena3: 1;
13216 assign sign_reg_a_wire_en = (signed_register_a == "CLOCK0")? ena0:
13217 (signed_register_a == "UNREGISTERED")? 1:
13218 (signed_register_a == "CLOCK1")? ena1:
13219 (signed_register_a == "CLOCK2")? ena2:
13220 (signed_register_a == "CLOCK3")? ena3: 1;
13224 assign sign_pipe_a_wire_en = (signed_pipeline_register_a == "CLOCK0")? ena0:
13225 (signed_pipeline_register_a == "UNREGISTERED")? 1:
13226 (signed_pipeline_register_a == "CLOCK1")? ena1:
13227 (signed_pipeline_register_a == "CLOCK2")? ena2:
13228 (signed_pipeline_register_a == "CLOCK3")? ena3: 1;
13232 assign sign_reg_b_wire_en = (signed_register_b == "CLOCK0")? ena0:
13233 (signed_register_b == "UNREGISTERED")? 1:
13234 (signed_register_b == "CLOCK1")? ena1:
13235 (signed_register_b == "CLOCK2")? ena2:
13236 (signed_register_b == "CLOCK3")? ena3: 1;
13240 assign sign_pipe_b_wire_en = (signed_pipeline_register_b == "CLOCK0")? ena0:
13241 (signed_pipeline_register_b == "UNREGISTERED")? 1:
13242 (signed_pipeline_register_b == "CLOCK1")? ena1:
13243 (signed_pipeline_register_b == "CLOCK2")? ena2:
13244 (signed_pipeline_register_b == "CLOCK3")? ena3: 1;
13248 assign multiplier_reg0_wire_en = (multiplier_register0 == "CLOCK0")? ena0:
13249 (multiplier_register0 == "UNREGISTERED")? 1:
13250 (multiplier_register0 == "CLOCK1")? ena1:
13251 (multiplier_register0 == "CLOCK2")? ena2:
13252 (multiplier_register0 == "CLOCK3")? ena3: 1;
13256 assign multiplier_reg1_wire_en = (multiplier_register1 == "CLOCK0")? ena0:
13257 (multiplier_register1 == "UNREGISTERED")? 1:
13258 (multiplier_register1 == "CLOCK1")? ena1:
13259 (multiplier_register1 == "CLOCK2")? ena2:
13260 (multiplier_register1 == "CLOCK3")? ena3: 1;
13263 assign multiplier_reg2_wire_en = (multiplier_register2 == "CLOCK0")? ena0:
13264 (multiplier_register2 == "UNREGISTERED")? 1:
13265 (multiplier_register2 == "CLOCK1")? ena1:
13266 (multiplier_register2 == "CLOCK2")? ena2:
13267 (multiplier_register2 == "CLOCK3")? ena3: 1;
13271 assign multiplier_reg3_wire_en = (multiplier_register3 == "CLOCK0")? ena0:
13272 (multiplier_register3 == "UNREGISTERED")? 1:
13273 (multiplier_register3 == "CLOCK1")? ena1:
13274 (multiplier_register3 == "CLOCK2")? ena2:
13275 (multiplier_register3 == "CLOCK3")? ena3: 1;
13279 assign output_reg_wire_en = (output_register == "CLOCK0")? ena0:
13280 (output_register == "UNREGISTERED")? 1:
13281 (output_register == "CLOCK1")? ena1:
13282 (output_register == "CLOCK2")? ena2:
13283 (output_register == "CLOCK3")? ena3: 1;
13286 assign addnsub1_round_wire_en = (addnsub1_round_register == "CLOCK0")? ena0:
13287 (addnsub1_round_register == "UNREGISTERED")? 1:
13288 (addnsub1_round_register == "CLOCK1")? ena1:
13289 (addnsub1_round_register == "CLOCK2")? ena2:
13290 (addnsub1_round_register == "CLOCK3")? ena3: 1;
13293 assign addnsub1_round_pipe_wire_en = (addnsub1_round_pipeline_register == "CLOCK0")? ena0:
13294 (addnsub1_round_pipeline_register == "UNREGISTERED")? 1:
13295 (addnsub1_round_pipeline_register == "CLOCK1")? ena1:
13296 (addnsub1_round_pipeline_register == "CLOCK2")? ena2:
13297 (addnsub1_round_pipeline_register == "CLOCK3")? ena3: 1;
13300 assign addnsub3_round_wire_en = (addnsub3_round_register == "CLOCK0")? ena0:
13301 (addnsub3_round_register == "UNREGISTERED")? 1:
13302 (addnsub3_round_register == "CLOCK1")? ena1:
13303 (addnsub3_round_register == "CLOCK2")? ena2:
13304 (addnsub3_round_register == "CLOCK3")? ena3: 1;
13307 assign addnsub3_round_pipe_wire_en = (addnsub3_round_pipeline_register == "CLOCK0")? ena0:
13308 (addnsub3_round_pipeline_register == "UNREGISTERED")? 1:
13309 (addnsub3_round_pipeline_register == "CLOCK1")? ena1:
13310 (addnsub3_round_pipeline_register == "CLOCK2")? ena2:
13311 (addnsub3_round_pipeline_register == "CLOCK3")? ena3: 1;
13314 assign mult01_round_wire_en = (mult01_round_register == "CLOCK0")? ena0:
13315 (mult01_round_register == "UNREGISTERED")? 1:
13316 (mult01_round_register == "CLOCK1")? ena1:
13317 (mult01_round_register == "CLOCK2")? ena2:
13318 (mult01_round_register == "CLOCK3")? ena3: 1;
13321 assign mult01_saturate_wire_en = (mult01_saturation_register == "CLOCK0")? ena0:
13322 (mult01_saturation_register == "UNREGISTERED")? 1:
13323 (mult01_saturation_register == "CLOCK1")? ena1:
13324 (mult01_saturation_register == "CLOCK2")? ena2:
13325 (mult01_saturation_register == "CLOCK3")? ena3: 1;
13328 assign mult23_round_wire_en = (mult23_round_register == "CLOCK0")? ena0:
13329 (mult23_round_register == "UNREGISTERED")? 1:
13330 (mult23_round_register == "CLOCK1")? ena1:
13331 (mult23_round_register == "CLOCK2")? ena2:
13332 (mult23_round_register == "CLOCK3")? ena3: 1;
13335 assign mult23_saturate_wire_en = (mult23_saturation_register == "CLOCK0")? ena0:
13336 (mult23_saturation_register == "UNREGISTERED")? 1:
13337 (mult23_saturation_register == "CLOCK1")? ena1:
13338 (mult23_saturation_register == "CLOCK2")? ena2:
13339 (mult23_saturation_register == "CLOCK3")? ena3: 1;
13342 // ---------------------------------------------------------
13343 // This block updates the internal clear signals accordingly
13344 // every time the global clear signal changes state
13345 // ---------------------------------------------------------
13347 assign input_reg_a0_wire_clr = (input_aclr_a0 == "ACLR3")? aclr3:
13348 (input_aclr_a0 == "UNREGISTERED")? 0:
13349 (input_aclr_a0 == "ACLR0")? aclr0:
13350 (input_aclr_a0 == "ACLR1")? aclr1:
13351 (input_aclr_a0 == "ACLR2")? aclr2: 0;
13355 assign input_reg_a1_wire_clr = (input_aclr_a1 == "ACLR3")? aclr3:
13356 (input_aclr_a1 == "UNREGISTERED")? 0:
13357 (input_aclr_a1 == "ACLR0")? aclr0:
13358 (input_aclr_a1 == "ACLR1")? aclr1:
13359 (input_aclr_a1 == "ACLR2")? aclr2: 0;
13362 assign input_reg_a2_wire_clr = (input_aclr_a2 == "ACLR3")? aclr3:
13363 (input_aclr_a2 == "UNREGISTERED")? 0:
13364 (input_aclr_a2 == "ACLR0")? aclr0:
13365 (input_aclr_a2 == "ACLR1")? aclr1:
13366 (input_aclr_a2 == "ACLR2")? aclr2: 0;
13370 assign input_reg_a3_wire_clr = (input_aclr_a3 == "ACLR3")? aclr3:
13371 (input_aclr_a3 == "UNREGISTERED")? 0:
13372 (input_aclr_a3 == "ACLR0")? aclr0:
13373 (input_aclr_a3 == "ACLR1")? aclr1:
13374 (input_aclr_a3 == "ACLR2")? aclr2: 0;
13377 assign input_reg_b0_wire_clr = (input_aclr_b0 == "ACLR3")? aclr3:
13378 (input_aclr_b0 == "UNREGISTERED")? 0:
13379 (input_aclr_b0 == "ACLR0")? aclr0:
13380 (input_aclr_b0 == "ACLR1")? aclr1:
13381 (input_aclr_b0 == "ACLR2")? aclr2: 0;
13384 assign input_reg_b1_wire_clr = (input_aclr_b1 == "ACLR3")? aclr3:
13385 (input_aclr_b1 == "UNREGISTERED")? 0:
13386 (input_aclr_b1 == "ACLR0")? aclr0:
13387 (input_aclr_b1 == "ACLR1")? aclr1:
13388 (input_aclr_b1 == "ACLR2")? aclr2: 0;
13391 assign input_reg_b2_wire_clr = (input_aclr_b2 == "ACLR3")? aclr3:
13392 (input_aclr_b2 == "UNREGISTERED")? 0:
13393 (input_aclr_b2 == "ACLR0")? aclr0:
13394 (input_aclr_b2 == "ACLR1")? aclr1:
13395 (input_aclr_b2 == "ACLR2")? aclr2: 0;
13399 assign input_reg_b3_wire_clr = (input_aclr_b3 == "ACLR3")? aclr3:
13400 (input_aclr_b3 == "UNREGISTERED")? 0:
13401 (input_aclr_b3 == "ACLR0")? aclr0:
13402 (input_aclr_b3 == "ACLR1")? aclr1:
13403 (input_aclr_b3 == "ACLR2")? aclr2: 0;
13408 assign addsub1_reg_wire_clr = (addnsub_multiplier_aclr1 == "ACLR3")? aclr3:
13409 (addnsub_multiplier_aclr1 == "UNREGISTERED")? 0:
13410 (addnsub_multiplier_aclr1 == "ACLR0")? aclr0:
13411 (addnsub_multiplier_aclr1 == "ACLR1")? aclr1:
13412 (addnsub_multiplier_aclr1 == "ACLR2")? aclr2: 0;
13416 assign addsub1_pipe_wire_clr = (addnsub_multiplier_pipeline_aclr1 == "ACLR3")? aclr3:
13417 (addnsub_multiplier_pipeline_aclr1 == "UNREGISTERED")? 0:
13418 (addnsub_multiplier_pipeline_aclr1 == "ACLR0")? aclr0:
13419 (addnsub_multiplier_pipeline_aclr1 == "ACLR1")? aclr1:
13420 (addnsub_multiplier_pipeline_aclr1 == "ACLR2")? aclr2: 0;
13425 assign addsub3_reg_wire_clr = (addnsub_multiplier_aclr3 == "ACLR3")? aclr3:
13426 (addnsub_multiplier_aclr3 == "UNREGISTERED")? 0:
13427 (addnsub_multiplier_aclr3 == "ACLR0")? aclr0:
13428 (addnsub_multiplier_aclr3 == "ACLR1")? aclr1:
13429 (addnsub_multiplier_aclr3 == "ACLR2")? aclr2: 0;
13433 assign addsub3_pipe_wire_clr = (addnsub_multiplier_pipeline_aclr3 == "ACLR3")? aclr3:
13434 (addnsub_multiplier_pipeline_aclr3 == "UNREGISTERED")? 0:
13435 (addnsub_multiplier_pipeline_aclr3 == "ACLR0")? aclr0:
13436 (addnsub_multiplier_pipeline_aclr3 == "ACLR1")? aclr1:
13437 (addnsub_multiplier_pipeline_aclr3 == "ACLR2")? aclr2: 0;
13442 assign sign_reg_a_wire_clr = (signed_aclr_a == "ACLR3")? aclr3:
13443 (signed_aclr_a == "UNREGISTERED")? 0:
13444 (signed_aclr_a == "ACLR0")? aclr0:
13445 (signed_aclr_a == "ACLR1")? aclr1:
13446 (signed_aclr_a == "ACLR2")? aclr2: 0;
13450 assign sign_pipe_a_wire_clr = (signed_pipeline_aclr_a == "ACLR3")? aclr3:
13451 (signed_pipeline_aclr_a == "UNREGISTERED")? 0:
13452 (signed_pipeline_aclr_a == "ACLR0")? aclr0:
13453 (signed_pipeline_aclr_a == "ACLR1")? aclr1:
13454 (signed_pipeline_aclr_a == "ACLR2")? aclr2: 0;
13458 assign sign_reg_b_wire_clr = (signed_aclr_b == "ACLR3")? aclr3:
13459 (signed_aclr_b == "UNREGISTERED")? 0:
13460 (signed_aclr_b == "ACLR0")? aclr0:
13461 (signed_aclr_b == "ACLR1")? aclr1:
13462 (signed_aclr_b == "ACLR2")? aclr2: 0;
13466 assign sign_pipe_b_wire_clr = (signed_pipeline_aclr_b == "ACLR3")? aclr3:
13467 (signed_pipeline_aclr_b == "UNREGISTERED")? 0:
13468 (signed_pipeline_aclr_b == "ACLR0")? aclr0:
13469 (signed_pipeline_aclr_b == "ACLR1")? aclr1:
13470 (signed_pipeline_aclr_b == "ACLR2")? aclr2: 0;
13475 assign multiplier_reg0_wire_clr = (multiplier_aclr0 == "ACLR3")? aclr3:
13476 (multiplier_aclr0 == "UNREGISTERED")? 0:
13477 (multiplier_aclr0 == "ACLR0")? aclr0:
13478 (multiplier_aclr0 == "ACLR1")? aclr1:
13479 (multiplier_aclr0 == "ACLR2")? aclr2: 0;
13483 assign multiplier_reg1_wire_clr = (multiplier_aclr1 == "ACLR3")? aclr3:
13484 (multiplier_aclr1 == "UNREGISTERED")? 0:
13485 (multiplier_aclr1 == "ACLR0")? aclr0:
13486 (multiplier_aclr1 == "ACLR1")? aclr1:
13487 (multiplier_aclr1 == "ACLR2")? aclr2: 0;
13491 assign multiplier_reg2_wire_clr = (multiplier_aclr2 == "ACLR3")? aclr3:
13492 (multiplier_aclr2 == "UNREGISTERED")? 0:
13493 (multiplier_aclr2 == "ACLR0")? aclr0:
13494 (multiplier_aclr2 == "ACLR1")? aclr1:
13495 (multiplier_aclr2 == "ACLR2")? aclr2: 0;
13500 assign multiplier_reg3_wire_clr = (multiplier_aclr3 == "ACLR3")? aclr3:
13501 (multiplier_aclr3 == "UNREGISTERED")? 0:
13502 (multiplier_aclr3 == "ACLR0")? aclr0:
13503 (multiplier_aclr3 == "ACLR1")? aclr1:
13504 (multiplier_aclr3 == "ACLR2")? aclr2: 0;
13509 assign output_reg_wire_clr = (output_aclr == "ACLR3")? aclr3:
13510 (output_aclr == "UNREGISTERED")? 0:
13511 (output_aclr == "ACLR0")? aclr0:
13512 (output_aclr == "ACLR1")? aclr1:
13513 (output_aclr == "ACLR2")? aclr2: 0;
13517 assign addnsub1_round_wire_clr = (addnsub1_round_aclr == "ACLR3")? aclr3:
13518 (addnsub1_round_register == "UNREGISTERED")? 0:
13519 (addnsub1_round_aclr == "ACLR0")? aclr0:
13520 (addnsub1_round_aclr == "ACLR1")? aclr1:
13521 (addnsub1_round_aclr == "ACLR2")? aclr2: 0;
13525 assign addnsub1_round_pipe_wire_clr = (addnsub1_round_pipeline_aclr == "ACLR3")? aclr3:
13526 (addnsub1_round_pipeline_register == "UNREGISTERED")? 0:
13527 (addnsub1_round_pipeline_aclr == "ACLR0")? aclr0:
13528 (addnsub1_round_pipeline_aclr == "ACLR1")? aclr1:
13529 (addnsub1_round_pipeline_aclr == "ACLR2")? aclr2: 0;
13533 assign addnsub3_round_wire_clr = (addnsub3_round_aclr == "ACLR3")? aclr3:
13534 (addnsub3_round_register == "UNREGISTERED")? 0:
13535 (addnsub3_round_aclr == "ACLR0")? aclr0:
13536 (addnsub3_round_aclr == "ACLR1")? aclr1:
13537 (addnsub3_round_aclr == "ACLR2")? aclr2: 0;
13541 assign addnsub3_round_pipe_wire_clr = (addnsub3_round_pipeline_aclr == "ACLR3")? aclr3:
13542 (addnsub3_round_pipeline_register == "UNREGISTERED")? 0:
13543 (addnsub3_round_pipeline_aclr == "ACLR0")? aclr0:
13544 (addnsub3_round_pipeline_aclr == "ACLR1")? aclr1:
13545 (addnsub3_round_pipeline_aclr == "ACLR2")? aclr2: 0;
13549 assign mult01_round_wire_clr = (mult01_round_aclr == "ACLR3")? aclr3:
13550 (mult01_round_register == "UNREGISTERED")? 0:
13551 (mult01_round_aclr == "ACLR0")? aclr0:
13552 (mult01_round_aclr == "ACLR1")? aclr1:
13553 (mult01_round_aclr == "ACLR2")? aclr2: 0;
13557 assign mult01_saturate_wire_clr = (mult01_saturation_aclr == "ACLR3")? aclr3:
13558 (mult01_saturation_register == "UNREGISTERED")? 0:
13559 (mult01_saturation_aclr == "ACLR0")? aclr0:
13560 (mult01_saturation_aclr == "ACLR1")? aclr1:
13561 (mult01_saturation_aclr == "ACLR2")? aclr2: 0;
13565 assign mult23_round_wire_clr = (mult23_round_aclr == "ACLR3")? aclr3:
13566 (mult23_round_register == "UNREGISTERED")? 0:
13567 (mult23_round_aclr == "ACLR0")? aclr0:
13568 (mult23_round_aclr == "ACLR1")? aclr1:
13569 (mult23_round_aclr == "ACLR2")? aclr2: 0;
13573 assign mult23_saturate_wire_clr = (mult23_saturation_aclr == "ACLR3")? aclr3:
13574 (mult23_saturation_register == "UNREGISTERED")? 0:
13575 (mult23_saturation_aclr == "ACLR0")? aclr0:
13576 (mult23_saturation_aclr == "ACLR1")? aclr1:
13577 (mult23_saturation_aclr == "ACLR2")? aclr2: 0;
13581 // -------------------------------------------------------------------------------------
13582 // This block contains 1 register and 1 combinatorial block (to set mult_a[int_width_a-1:0])
13583 // Signal Registered : mult_a_pre[int_width_a-1:0]
13585 // Register is controlled by posedge input_reg_a0_wire_clk
13586 // Register has a clock enable input_reg_a0_wire_en
13587 // Register has an asynchronous clear signal, input_reg_a0_wire_clr
13588 // NOTE : The combinatorial block will be executed if
13589 // input_register_a0 is unregistered and mult_a_pre[int_width_a-1:0] changes value
13590 // -------------------------------------------------------------------------------------
13591 assign mult_a_wire[int_width_a-1:0] = (input_register_a0 == "UNREGISTERED")?
13592 mult_a_pre[int_width_a-1:0]: mult_a_reg[int_width_a-1:0];
13593 always @(posedge input_reg_a0_wire_clk or posedge input_reg_a0_wire_clr)
13595 if (input_reg_a0_wire_clr == 1)
13596 mult_a_reg[int_width_a-1:0] <= 0;
13597 else if ((input_reg_a0_wire_clk === 1'b1) && (input_reg_a0_wire_en == 1))
13598 mult_a_reg[int_width_a-1:0] <= mult_a_pre[int_width_a-1:0];
13602 // -----------------------------------------------------------------------------------------------
13603 // This block contains 1 register and 1 combinatorial block (to set mult_a[(2*int_width_a)-1:int_width_a])
13604 // Signal Registered : mult_a_pre[(2*int_width_a)-1:int_width_a]
13606 // Register is controlled by posedge input_reg_a1_wire_clk
13607 // Register has a clock enable input_reg_a1_wire_en
13608 // Register has an asynchronous clear signal, input_reg_a1_wire_clr
13609 // NOTE : The combinatorial block will be executed if
13610 // input_register_a1 is unregistered and mult_a_pre[(2*int_width_a)-1:int_width_a] changes value
13611 // -----------------------------------------------------------------------------------------------
13613 assign mult_a_wire[(2*int_width_a)-1:int_width_a] = (input_register_a1 == "UNREGISTERED")?
13614 mult_a_pre[(2*int_width_a)-1:int_width_a]: mult_a_reg[(2*int_width_a)-1:int_width_a];
13616 always @(posedge input_reg_a1_wire_clk or posedge input_reg_a1_wire_clr)
13619 if (input_reg_a1_wire_clr == 1)
13620 mult_a_reg[(2*int_width_a)-1:int_width_a] <= 0;
13621 else if ((input_reg_a1_wire_clk == 1) && (input_reg_a1_wire_en == 1))
13622 mult_a_reg[(2*int_width_a)-1:int_width_a] <= mult_a_pre[(2*int_width_a)-1:int_width_a];
13626 // -------------------------------------------------------------------------------------------------
13627 // This block contains 1 register and 1 combinatorial block (to set mult_a[(3*int_width_a)-1:2*int_width_a])
13628 // Signal Registered : mult_a_pre[(3*int_width_a)-1:2*int_width_a]
13630 // Register is controlled by posedge input_reg_a2_wire_clk
13631 // Register has a clock enable input_reg_a2_wire_en
13632 // Register has an asynchronous clear signal, input_reg_a2_wire_clr
13633 // NOTE : The combinatorial block will be executed if
13634 // input_register_a2 is unregistered and mult_a_pre[(3*int_width_a)-1:2*int_width_a] changes value
13635 // -------------------------------------------------------------------------------------------------
13636 assign mult_a_wire[(3*int_width_a)-1 : 2*int_width_a ] = (input_register_a2 == "UNREGISTERED")?
13637 mult_a_pre[(3*int_width_a)-1 : 2*int_width_a]: mult_a_reg[(3*int_width_a)-1 : 2*int_width_a ];
13640 always @(posedge input_reg_a2_wire_clk or posedge input_reg_a2_wire_clr)
13642 if (input_reg_a2_wire_clr == 1)
13643 mult_a_reg[(3*int_width_a)-1 : 2*int_width_a ] <= 0;
13644 else if ((input_reg_a2_wire_clk == 1) && (input_reg_a2_wire_en == 1))
13645 mult_a_reg[(3*int_width_a)-1 : 2*int_width_a ] <= mult_a_pre[(3*int_width_a)-1 : 2*int_width_a];
13649 // -------------------------------------------------------------------------------------------------
13650 // This block contains 1 register and 1 combinatorial block (to set mult_a[(4*int_width_a)-1:3*int_width_a])
13651 // Signal Registered : mult_a_pre[(4*int_width_a)-1:3*int_width_a]
13653 // Register is controlled by posedge input_reg_a3_wire_clk
13654 // Register has a clock enable input_reg_a3_wire_en
13655 // Register has an asynchronous clear signal, input_reg_a3_wire_clr
13656 // NOTE : The combinatorial block will be executed if
13657 // input_register_a3 is unregistered and mult_a_pre[(4*int_width_a)-1:3*int_width_a] changes value
13658 // -------------------------------------------------------------------------------------------------
13659 assign mult_a_wire[(4*int_width_a)-1 : 3*int_width_a ] = (input_register_a3 == "UNREGISTERED")?
13660 mult_a_pre[(4*int_width_a)-1:3*int_width_a]: mult_a_reg[(4*int_width_a)-1:3*int_width_a];
13662 always @(posedge input_reg_a3_wire_clk or posedge input_reg_a3_wire_clr)
13664 if (input_reg_a3_wire_clr == 1)
13665 mult_a_reg[(4*int_width_a)-1 : 3*int_width_a ] <= 0;
13666 else if ((input_reg_a3_wire_clk == 1) && (input_reg_a3_wire_en == 1))
13667 mult_a_reg[(4*int_width_a)-1 : 3*int_width_a ] <= mult_a_pre[(4*int_width_a)-1:3*int_width_a];
13672 // -------------------------------------------------------------------------------------
13673 // This block contains 1 register and 1 combinatorial block (to set mult_b[int_width_b-1:0])
13674 // Signal Registered : mult_b_pre[int_width_b-1:0]
13676 // Register is controlled by posedge input_reg_b0_wire_clk
13677 // Register has a clock enable input_reg_b0_wire_en
13678 // Register has an asynchronous clear signal, input_reg_b0_wire_clr
13679 // NOTE : The combinatorial block will be executed if
13680 // input_register_b0 is unregistered and mult_b_pre[int_width_b-1:0] changes value
13681 // -------------------------------------------------------------------------------------
13683 assign mult_b_wire[int_width_b-1:0] = (input_register_b0 == "UNREGISTERED")?
13684 mult_b_pre[int_width_b-1:0]: mult_b_reg[int_width_b-1:0];
13686 always @(posedge input_reg_b0_wire_clk or posedge input_reg_b0_wire_clr)
13688 if (input_reg_b0_wire_clr == 1)
13689 mult_b_reg[int_width_b-1:0] <= 0;
13690 else if ((input_reg_b0_wire_clk == 1) && (input_reg_b0_wire_en == 1))
13691 mult_b_reg[int_width_b-1:0] <= mult_b_pre[int_width_b-1:0];
13695 // -----------------------------------------------------------------------------------------------
13696 // This block contains 1 register and 1 combinatorial block (to set mult_b[(2*int_width_b)-1:int_width_b])
13697 // Signal Registered : mult_b_pre[(2*int_width_b)-1:int_width_b]
13699 // Register is controlled by posedge input_reg_a1_wire_clk
13700 // Register has a clock enable input_reg_b1_wire_en
13701 // Register has an asynchronous clear signal, input_reg_b1_wire_clr
13702 // NOTE : The combinatorial block will be executed if
13703 // input_register_b1 is unregistered and mult_b_pre[(2*int_width_b)-1:int_width_b] changes value
13704 // -----------------------------------------------------------------------------------------------
13705 assign mult_b_wire[(2*int_width_b)-1:int_width_b] = (input_register_b1 == "UNREGISTERED")?
13706 mult_b_pre[(2*int_width_b)-1:int_width_b]: mult_b_reg[(2*int_width_b)-1:int_width_b];
13710 always @(posedge input_reg_b1_wire_clk or posedge input_reg_b1_wire_clr)
13712 if (input_reg_b1_wire_clr == 1)
13713 mult_b_reg[(2*int_width_b)-1:int_width_b] <= 0;
13714 else if ((input_reg_b1_wire_clk == 1) && (input_reg_b1_wire_en == 1))
13715 mult_b_reg[(2*int_width_b)-1:int_width_b] <= mult_b_pre[(2*int_width_b)-1:int_width_b];
13720 // -------------------------------------------------------------------------------------------------
13721 // This block contains 1 register and 1 combinatorial block (to set mult_b[(3*int_width_b)-1:2*int_width_b])
13722 // Signal Registered : mult_b_pre[(3*int_width_b)-1:2*int_width_b]
13724 // Register is controlled by posedge input_reg_b2_wire_clk
13725 // Register has a clock enable input_reg_b2_wire_en
13726 // Register has an asynchronous clear signal, input_reg_b2_wire_clr
13727 // NOTE : The combinatorial block will be executed if
13728 // input_register_b2 is unregistered and mult_b_pre[(3*int_width_b)-1:2*int_width_b] changes value
13729 // -------------------------------------------------------------------------------------------------
13730 assign mult_b_wire[(3*int_width_b)-1:2*int_width_b] = (input_register_b2 == "UNREGISTERED")?
13731 mult_b_pre[(3*int_width_b)-1:2*int_width_b]: mult_b_reg[(3*int_width_b)-1:2*int_width_b];
13734 always @(posedge input_reg_b2_wire_clk or posedge input_reg_b2_wire_clr)
13736 if (input_reg_b2_wire_clr == 1)
13737 mult_b_reg[(3*int_width_b)-1:2*int_width_b] <= 0;
13738 else if ((input_reg_b2_wire_clk == 1) && (input_reg_b2_wire_en == 1))
13739 mult_b_reg[(3*int_width_b)-1:2*int_width_b] <= mult_b_pre[(3*int_width_b)-1:2*int_width_b];
13744 // -------------------------------------------------------------------------------------------------
13745 // This block contains 1 register and 1 combinatorial block (to set mult_b[(4*int_width_b)-1:3*int_width_b])
13746 // Signal Registered : mult_b_pre[(4*int_width_b)-1:3*int_width_b]
13748 // Register is controlled by posedge input_reg_b3_wire_clk
13749 // Register has a clock enable input_reg_b3_wire_en
13750 // Register has an asynchronous clear signal, input_reg_b3_wire_clr
13751 // NOTE : The combinatorial block will be executed if
13752 // input_register_b3 is unregistered and mult_b_pre[(4*int_width_b)-1:3*int_width_b] changes value
13753 // -------------------------------------------------------------------------------------------------
13754 assign mult_b_wire[(4*int_width_b)-1:3*int_width_b] = (input_register_b3 == "UNREGISTERED")?
13755 mult_b_pre[(4*int_width_b)-1:3*int_width_b]: mult_b_reg[(4*int_width_b)-1:3*int_width_b];
13758 always @(posedge input_reg_b3_wire_clk or posedge input_reg_b3_wire_clr)
13760 if (input_reg_b3_wire_clr == 1)
13761 mult_b_reg[(4*int_width_b)-1 : 3*int_width_b ] <= 0;
13762 else if ((input_reg_b3_wire_clk == 1) && (input_reg_b3_wire_en == 1))
13763 mult_b_reg[(4*int_width_b)-1:3*int_width_b] <= mult_b_pre[(4*int_width_b)-1:3*int_width_b];
13767 // -------------------------------------------------------------------------------------------------
13768 // This block contains 1 register and 1 combinatorial block (to set mult01_round_wire)
13769 // Signal Registered : mult01_round_pre
13771 // Register is controlled by posedge mult01_round_wire_clk
13772 // Register has a clock enable mult01_round_wire_en
13773 // Register has an asynchronous clear signal, mult01_round_wire_clr
13774 // NOTE : The combinatorial block will be executed if
13775 // mult01_round_register is unregistered and mult01_round changes value
13776 // -------------------------------------------------------------------------------------------------
13777 assign mult01_round_wire = (mult01_round_register == "UNREGISTERED")?
13778 mult01_round_pre : mult01_round_reg;
13780 always @(posedge mult01_round_wire_clk or posedge mult01_round_wire_clr)
13782 if (mult01_round_wire_clr == 1)
13783 mult01_round_reg <= 0;
13784 else if ((mult01_round_wire_clk == 1) && (mult01_round_wire_en == 1))
13785 mult01_round_reg <= mult01_round_pre;
13789 // -------------------------------------------------------------------------------------------------
13790 // This block contains 1 register and 1 combinatorial block (to set mult01_saturate_wire)
13791 // Signal Registered : mult01_saturation_pre
13793 // Register is controlled by posedge mult01_saturate_wire_clk
13794 // Register has a clock enable mult01_saturate_wire_en
13795 // Register has an asynchronous clear signal, mult01_saturate_wire_clr
13796 // NOTE : The combinatorial block will be executed if
13797 // mult01_saturation_register is unregistered and mult01_saturate_pre changes value
13798 // -------------------------------------------------------------------------------------------------
13799 assign mult01_saturate_wire = (mult01_saturation_register == "UNREGISTERED")?
13800 mult01_saturate_pre : mult01_saturate_reg;
13802 always @(posedge mult01_saturate_wire_clk or posedge mult01_saturate_wire_clr)
13804 if (mult01_saturate_wire_clr == 1)
13805 mult01_saturate_reg <= 0;
13806 else if ((mult01_saturate_wire_clk == 1) && (mult01_saturate_wire_en == 1))
13807 mult01_saturate_reg <= mult01_saturate_pre;
13811 // -------------------------------------------------------------------------------------------------
13812 // This block contains 1 register and 1 combinatorial block (to set mult23_round_wire)
13813 // Signal Registered : mult23_round_pre
13815 // Register is controlled by posedge mult23_round_wire_clk
13816 // Register has a clock enable mult23_round_wire_en
13817 // Register has an asynchronous clear signal, mult23_round_wire_clr
13818 // NOTE : The combinatorial block will be executed if
13819 // mult23_round_register is unregistered and mult23_round_pre changes value
13820 // -------------------------------------------------------------------------------------------------
13821 assign mult23_round_wire = (mult23_round_register == "UNREGISTERED")?
13822 mult23_round_pre : mult23_round_reg;
13824 always @(posedge mult23_round_wire_clk or posedge mult23_round_wire_clr)
13826 if (mult23_round_wire_clr == 1)
13827 mult23_round_reg <= 0;
13828 else if ((mult23_round_wire_clk == 1) && (mult23_round_wire_en == 1))
13829 mult23_round_reg <= mult23_round_pre;
13833 // -------------------------------------------------------------------------------------------------
13834 // This block contains 1 register and 1 combinatorial block (to set mult23_saturate_wire)
13835 // Signal Registered : mult23_round_pre
13837 // Register is controlled by posedge mult23_saturate_wire_clk
13838 // Register has a clock enable mult23_saturate_wire_en
13839 // Register has an asynchronous clear signal, mult23_saturate_wire_clr
13840 // NOTE : The combinatorial block will be executed if
13841 // mult23_saturation_register is unregistered and mult23_saturation_pre changes value
13842 // -------------------------------------------------------------------------------------------------
13843 assign mult23_saturate_wire = (mult23_saturation_register == "UNREGISTERED")?
13844 mult23_saturate_pre : mult23_saturate_reg;
13846 always @(posedge mult23_saturate_wire_clk or posedge mult23_saturate_wire_clr)
13848 if (mult23_saturate_wire_clr == 1)
13849 mult23_saturate_reg <= 0;
13850 else if ((mult23_saturate_wire_clk == 1) && (mult23_saturate_wire_en == 1))
13851 mult23_saturate_reg <= mult23_saturate_pre;
13855 // ---------------------------------------------------------------------------------
13856 // This block contains 1 register and 1 combinatorial block (to set addnsub1_round_wire)
13857 // Signal Registered : addnsub1_round_pre
13859 // Register is controlled by posedge addnsub1_round_wire_clk
13860 // Register has a clock enable addnsub1_round_wire_en
13861 // Register has an asynchronous clear signal, addnsub1_round_wire_clr
13862 // NOTE : The combinatorial block will be executed if
13863 // addnsub1_round_register is unregistered and addnsub1_round_pre changes value
13864 // ---------------------------------------------------------------------------------
13865 assign addnsub1_round_wire = (addnsub1_round_register=="UNREGISTERED")?
13866 addnsub1_round_pre : addnsub1_round_reg;
13868 always @(posedge addnsub1_round_wire_clk or posedge addnsub1_round_wire_clr)
13870 if (addnsub1_round_wire_clr == 1)
13871 addnsub1_round_reg <= 0;
13872 else if ((addnsub1_round_wire_clk == 1) && (addnsub1_round_wire_en == 1))
13873 addnsub1_round_reg <= addnsub1_round_pre;
13876 // ---------------------------------------------------------------------------------
13877 // This block contains 1 register and 1 combinatorial block (to set addnsub1_round_pipe_wire)
13878 // Signal Registered : addnsub1_round_wire
13880 // Register is controlled by posedge addnsub1_round_pipe_wire_clk
13881 // Register has a clock enable addnsub1_round_pipe_wire_en
13882 // Register has an asynchronous clear signal, addnsub1_round_wire_clr
13883 // NOTE : The combinatorial block will be executed if
13884 // addnsub1_round_pipeline_register is unregistered and addnsub1_round_wire changes value
13885 // ---------------------------------------------------------------------------------
13886 assign addnsub1_round_pipe_wire = (addnsub1_round_pipeline_register=="UNREGISTERED")?
13887 addnsub1_round_wire : addnsub1_round_pipe_reg;
13889 always @(posedge addnsub1_round_pipe_wire_clk or posedge addnsub1_round_pipe_wire_clr)
13891 if (addnsub1_round_pipe_wire_clr == 1)
13892 addnsub1_round_pipe_reg <= 0;
13893 else if ((addnsub1_round_pipe_wire_clk == 1) && (addnsub1_round_pipe_wire_en == 1))
13894 addnsub1_round_pipe_reg <= addnsub1_round_wire;
13897 // ---------------------------------------------------------------------------------
13898 // This block contains 1 register and 1 combinatorial block (to set addnsub3_round_wire)
13899 // Signal Registered : addnsub3_round_pre
13901 // Register is controlled by posedge addnsub3_round_wire_clk
13902 // Register has a clock enable addnsub3_round_wire_en
13903 // Register has an asynchronous clear signal, addnsub3_round_wire_clr
13904 // NOTE : The combinatorial block will be executed if
13905 // addnsub3_round_register is unregistered and addnsub3_round_pre changes value
13906 // ---------------------------------------------------------------------------------
13907 assign addnsub3_round_wire = (addnsub3_round_register=="UNREGISTERED")?
13908 addnsub3_round_pre : addnsub3_round_reg;
13910 always @(posedge addnsub3_round_wire_clk or posedge addnsub3_round_wire_clr)
13912 if (addnsub3_round_wire_clr == 1)
13913 addnsub3_round_reg <= 0;
13914 else if ((addnsub3_round_wire_clk == 1) && (addnsub3_round_wire_en == 1))
13915 addnsub3_round_reg <= addnsub3_round_pre;
13918 // ---------------------------------------------------------------------------------
13919 // This block contains 1 register and 1 combinatorial block (to set addnsub3_round_pipe_wire)
13920 // Signal Registered : addnsub3_round_wire
13922 // Register is controlled by posedge addnsub3_round_pipe_wire_clk
13923 // Register has a clock enable addnsub3_round_pipe_wire_en
13924 // Register has an asynchronous clear signal, addnsub3_round_wire_clr
13925 // NOTE : The combinatorial block will be executed if
13926 // addnsub3_round_pipeline_register is unregistered and addnsub3_round_wire changes value
13927 // ---------------------------------------------------------------------------------
13928 assign addnsub3_round_pipe_wire = (addnsub3_round_pipeline_register=="UNREGISTERED")?
13929 addnsub3_round_wire : addnsub3_round_pipe_reg;
13931 always @(posedge addnsub3_round_pipe_wire_clk or posedge addnsub3_round_pipe_wire_clr)
13933 if (addnsub3_round_pipe_wire_clr == 1)
13934 addnsub3_round_pipe_reg <= 0;
13935 else if ((addnsub3_round_pipe_wire_clk == 1) && (addnsub3_round_pipe_wire_en == 1))
13936 addnsub3_round_pipe_reg <= addnsub3_round_wire;
13940 // ---------------------------------------------------------------------------------
13941 // This block contains 1 register and 1 combinatorial block (to set addsub1_reg)
13942 // Signal Registered : addsub1_int
13944 // Register is controlled by posedge addsub1_reg_wire_clk
13945 // Register has a clock enable addsub1_reg_wire_en
13946 // Register has an asynchronous clear signal, addsub1_reg_wire_clr
13947 // NOTE : The combinatorial block will be executed if
13948 // addnsub_multiplier_register1 is unregistered and addsub1_int changes value
13949 // ---------------------------------------------------------------------------------
13950 assign addsub1_wire = (addnsub_multiplier_register1=="UNREGISTERED")? addsub1_int : addsub1_reg;
13952 always @(posedge addsub1_reg_wire_clk or posedge addsub1_reg_wire_clr)
13954 if ((addsub1_reg_wire_clr == 1) && (multiplier1_direction == "UNUSED"))
13956 else if ((addsub1_reg_wire_clk == 1) && (addsub1_reg_wire_en == 1))
13957 addsub1_reg <= addsub1_int;
13961 // -------------------------------------------------------------------------------------------
13962 // This block contains 1 register and 1 combinatorial block (to set addsub1_pipe)
13963 // Signal Registered : addsub1_reg
13965 // Register is controlled by posedge addsub1_pipe_wire_clk
13966 // Register has a clock enable addsub1_pipe_wire_en
13967 // Register has an asynchronous clear signal, addsub1_pipe_wire_clr
13968 // NOTE : The combinatorial block will be executed if
13969 // addnsub_multiplier_pipeline_register1 is unregistered and addsub1_reg changes value
13970 // ------------------------------------------------------------------------------------------
13972 assign addsub1_pipe_wire = (addnsub_multiplier_pipeline_register1 == "UNREGISTERED")?
13973 addsub1_wire : addsub1_pipe_reg;
13974 always @(posedge addsub1_pipe_wire_clk or posedge addsub1_pipe_wire_clr)
13976 if ((addsub1_pipe_wire_clr == 1) && (multiplier1_direction == "UNUSED"))
13977 addsub1_pipe_reg <= 0;
13978 else if ((addsub1_pipe_wire_clk == 1) && (addsub1_pipe_wire_en == 1))
13979 addsub1_pipe_reg <= addsub1_wire;
13983 // ---------------------------------------------------------------------------------
13984 // This block contains 1 register and 1 combinatorial block (to set addsub3_reg)
13985 // Signal Registered : addsub3_int
13987 // Register is controlled by posedge addsub3_reg_wire_clk
13988 // Register has a clock enable addsub3_reg_wire_en
13989 // Register has an asynchronous clear signal, addsub3_reg_wire_clr
13990 // NOTE : The combinatorial block will be executed if
13991 // addnsub_multiplier_register3 is unregistered and addsub3_int changes value
13992 // ---------------------------------------------------------------------------------
13993 assign addsub3_wire = (addnsub_multiplier_register3=="UNREGISTERED")?
13994 addsub3_int : addsub3_reg;
13997 always @(posedge addsub3_reg_wire_clk or posedge addsub3_reg_wire_clr)
13999 if ((addsub3_reg_wire_clr == 1) && (multiplier3_direction == "UNUSED"))
14001 else if ((addsub3_reg_wire_clk == 1) && (addsub3_reg_wire_en == 1))
14002 addsub3_reg <= addsub3_int;
14006 // -------------------------------------------------------------------------------------------
14007 // This block contains 1 register and 1 combinatorial block (to set addsub3_pipe)
14008 // Signal Registered : addsub3_reg
14010 // Register is controlled by posedge addsub3_pipe_wire_clk
14011 // Register has a clock enable addsub3_pipe_wire_en
14012 // Register has an asynchronous clear signal, addsub3_pipe_wire_clr
14013 // NOTE : The combinatorial block will be executed if
14014 // addnsub_multiplier_pipeline_register3 is unregistered and addsub3_reg changes value
14015 // ------------------------------------------------------------------------------------------
14016 assign addsub3_pipe_wire = (addnsub_multiplier_pipeline_register3 == "UNREGISTERED")?
14017 addsub3_wire : addsub3_pipe_reg;
14019 always @(posedge addsub3_pipe_wire_clk or posedge addsub3_pipe_wire_clr)
14021 if ((addsub3_pipe_wire_clr == 1) && (multiplier3_direction == "UNUSED"))
14022 addsub3_pipe_reg <= 0;
14023 else if ((addsub3_pipe_wire_clk == 1) && (addsub3_pipe_wire_en == 1))
14024 addsub3_pipe_reg <= addsub3_wire;
14028 // ----------------------------------------------------------------------------
14029 // This block contains 1 register and 1 combinatorial block (to set sign_a_reg)
14030 // Signal Registered : sign_a_int
14032 // Register is controlled by posedge sign_reg_a_wire_clk
14033 // Register has a clock enable sign_reg_a_wire_en
14034 // Register has an asynchronous clear signal, sign_reg_a_wire_clr
14035 // NOTE : The combinatorial block will be executed if
14036 // signed_register_a is unregistered and sign_a_int changes value
14037 // ----------------------------------------------------------------------------
14039 assign sign_a_wire = (signed_register_a == "UNREGISTERED")? sign_a_int : sign_a_reg;
14040 always @(posedge sign_reg_a_wire_clk or posedge sign_reg_a_wire_clr)
14042 if ((sign_reg_a_wire_clr == 1) && (representation_a == "UNUSED"))
14044 else if ((sign_reg_a_wire_clk == 1) && (sign_reg_a_wire_en == 1))
14045 sign_a_reg <= sign_a_int;
14049 // ------------------------------------------------------------------------------
14050 // This block contains 1 register and 1 combinatorial block (to set sign_a_pipe)
14051 // Signal Registered : sign_a_reg
14053 // Register is controlled by posedge sign_pipe_a_wire_clk
14054 // Register has a clock enable sign_pipe_a_wire_en
14055 // Register has an asynchronous clear signal, sign_pipe_a_wire_clr
14056 // NOTE : The combinatorial block will be executed if
14057 // signed_pipeline_register_a is unregistered and sign_a_reg changes value
14058 // ------------------------------------------------------------------------------
14060 assign sign_a_pipe_wire = (signed_pipeline_register_a == "UNREGISTERED")? sign_a_wire : sign_a_pipe_reg;
14061 always @(posedge sign_pipe_a_wire_clk or posedge sign_pipe_a_wire_clr)
14063 if ((sign_pipe_a_wire_clr == 1) && (representation_a == "UNUSED"))
14064 sign_a_pipe_reg <= 0;
14065 else if ((sign_pipe_a_wire_clk == 1) && (sign_pipe_a_wire_en == 1))
14066 sign_a_pipe_reg <= sign_a_wire;
14070 // ----------------------------------------------------------------------------
14071 // This block contains 1 register and 1 combinatorial block (to set sign_b_reg)
14072 // Signal Registered : sign_b_int
14074 // Register is controlled by posedge sign_reg_b_wire_clk
14075 // Register has a clock enable sign_reg_b_wire_en
14076 // Register has an asynchronous clear signal, sign_reg_b_wire_clr
14077 // NOTE : The combinatorial block will be executed if
14078 // signed_register_b is unregistered and sign_b_int changes value
14079 // ----------------------------------------------------------------------------
14081 assign sign_b_wire = (signed_register_b == "UNREGISTERED")? sign_b_int : sign_b_reg;
14083 always @(posedge sign_reg_b_wire_clk or posedge sign_reg_b_wire_clr)
14085 if ((sign_reg_b_wire_clr == 1) && (representation_b == "UNUSED"))
14087 else if ((sign_reg_b_wire_clk == 1) && (sign_reg_b_wire_en == 1))
14088 sign_b_reg <= sign_b_int;
14093 // ------------------------------------------------------------------------------
14094 // This block contains 1 register and 1 combinatorial block (to set sign_b_pipe)
14095 // Signal Registered : sign_b_reg
14097 // Register is controlled by posedge sign_pipe_b_wire_clk
14098 // Register has a clock enable sign_pipe_b_wire_en
14099 // Register has an asynchronous clear signal, sign_pipe_b_wire_clr
14100 // NOTE : The combinatorial block will be executed if
14101 // signed_pipeline_register_b is unregistered and sign_b_reg changes value
14102 // ------------------------------------------------------------------------------
14103 assign sign_b_pipe_wire = (signed_pipeline_register_b == "UNREGISTERED")? sign_b_wire : sign_b_pipe_reg;
14104 always @(posedge sign_pipe_b_wire_clk or posedge sign_pipe_b_wire_clr)
14107 if ((sign_pipe_b_wire_clr == 1) && (representation_b == "UNUSED"))
14108 sign_b_pipe_reg <= 0;
14109 else if ((sign_pipe_b_wire_clk == 1) && (sign_pipe_b_wire_en == 1))
14110 sign_b_pipe_reg <= sign_b_wire;
14115 // --------------------------------------------------------
14116 // This block basically calls the task do_multiply() to set
14117 // the value of mult_res_0[(int_width_a + int_width_b) -1 :0]
14119 // If multiplier_register0 is registered, the call of the task
14120 // will be triggered by a posedge multiplier_reg0_wire_clk.
14121 // It also has an asynchronous clear signal multiplier_reg0_wire_clr
14123 // If multiplier_register0 is unregistered, a change of value
14124 // in either mult_a[int_width_a-1:0], mult_b[int_width_a-1:0],
14125 // sign_a_reg or sign_b_reg will trigger the task call.
14126 // --------------------------------------------------------
14127 assign mult_res_wire[(int_width_a + int_width_b - 1) :0] = (multiplier_register0 == "UNREGISTERED")?
14128 mult0_result[(int_width_a + int_width_b - 1) :0] :
14129 mult_res_reg[(int_width_a + int_width_b - 1) :0];
14131 assign mult_saturate_overflow_vec[0] = (multiplier_register0 == "UNREGISTERED")?
14132 mult0_saturate_overflow : mult_saturate_overflow_reg[0];
14135 // This always block is to perform the rounding and saturation operations (StratixII only)
14136 always @(mult_res_0 or mult01_round_wire or mult01_saturate_wire)
14138 if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family))
14140 // -------------------------------------------------------
14141 // Stratix II Rounding support
14142 // This block basically carries out the rounding for the
14143 // mult_res_0. The equation to get the mult0_round_out is
14144 // obtained from the Stratix II Mac FFD which is below:
14145 // round_adder_constant = (1 << (wfraction - wfraction_round - 1))
14146 // roundout[] = datain[] + round_adder_constant
14147 // For Stratix II rounding, we round up the bits to 15 bits
14148 // or in another word wfraction_round = 15.
14149 // --------------------------------------------------------
14151 if ((multiplier01_rounding == "YES") ||
14152 ((multiplier01_rounding == "VARIABLE") && (mult01_round_wire == 1)))
14154 mult0_round_out[(int_width_a + int_width_b) -1 :0] = mult_res_0[(int_width_a + int_width_b) -1 :0] + ( 1 << (`MULT_ROUND_BITS - 1));
14158 mult0_round_out[(int_width_a + int_width_b) -1 :0] = mult_res_0[(int_width_a + int_width_b) -1 :0];
14161 mult0_round_out[((int_width_a + int_width_b) + 2) : (int_width_a + int_width_b)] = {2{1'b0}};
14163 // -------------------------------------------------------
14164 // Stratix II Saturation support
14165 // This carries out the saturation for mult0_round_out.
14166 // The equation to get the saturated result is obtained
14167 // from Stratix II MAC FFD which is below:
14168 // satoverflow = 1 if sign bit is different
14169 // satvalue[wtotal-1 : wfraction] = roundout[wtotal-1]
14170 // satvalue[wfraction-1 : 0] = !roundout[wtotal-1]
14171 // -------------------------------------------------------
14173 if ((multiplier01_saturation == "YES") ||
14174 (( multiplier01_saturation == "VARIABLE") && (mult01_saturate_wire == 1)))
14177 mult0_saturate_overflow_stat = (~mult0_round_out[int_width_a + int_width_b - 1]) && mult0_round_out[int_width_a + int_width_b - 2];
14179 if (mult0_saturate_overflow_stat == 0)
14181 mult0_saturate_out = mult0_round_out;
14182 mult0_saturate_overflow = mult0_round_out[0];
14187 // We are doing Q2.31 saturation
14188 for (num_bit_mult0 = (int_width_a + int_width_b - 1); num_bit_mult0 >= (int_width_a + int_width_b - 2); num_bit_mult0 = num_bit_mult0 - 1)
14190 mult0_saturate_out[num_bit_mult0] = mult0_round_out[int_width_a + int_width_b - 1];
14193 for (num_bit_mult0 = sat_ini_value; num_bit_mult0 >= 3; num_bit_mult0 = num_bit_mult0 - 1)
14195 mult0_saturate_out[num_bit_mult0] = ~mult0_round_out[int_width_a + int_width_b - 1];
14198 mult0_saturate_out[2 : 0] = mult0_round_out[2:0];
14200 mult0_saturate_overflow = mult0_saturate_overflow_stat;
14205 mult0_saturate_out = mult0_round_out;
14206 mult0_saturate_overflow = 1'b0;
14209 if ((multiplier01_rounding == "YES") ||
14210 ((multiplier01_rounding == "VARIABLE") && (mult01_round_wire == 1)))
14213 for (num_bit_mult0 = (`MULT_ROUND_BITS - 1); num_bit_mult0 >= 0; num_bit_mult0 = num_bit_mult0 - 1)
14215 mult0_saturate_out[num_bit_mult0] = 1'b0;
14222 always @(mult0_saturate_out or mult_res_0)
14224 if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family))
14226 mult0_result <= mult0_saturate_out[(int_width_a + int_width_b) -1 :0];
14230 mult0_result <= mult_res_0;
14237 always @(posedge multiplier_reg0_wire_clk or posedge multiplier_reg0_wire_clr)
14239 if (multiplier_reg0_wire_clr == 1)
14241 mult_res_reg[(int_width_a + int_width_b) -1 :0] <= 0;
14242 mult_saturate_overflow_reg[0] <= 0;
14244 else if ((multiplier_reg0_wire_clk == 1) && (multiplier_reg0_wire_en == 1))
14246 if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0)
14247 mult_res_reg[(int_width_a + int_width_b) - 1 : 0] <= mult_res_0[(int_width_a + int_width_b) -1 :0];
14250 mult_res_reg[(int_width_a + int_width_b - 1) : 0] <= mult0_result;
14251 mult_saturate_overflow_reg[0] <= mult0_saturate_overflow;
14258 always @(mult_a_wire[(int_width_a *1) -1 : (int_width_a*0)] or mult_b_wire[(int_width_b *1) -1 : (int_width_b *0)] or
14259 sign_a_wire or sign_b_wire)
14261 mult_res_0 = do_multiply (0, sign_a_wire, sign_b_wire);
14267 // ------------------------------------------------------------------------
14268 // This block basically calls the task do_multiply() to set the value of
14269 // mult_res_1[(int_width_a + int_width_b) -1 :0]
14271 // If multiplier_register1 is registered, the call of the task
14272 // will be triggered by a posedge multiplier_reg1_wire_clk.
14273 // It also has an asynchronous clear signal multiplier_reg1_wire_clr
14275 // If multiplier_register1 is unregistered, a change of value
14276 // in either mult_a[(2*int_width_a)-1:int_width_a], mult_b[(2*int_width_a)-1:int_width_a],
14277 // sign_a_reg or sign_b_reg will trigger the task call.
14278 // -----------------------------------------------------------------------
14280 assign mult_res_wire[(((int_width_a + int_width_b) *2) - 1) : (int_width_a + int_width_b)] = (multiplier_register1 == "UNREGISTERED")?
14281 mult1_result[(int_width_a + int_width_b - 1) : 0]:
14282 mult_res_reg[((int_width_a + int_width_b) *2) - 1: (int_width_a + int_width_b)];
14284 assign mult_saturate_overflow_vec[1] = (multiplier_register1 == "UNREGISTERED")?
14285 mult1_saturate_overflow : mult_saturate_overflow_reg[1];
14288 // This always block is to perform the rounding and saturation operations (StratixII only)
14289 always @(mult_res_1 or mult01_round_wire or mult01_saturate_wire)
14291 if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family))
14293 // -------------------------------------------------------
14294 // Stratix II Rounding support
14295 // This block basically carries out the rounding for the
14296 // mult_res_1. The equation to get the mult1_round_out is
14297 // obtained from the Stratix II Mac FFD which is below:
14298 // round_adder_constant = (1 << (wfraction - wfraction_round - 1))
14299 // roundout[] = datain[] + round_adder_constant
14300 // For Stratix II rounding, we round up the bits to 15 bits
14301 // or in another word wfraction_round = 15.
14302 // --------------------------------------------------------
14304 if ((multiplier01_rounding == "YES") ||
14305 ((multiplier01_rounding == "VARIABLE") && (mult01_round_wire == 1)))
14307 mult1_round_out[(int_width_a + int_width_b) -1 :0] = mult_res_1[(int_width_a + int_width_b) -1 :0] + ( 1 << (`MULT_ROUND_BITS - 1));
14311 mult1_round_out[(int_width_a + int_width_b) -1 :0] = mult_res_1[(int_width_a + int_width_b) -1 :0];
14314 mult1_round_out[((int_width_a + int_width_b) + 2) : (int_width_a + int_width_b)] = {2{1'b0}};
14317 // -------------------------------------------------------
14318 // Stratix II Saturation support
14319 // This carries out the saturation for mult1_round_out.
14320 // The equation to get the saturated result is obtained
14321 // from Stratix II MAC FFD which is below:
14322 // satoverflow = 1 if sign bit is different
14323 // satvalue[wtotal-1 : wfraction] = roundout[wtotal-1]
14324 // satvalue[wfraction-1 : 0] = !roundout[wtotal-1]
14325 // -------------------------------------------------------
14328 if ((multiplier01_saturation == "YES") ||
14329 (( multiplier01_saturation == "VARIABLE") && (mult01_saturate_wire == 1)))
14331 mult1_saturate_overflow_stat = (~mult1_round_out[int_width_a + int_width_b - 1]) && mult1_round_out[int_width_a + int_width_b - 2];
14333 if (mult1_saturate_overflow_stat == 0)
14335 mult1_saturate_out = mult1_round_out;
14336 mult1_saturate_overflow = mult1_round_out[0];
14340 // We are doing Q2.31 saturation. Thus we would insert additional bit
14342 for (num_bit_mult1 = (int_width_a + int_width_b - 1); num_bit_mult1 >= (int_width_a + int_width_b - 2); num_bit_mult1 = num_bit_mult1 - 1)
14344 mult1_saturate_out[num_bit_mult1] = mult1_round_out[int_width_a + int_width_b - 1];
14347 for (num_bit_mult1 = sat_ini_value; num_bit_mult1 >= 3; num_bit_mult1 = num_bit_mult1 - 1)
14349 mult1_saturate_out[num_bit_mult1] = ~mult1_round_out[int_width_a + int_width_b - 1];
14352 mult1_saturate_out[2:0] = mult1_round_out[2:0];
14353 mult1_saturate_overflow = mult1_saturate_overflow_stat;
14358 mult1_saturate_out = mult1_round_out;
14359 mult1_saturate_overflow = 1'b0;
14362 if ((multiplier01_rounding == "YES") ||
14363 ((multiplier01_rounding == "VARIABLE") && (mult01_round_wire == 1)))
14366 for (num_bit_mult1 = (`MULT_ROUND_BITS - 1); num_bit_mult1 >= 0; num_bit_mult1 = num_bit_mult1 - 1)
14368 mult1_saturate_out[num_bit_mult1] = 1'b0;
14375 always @(mult1_saturate_out or mult_res_1)
14377 if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family))
14379 mult1_result <= mult1_saturate_out[(int_width_a + int_width_b) -1 :0];
14383 mult1_result <= mult_res_1;
14388 always @(posedge multiplier_reg1_wire_clk or posedge multiplier_reg1_wire_clr)
14390 if (multiplier_reg1_wire_clr == 1)
14392 mult_res_reg[((int_width_a + int_width_b) *2) -1 : (int_width_a + int_width_b)] <= 0;
14393 mult_saturate_overflow_reg[1] <= 0;
14395 else if ((multiplier_reg1_wire_clk == 1) && (multiplier_reg1_wire_en == 1))
14396 if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0)
14397 mult_res_reg[((int_width_a + int_width_b) *2) -1 : (int_width_a + int_width_b)] <=
14398 mult_res_1[(int_width_a + int_width_b) -1 :0];
14401 mult_res_reg[((int_width_a + int_width_b) *2) -1 : (int_width_a + int_width_b)] <= mult1_result;
14402 mult_saturate_overflow_reg[1] <= mult1_saturate_overflow;
14407 always @(mult_a_wire[(int_width_a *2) -1 : (int_width_a*1)] or mult_b_wire[(int_width_b *2) -1 : (int_width_b *1)] or
14408 sign_a_wire or sign_b_wire)
14411 mult_res_1 = do_multiply (1, sign_a_wire, sign_b_wire);
14418 // ----------------------------------------------------------------------------
14419 // This block basically calls the task do_multiply() to set the value of
14420 // mult_res_2[(int_width_a + int_width_b) -1 :0]
14422 // If multiplier_register2 is registered, the call of the task
14423 // will be triggered by a posedge multiplier_reg2_wire_clk.
14424 // It also has an asynchronous clear signal multiplier_reg2_wire_clr
14426 // If multiplier_register2 is unregistered, a change of value
14427 // in either mult_a[(3*int_width_a)-1:2*int_width_a], mult_b[(3*int_width_a)-1:2*int_width_a],
14428 // sign_a_reg or sign_b_reg will trigger the task call.
14429 // ---------------------------------------------------------------------------
14431 assign mult_res_wire[((int_width_a + int_width_b) *3) -1 : (2*(int_width_a + int_width_b))] = (multiplier_register2 == "UNREGISTERED")?
14432 mult2_result[(int_width_a + int_width_b) -1 :0] :
14433 mult_res_reg[((int_width_a + int_width_b) *3) -1 : (2*(int_width_a + int_width_b))];
14435 assign mult_saturate_overflow_vec[2] = (multiplier_register2 == "UNREGISTERED")?
14436 mult2_saturate_overflow : mult_saturate_overflow_reg[2];
14438 // This always block is to perform the rounding and saturation operations (StratixII only)
14439 always @(mult_res_2 or mult23_round_wire or mult23_saturate_wire)
14441 if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family))
14443 // -------------------------------------------------------
14444 // Stratix II Rounding support
14445 // This block basically carries out the rounding for the
14446 // mult_res_2. The equation to get the mult2_round_out is
14447 // obtained from the Stratix II Mac FFD which is below:
14448 // round_adder_constant = (1 << (wfraction - wfraction_round - 1))
14449 // roundout[] = datain[] + round_adder_constant
14450 // For Stratix II rounding, we round up the bits to 15 bits
14451 // or in another word wfraction_round = 15.
14452 // --------------------------------------------------------
14454 if ((multiplier23_rounding == "YES") ||
14455 ((multiplier23_rounding == "VARIABLE") && (mult23_round_wire == 1)))
14457 mult2_round_out[(int_width_a + int_width_b) -1 :0] = mult_res_2[(int_width_a + int_width_b) -1 :0] + ( 1 << (`MULT_ROUND_BITS - 1));
14461 mult2_round_out[(int_width_a + int_width_b) -1 :0] = mult_res_2[(int_width_a + int_width_b) -1 :0];
14464 mult2_round_out[((int_width_a + int_width_b) + 2) : (int_width_a + int_width_b)] = {2{1'b0}};
14466 // -------------------------------------------------------
14467 // Stratix II Saturation support
14468 // This carries out the saturation for mult2_round_out.
14469 // The equation to get the saturated result is obtained
14470 // from Stratix II MAC FFD which is below:
14471 // satoverflow = 1 if sign bit is different
14472 // satvalue[wtotal-1 : wfraction] = roundout[wtotal-1]
14473 // satvalue[wfraction-1 : 0] = !roundout[wtotal-1]
14474 // -------------------------------------------------------
14477 if ((multiplier23_saturation == "YES") ||
14478 (( multiplier23_saturation == "VARIABLE") && (mult23_saturate_wire == 1)))
14480 mult2_saturate_overflow_stat = (~mult2_round_out[int_width_a + int_width_b - 1]) && mult2_round_out[int_width_a + int_width_b - 2];
14482 if (mult2_saturate_overflow_stat == 0)
14484 mult2_saturate_out = mult2_round_out;
14485 mult2_saturate_overflow = mult2_round_out[0];
14489 // We are doing Q2.31 saturation. Thus we would insert additional bit
14491 for (num_bit_mult2 = (int_width_a + int_width_b - 1); num_bit_mult2 >= (int_width_a + int_width_b - 2); num_bit_mult2 = num_bit_mult2 - 1)
14493 mult2_saturate_out[num_bit_mult2] = mult2_round_out[int_width_a + int_width_b - 1];
14496 for (num_bit_mult2 = sat_ini_value; num_bit_mult2 >= 3; num_bit_mult2 = num_bit_mult2 - 1)
14498 mult2_saturate_out[num_bit_mult2] = ~mult2_round_out[int_width_a + int_width_b - 1];
14501 mult2_saturate_out[2:0] = mult2_round_out[2:0];
14502 mult2_saturate_overflow = mult2_saturate_overflow_stat;
14507 mult2_saturate_out = mult2_round_out;
14508 mult2_saturate_overflow = 1'b0;
14511 if ((multiplier23_rounding == "YES") ||
14512 ((multiplier23_rounding == "VARIABLE") && (mult23_round_wire == 1)))
14515 for (num_bit_mult2 = (`MULT_ROUND_BITS - 1); num_bit_mult2 >= 0; num_bit_mult2 = num_bit_mult2 - 1)
14517 mult2_saturate_out[num_bit_mult2] = 1'b0;
14524 always @(mult2_saturate_out or mult_res_2)
14526 if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family))
14528 mult2_result <= mult2_saturate_out[(int_width_a + int_width_b) -1 :0];
14532 mult2_result <= mult_res_2;
14537 always @(posedge multiplier_reg2_wire_clk or posedge multiplier_reg2_wire_clr)
14539 if (multiplier_reg2_wire_clr == 1)
14541 mult_res_reg[((int_width_a + int_width_b) *3) -1 : (2*(int_width_a + int_width_b))] <= 0;
14542 mult_saturate_overflow_reg[2] <= 0;
14544 else if ((multiplier_reg2_wire_clk == 1) && (multiplier_reg2_wire_en == 1))
14545 if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0)
14546 mult_res_reg[((int_width_a + int_width_b) *3) -1 : (2*(int_width_a + int_width_b))] <=
14547 mult_res_2[(int_width_a + int_width_b) -1 :0];
14550 mult_res_reg[((int_width_a + int_width_b) *3) -1 : (2*(int_width_a + int_width_b))] <= mult2_result;
14551 mult_saturate_overflow_reg[2] <= mult2_saturate_overflow;
14555 always @(mult_a_wire[(int_width_a *3) -1 : (int_width_a*2)] or mult_b_wire[(int_width_b *3) -1 : (int_width_b *2)] or
14556 sign_a_wire or sign_b_wire)
14558 mult_res_2 = do_multiply (2, sign_a_wire, sign_b_wire);
14564 // ----------------------------------------------------------------------------
14565 // This block basically calls the task do_multiply() to set the value of
14566 // mult_res_3[(int_width_a + int_width_b) -1 :0]
14568 // If multiplier_register3 is registered, the call of the task
14569 // will be triggered by a posedge multiplier_reg3_wire_clk.
14570 // It also has an asynchronous clear signal multiplier_reg3_wire_clr
14572 // If multiplier_register3 is unregistered, a change of value
14573 // in either mult_a[(4*int_width_a)-1:3*int_width_a], mult_b[(4*int_width_a)-1:3*int_width_a],
14574 // sign_a_reg or sign_b_reg will trigger the task call.
14575 // ---------------------------------------------------------------------------
14577 assign mult_res_wire[((int_width_a + int_width_b) *4) -1 : 3*(int_width_a + int_width_b)] = (multiplier_register3 == "UNREGISTERED")?
14578 mult3_result[(int_width_a + int_width_b) -1 :0] :
14579 mult_res_reg[((int_width_a + int_width_b) *4) -1 : 3*(int_width_a + int_width_b)];
14581 assign mult_saturate_overflow_vec[3] = (multiplier_register3 == "UNREGISTERED")?
14582 mult3_saturate_overflow : mult_saturate_overflow_reg[3];
14584 // This always block is to perform the rounding and saturation operations (StratixII only)
14585 always @(mult_res_3 or mult23_round_wire or mult23_saturate_wire)
14587 if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family))
14589 // -------------------------------------------------------
14590 // Stratix II Rounding support
14591 // This block basically carries out the rounding for the
14592 // mult_res_3. The equation to get the mult3_round_out is
14593 // obtained from the Stratix II Mac FFD which is below:
14594 // round_adder_constant = (1 << (wfraction - wfraction_round - 1))
14595 // roundout[] = datain[] + round_adder_constant
14596 // For Stratix II rounding, we round up the bits to 15 bits
14597 // or in another word wfraction_round = 15.
14598 // --------------------------------------------------------
14600 if ((multiplier23_rounding == "YES") ||
14601 ((multiplier23_rounding == "VARIABLE") && (mult23_round_wire == 1)))
14603 mult3_round_out[(int_width_a + int_width_b) -1 :0] = mult_res_3[(int_width_a + int_width_b) -1 :0] + ( 1 << (`MULT_ROUND_BITS - 1));
14607 mult3_round_out[(int_width_a + int_width_b) -1 :0] = mult_res_3[(int_width_a + int_width_b) -1 :0];
14610 mult3_round_out[((int_width_a + int_width_b) + 2) : (int_width_a + int_width_b)] = {2{1'b0}};
14612 // -------------------------------------------------------
14613 // Stratix II Saturation support
14614 // This carries out the saturation for mult3_round_out.
14615 // The equation to get the saturated result is obtained
14616 // from Stratix II MAC FFD which is below:
14617 // satoverflow = 1 if sign bit is different
14618 // satvalue[wtotal-1 : wfraction] = roundout[wtotal-1]
14619 // satvalue[wfraction-1 : 0] = !roundout[wtotal-1]
14620 // -------------------------------------------------------
14623 if ((multiplier23_saturation == "YES") ||
14624 (( multiplier23_saturation == "VARIABLE") && (mult23_saturate_wire == 1)))
14626 mult3_saturate_overflow_stat = (~mult3_round_out[int_width_a + int_width_b - 1]) && mult3_round_out[int_width_a + int_width_b - 2];
14628 if (mult3_saturate_overflow_stat == 0)
14630 mult3_saturate_out = mult3_round_out;
14631 mult3_saturate_overflow = mult3_round_out[0];
14635 // We are doing Q2.31 saturation. Thus we would make sure the 3 LSB bits isn't reset
14636 for (num_bit_mult3 = (int_width_a + int_width_b -1); num_bit_mult3 >= (int_width_a + int_width_b - 2); num_bit_mult3 = num_bit_mult3 - 1)
14638 mult3_saturate_out[num_bit_mult3] = mult3_round_out[int_width_a + int_width_b - 1];
14641 for (num_bit_mult3 = sat_ini_value; num_bit_mult3 >= 3; num_bit_mult3 = num_bit_mult3 - 1)
14643 mult3_saturate_out[num_bit_mult3] = ~mult3_round_out[int_width_a + int_width_b - 1];
14646 mult3_saturate_out[2:0] = mult3_round_out[2:0];
14647 mult3_saturate_overflow = mult3_saturate_overflow_stat;
14652 mult3_saturate_out = mult3_round_out;
14653 mult3_saturate_overflow = 1'b0;
14656 if ((multiplier23_rounding == "YES") ||
14657 ((multiplier23_rounding == "VARIABLE") && (mult23_round_wire == 1)))
14660 for (num_bit_mult3 = (`MULT_ROUND_BITS - 1); num_bit_mult3 >= 0; num_bit_mult3 = num_bit_mult3 - 1)
14662 mult3_saturate_out[num_bit_mult3] = 1'b0;
14669 always @(mult3_saturate_out or mult_res_3)
14671 if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family))
14673 mult3_result <= mult3_saturate_out[(int_width_a + int_width_b) -1 :0];
14677 mult3_result <= mult_res_3;
14682 always @(posedge multiplier_reg3_wire_clk or posedge multiplier_reg3_wire_clr)
14684 if (multiplier_reg3_wire_clr == 1)
14686 mult_res_reg[((int_width_a + int_width_b) *4) -1 : (3*(int_width_a + int_width_b))] <= 0;
14687 mult_saturate_overflow_reg[3] <= 0;
14689 else if ((multiplier_reg3_wire_clk == 1) && (multiplier_reg3_wire_en == 1))
14690 if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0)
14691 mult_res_reg[((int_width_a + int_width_b) *4) -1 : (3*(int_width_a + int_width_b))] <=
14692 mult_res_3[(int_width_a + int_width_b) -1 :0];
14695 mult_res_reg[((int_width_a + int_width_b) *4) -1: 3*(int_width_a + int_width_b)] <= mult3_result;
14696 mult_saturate_overflow_reg[3] <= mult3_saturate_overflow;
14704 always @(mult_a_wire[(int_width_a *4) -1 : (int_width_a*3)] or mult_b_wire[(int_width_b *4) -1 : (int_width_b *3)] or
14705 sign_a_wire or sign_b_wire)
14707 mult_res_3 = do_multiply (3, sign_a_wire, sign_b_wire);
14711 //------------------------------
14712 // Continuous assign statements
14713 //------------------------------
14715 // Clock in all the A input registers
14716 assign i_scanina = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0)?
14717 dataa_int[int_width_a-1:0] : scanina_z;
14719 assign mult_a_pre[int_width_a-1:0] = (input_source_a0 == "DATAA")? dataa_int[int_width_a-1:0] :
14720 (input_source_a0 == "SCANA")? i_scanina :
14721 (sourcea_wire[0] == 1)? scanina_z : dataa_int[int_width_a-1:0];
14723 assign mult_a_pre[(2*int_width_a)-1:int_width_a] = (input_source_a1 == "DATAA") ? dataa_int[(2*int_width_a)-1:int_width_a] :
14724 (input_source_a1 == "SCANA")? mult_a_wire[int_width_a-1:0] :
14725 (sourcea_wire[1] == 1)? mult_a_wire[int_width_a-1:0] : dataa_int[(2*int_width_a)-1:int_width_a];
14727 assign mult_a_pre[(3*int_width_a)-1:2*int_width_a] = (input_source_a2 == "DATAA") ? dataa_int[(3*int_width_a)-1:2*int_width_a] :
14728 (input_source_a2 == "SCANA")? mult_a_wire[(2*int_width_a)-1:int_width_a] :
14729 (sourcea_wire[2] == 1)? mult_a_wire[(2*int_width_a)-1:int_width_a] : dataa_int[(3*int_width_a)-1:2*int_width_a];
14731 assign mult_a_pre[(4*int_width_a)-1:3*int_width_a] = (input_source_a3 == "DATAA") ? dataa_int[(4*int_width_a)-1:3*int_width_a] :
14732 (input_source_a3 == "SCANA")? mult_a_wire[(3*int_width_a)-1:2*int_width_a] :
14733 (sourcea_wire[3] == 1)? mult_a_wire[(3*int_width_a)-1:2*int_width_a] : dataa_int[(4*int_width_a)-1:3*int_width_a];
14735 assign scanouta = mult_a_wire[(number_of_multipliers * int_width_a)-1 : ((number_of_multipliers-1) * int_width_a) + (int_width_a - width_a)];
14736 assign scanoutb = mult_b_wire[(number_of_multipliers * int_width_b)-1 : ((number_of_multipliers-1) * int_width_b) + (int_width_b - width_b)];
14738 // Clock in all the B input registers
14739 assign i_scaninb = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0)?
14740 datab_int[int_width_b-1:0] : scaninb_z;
14742 assign mult_b_pre[int_width_b-1:0] = (input_source_b0 == "DATAB")? datab_int[int_width_b-1:0] :
14743 (input_source_b0 == "SCANB")? i_scaninb :
14744 (sourceb_wire[0] == 1)? scaninb_z : datab_int[int_width_b-1:0];
14746 assign mult_b_pre[(2*int_width_b)-1:int_width_b] = (input_source_b1 == "DATAB") ? datab_int[(2*int_width_b)-1 : int_width_b ]:
14747 (input_source_b1 == "SCANB")? mult_b_wire[int_width_b -1 : 0] :
14748 (sourceb_wire[1] == 1)? mult_b_wire[int_width_b -1 : 0] : datab_int[(2*int_width_b)-1 : int_width_b ];
14750 assign mult_b_pre[(3*int_width_b)-1:2*int_width_b] = (input_source_b2 == "DATAB") ? datab_int[(3*int_width_b)-1:2*int_width_b] :
14751 (input_source_b2 == "SCANB")? mult_b_wire[(2*int_width_b)-1:int_width_b] :
14752 (sourceb_wire[2] == 1)? mult_b_wire[(2*int_width_b)-1:int_width_b] : datab_int[(3*int_width_b)-1:2*int_width_b];
14754 assign mult_b_pre[(4*int_width_b)-1:3*int_width_b] = (input_source_b3 == "DATAB") ? datab_int[(4*int_width_b)-1:3*int_width_b] :
14755 (input_source_b3 == "SCANB")? mult_b_wire[(3*int_width_b)-1:2*int_width_b] :
14756 (sourceb_wire[3] == 1)? mult_b_wire[(3*int_width_b)-1:2*int_width_b] : datab_int[(4*int_width_b)-1:3*int_width_b];
14758 // clock in all the control signals
14759 assign addsub1_int = ((port_addnsub1 == "PORT_CONNECTIVITY")?
14760 ((multiplier1_direction != "UNUSED")? (multiplier1_direction == "ADD" ? 1 : 0) : addnsub1_z) :
14761 ((port_addnsub1 == "PORT_USED")? addnsub1_z :
14762 (port_addnsub1 == "PORT_UNUSED")? (multiplier1_direction == "ADD" ? 1 : 0) : addnsub1_z));
14764 assign addsub3_int = ((port_addnsub3 == "PORT_CONNECTIVITY")?
14765 ((multiplier3_direction != "UNUSED") ? (multiplier3_direction == "ADD" ? 1 : 0) : addnsub3_z) :
14766 ((port_addnsub3 == "PORT_USED")? addnsub3_z :
14767 (port_addnsub3 == "PORT_UNUSED")? (multiplier3_direction == "ADD" ? 1 : 0) : addnsub3_z));
14769 assign sign_a_int = ((port_signa == "PORT_CONNECTIVITY")?
14770 ((representation_a != "UNUSED") ? (representation_a == "SIGNED" ? 1 : 0) : signa_z) :
14771 (port_signa == "PORT_USED")? signa_z :
14772 (port_signa == "PORT_UNUSED")? (representation_a == "SIGNED" ? 1 : 0) : signa_z);
14774 assign sign_b_int = ((port_signb == "PORT_CONNECTIVITY")?
14775 ((representation_b != "UNUSED") ? (representation_b == "SIGNED" ? 1 : 0) : signb_z) :
14776 (port_signb == "PORT_USED")? signb_z :
14777 (port_signb == "PORT_UNUSED")? (representation_b == "SIGNED" ? 1 : 0) : signb_z);
14781 // -----------------------------------------------------------------
14782 // This is the main block that performs the addition and subtraction
14783 // -----------------------------------------------------------------
14785 assign result = (output_register == "UNREGISTERED")?
14786 temp_sum[width_result - 1 + int_mult_diff_bit : int_mult_diff_bit]: temp_sum_reg[width_result - 1 + int_mult_diff_bit:int_mult_diff_bit];
14788 assign mult_is_saturate_vec = (output_register == "UNREGISTERED")?
14789 mult_saturate_overflow_vec: mult_saturate_overflow_pipe_reg;
14791 always @(posedge output_reg_wire_clk or posedge output_reg_wire_clr)
14793 if (output_reg_wire_clr == 1)
14795 temp_sum_reg <= {(int_width_result + 1){1'b0}};
14797 for ( num_stor = extra_latency; num_stor >= 0; num_stor = num_stor - 1 )
14799 result_pipe[num_stor] <= {int_width_result{1'b0}};
14802 mult_saturate_overflow_pipe_reg <= {4{1'b0}};
14806 else if ((output_reg_wire_clk ==1) && (output_reg_wire_en ==1))
14809 if (extra_latency == 0)
14811 temp_sum_reg[int_width_result-1 :0] <= temp_sum[int_width_result-1 :0];
14815 result_pipe [head_result] <= temp_sum[int_width_result-1 :0];
14816 head_result <= (head_result +1) % (extra_latency + 1);
14818 mult_saturate_overflow_pipe_reg <= mult_saturate_overflow_vec;
14823 assign head_result_wire = head_result[31:0];
14825 always @(head_result_wire or result_pipe[head_result_wire])
14827 if (extra_latency != 0)
14828 temp_sum_reg[int_width_result-1 :0] <= result_pipe[head_result_wire];
14831 always @(mult_res_wire [4 * (int_width_a + int_width_b) -1:0] or
14832 addsub1_pipe_wire or addsub3_pipe_wire or
14833 sign_a_pipe_wire or sign_b_pipe_wire or addnsub1_round_pipe_wire or
14834 addnsub3_round_pipe_wire)
14837 for (num_mult = 0; num_mult < number_of_multipliers; num_mult = num_mult +1)
14840 mult_res_temp = mult_res_wire >> (num_mult * (int_width_a + int_width_b));
14841 mult_res_ext = ((int_width_result > (int_width_a + int_width_b))?
14842 {{(int_width_result - int_width_a - int_width_b)
14843 {mult_res_temp [int_width_a + int_width_b - 1] &
14844 (sign_a_pipe_wire | sign_b_pipe_wire)}}, mult_res_temp}:mult_res_temp);
14848 if (addsub1_pipe_wire)
14849 temp_sum = temp_sum + mult_res_ext;
14851 temp_sum = temp_sum - mult_res_ext;
14853 if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 1)
14855 // -------------------------------------------------------
14856 // Stratix II Rounding support
14857 // This block basically carries out the rounding for the
14858 // temp_sum. The equation to get the roundout for adder1 and
14859 // adder3 is obtained from the Stratix II Mac FFD which is below:
14860 // round_adder_constant = (1 << (wfraction - wfraction_round - 1))
14861 // roundout[] = datain[] + round_adder_constant
14862 // For Stratix II rounding, we round up the bits to 15 bits
14863 // or in another word wfraction_round = 15.
14864 // --------------------------------------------------------
14866 if ((adder1_rounding == "YES") ||
14867 ((adder1_rounding == "VARIABLE") && (addnsub1_round_pipe_wire == 1)))
14869 adder1_round_out = temp_sum + ( 1 << (`ADDER_ROUND_BITS - 1));
14871 for (j = (`ADDER_ROUND_BITS - 1); j >= 0; j = j - 1)
14873 adder1_round_out[j] = 1'b0;
14879 adder1_round_out = temp_sum;
14882 adder1_result = adder1_round_out;
14885 if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family))
14887 temp_sum = adder1_result;
14891 else if (num_mult == 3)
14893 if (addsub3_pipe_wire)
14894 temp_sum = temp_sum + mult_res_ext;
14896 temp_sum = temp_sum - mult_res_ext;
14898 if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 1)
14900 // StratixII rounding support
14901 // Please see the description for rounding support in adder1
14903 if ((adder3_rounding == "YES") ||
14904 ((adder3_rounding == "VARIABLE") && (addnsub3_round_pipe_wire == 1)))
14907 adder3_round_out = temp_sum + ( 1 << (`ADDER_ROUND_BITS - 1));
14909 for (j = (`ADDER_ROUND_BITS - 1); j >= 0; j = j - 1)
14911 adder3_round_out[j] = 1'b0;
14917 adder3_round_out = temp_sum;
14920 adder3_result = adder3_round_out;
14923 if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family))
14925 temp_sum = adder3_result;
14931 temp_sum = temp_sum + mult_res_ext;
14938 endmodule // end of ALTMULT_ADD
14941 //START_MODULE_NAME-------------------------------------------------------------
14943 // Module Name : altfp_mult
14945 // Description : Parameterized floating point multiplier megafunction.
14946 // This module implements IEEE-754 Compliant Floating Poing
14947 // Multiplier.It supports Single Precision, Single Extended
14948 // Precision and Double Precision floating point
14951 // Limitation : Fixed clock latency with 4 clock cycle delay.
14953 // Results expected: result of multiplication and the result's status bits
14955 //END_MODULE_NAME---------------------------------------------------------------
14957 // BEGINNING OF MODULE
14958 `timescale 1 ps / 1 ps
14960 module altfp_mult (
14961 clock, // Clock input to the multiplier.(Required)
14962 clk_en, // Clock enable for the multiplier.
14963 aclr, // Asynchronous clear for the multiplier.
14964 dataa, // Data input to the multiplier.(Required)
14965 datab, // Data input to the multiplier.(Required)
14966 result, // Multiplier output port.(Required)
14967 overflow, // Overflow port for the multiplier.
14968 underflow, // Underflow port for the multiplier.
14969 zero, // Zero port for the multiplier.
14970 denormal, // Denormal port for the multiplier.
14971 indefinite, // Indefinite port for the multiplier.
14972 nan // Nan port for the multiplier.
14975 // GLOBAL PARAMETER DECLARATION
14976 // Specifies the value of the exponent, Minimum = 8, Maximum = 31
14977 parameter width_exp = 8;
14978 // Specifies the value of the mantissa, Minimum = 23, Maximum = 52
14979 parameter width_man = 23;
14980 // Specifies whether to use dedicated multiplier circuitry.
14981 parameter dedicated_multiplier_circuitry = "AUTO";
14982 parameter reduced_functionality = "NO";
14983 parameter pipeline = 5;
14984 parameter lpm_hint = "UNUSED";
14985 parameter lpm_type = "altfp_mult";
14987 // LOCAL PARAMETER DECLARATION
14989 parameter LATENCY = pipeline -1;
14990 // Sum of mantissa's width and exponent's width
14991 parameter WIDTH_MAN_EXP = width_exp + width_man;
14993 // INPUT PORT DECLARATION
14994 input [WIDTH_MAN_EXP : 0] dataa;
14995 input [WIDTH_MAN_EXP : 0] datab;
15000 // OUTPUT PORT DECLARATION
15001 output [WIDTH_MAN_EXP : 0] result;
15009 // INTERNAL REGISTERS DECLARATION
15010 reg[width_man : 0] mant_dataa;
15011 reg[width_man : 0] mant_datab;
15012 reg[(2 * width_man) + 1 : 0] mant_result;
15014 reg zero_mant_dataa;
15015 reg zero_mant_datab;
15025 reg mant_result_msb;
15031 reg[WIDTH_MAN_EXP : 0] result_pipe[LATENCY : 0];
15032 reg[LATENCY : 0] overflow_pipe;
15033 reg[LATENCY : 0] underflow_pipe;
15034 reg[LATENCY : 0] zero_pipe;
15035 reg[LATENCY : 0] denormal_pipe;
15036 reg[LATENCY : 0] indefinite_pipe;
15037 reg[LATENCY : 0] nan_pipe;
15038 reg[WIDTH_MAN_EXP : 0] temp_result;
15043 reg indefinite_bit;
15046 // INTERNAL TRI DECLARATION
15050 // LOCAL INTEGER DECLARATION
15053 integer exp_result;
15063 // TASK DECLARATION
15065 // Add up two bits to get the result(<mantissa of datab> + <temporary result
15066 // of mantissa's multiplication>)
15067 //Also output the carry bit.
15069 // Value to be added to the temporary result of mantissa's multiplication.
15070 input [width_man : 0] val1;
15071 // temporary result of mantissa's multiplication.
15072 inout [(2 * width_man) + 1 : 0] temp_mant_result;
15073 output cout; // carry out bit
15075 reg co; // temporary storage to store the carry out bit
15079 for(i0 = 0; i0 <= width_man; i0 = i0 + 1)
15081 // if the carry out bit from the previous bit addition is 1'b0
15084 if (val1[i0] != temp_mant_result[i0 + width_man + 1])
15086 temp_mant_result[i0 + width_man + 1] = 1'b1;
15090 co = val1[i0] & temp_mant_result[i0 + width_man + 1];
15091 temp_mant_result[i0 + width_man + 1] = 1'b0;
15094 else // if (co == 1'b1)
15096 co = val1[i0] | temp_mant_result[i0 + width_man + 1];
15097 if (val1[i0] != temp_mant_result[i0 + width_man + 1])
15099 temp_mant_result[i0 + width_man + 1] = 1'b0;
15103 temp_mant_result[i0 + width_man + 1] = 1'b1;
15106 end // end of for loop
15109 endtask // add_bits
15111 // FUNCTON DECLARATION
15113 // Check whether the all the bits from index <index1> to <index2> is 1'b1
15114 // Return 1'b1 if true, otherwise return 1'b0
15115 function bit_all_0;
15116 input [(2 * width_man) + 1: 0] val;
15122 reg all_0; //temporary storage to indicate whether all the currently
15123 // checked bits are 1'b0
15127 for (i1 = index1; i1 <= index2; i1 = i1 + 1)
15129 if ((val[i1]) == 1'b1)
15132 disable LOOP_1; //break the loop to stop checking
15138 endfunction // bit_all_0
15140 // Calculate the exponential value (<base_number> power of <exponent_number>)
15141 function integer exponential_value;
15143 input exponent_number;
15144 integer base_number;
15145 integer exponent_number;
15146 integer value; // temporary storage to store the exponential value
15150 for (i2 = 0; i2 < exponent_number; i2 = i2 + 1)
15152 value = base_number * value;
15154 exponential_value = value;
15156 endfunction // exponential_value
15158 // INITIAL CONSTRUCT BLOCK
15160 begin : INITIALIZATION
15161 for(i3 = LATENCY; i3 >= 0; i3 = i3 - 1)
15163 result_pipe[i3] = 0;
15164 overflow_pipe[i3] = 1'b0;
15165 underflow_pipe[i3] = 1'b0;
15166 zero_pipe[i3] = 1'b0;
15167 denormal_pipe[i3] = 1'b0;
15168 indefinite_pipe[i3] = 1'b0;
15169 nan_pipe[i3] = 1'b0;
15171 // Check for illegal mode setting
15172 if (WIDTH_MAN_EXP >= 64)
15174 $display("ERROR: The sum of width_exp(%d) and width_man(%d) must be less 64!", width_exp, width_man);
15179 $display("ERROR: width_exp(%d) must be at least 8!", width_exp);
15182 if (width_man < 23)
15184 $display("ERROR: width_man(%d) must be at least 23!", width_man);
15187 if (~((width_exp >= 11) || ((width_exp == 8) && (width_man == 23))))
15189 $display("ERROR: Found width_exp(%d) inside the range of Single Precision. width_exp must be 8 and width_man must be 23 for Single Presicion!", width_exp);
15192 if (~((width_man >= 31) || ((width_exp == 8) && (width_man == 23))))
15194 $display("ERROR: Found width_man(%d) inside the range of Single Precision. width_exp must be 8 and width_man must be 23 for Single Presicion!", width_man);
15197 if (width_exp >= width_man)
15199 $display("ERROR: width_exp(%d) must be less than width_man(%d)!", width_exp, width_man);
15202 if ((pipeline != 5) && (pipeline != 6))
15204 $display("ERROR: The legal value for PIPELINE is 5 or 6!");
15208 if ((reduced_functionality != "NO") && (reduced_functionality != "YES"))
15210 $display("ERROR: reduced_functionality value must be \"YES\" or \"NO\"!");
15214 if (reduced_functionality != "NO")
15216 $display("Info: The Clearbox support is available for reduced functionality Floating Point Multiplier.");
15218 end // INITIALIZATION
15220 // ALWAYS CONSTRUCT BLOCK
15223 always @(dataa or datab)
15224 begin : MULTIPLY_FP
15225 temp_result = {(WIDTH_MAN_EXP + 1){1'b0}};
15226 overflow_bit = 1'b0;
15227 underflow_bit = 1'b0;
15229 denormal_bit = 1'b0;
15230 indefinite_bit = 1'b0;
15232 mant_result = {((2 * width_man) + 2){1'b0}};
15235 // Set the exponential value
15236 exp_dataa = dataa[width_exp + width_man -1:width_man];
15237 exp_datab = datab[width_exp + width_man -1:width_man];
15239 zero_mant_dataa = 1'b1;
15240 // Check whether the mantissa for dataa is zero
15242 for (i4 = 0; i4 <= width_man - 1; i4 = i4 + 1)
15244 if ((dataa[i4]) == 1'b1)
15246 zero_mant_dataa = 1'b0;
15251 zero_mant_datab = 1'b1;
15252 // Check whether the mantissa for datab is zero
15254 for (i4 = 0; i4 <= width_man -1; i4 = i4 + 1)
15256 if ((datab[i4]) == 1'b1)
15258 zero_mant_datab = 1'b0;
15267 // Check whether dataa is special input
15268 if (exp_dataa == 0)
15270 if ((zero_mant_dataa == 1'b1)
15271 || (reduced_functionality != "NO"))
15273 zero_dataa = 1'b1; // dataa is zero
15277 den_dataa = 1'b1; // dataa is denormalized
15280 else if (exp_dataa == (exponential_value(2, width_exp) - 1))
15282 if (zero_mant_dataa == 1'b1)
15284 inf_dataa = 1'b1; // dataa is infinity
15288 nan_dataa = 1'b1; // dataa is Nan
15295 // Check whether datab is special input
15296 if (exp_datab == 0)
15298 if ((zero_mant_datab == 1'b1)
15299 || (reduced_functionality != "NO"))
15301 zero_datab = 1'b1; // datab is zero
15305 den_datab = 1'b1; // datab is denormalized
15308 else if (exp_datab == (exponential_value(2, width_exp) - 1))
15310 if (zero_mant_datab == 1'b1)
15312 inf_datab = 1'b1; // datab is infinity
15316 nan_datab = 1'b1; // datab is Nan
15319 no_multiply = 1'b0;
15320 // Set status flag if special input exists
15321 if (nan_dataa || nan_datab || (inf_dataa && zero_datab) ||
15322 (inf_datab && zero_dataa))
15324 nan_bit = 1'b1; // NaN
15325 for (i4 = width_man - 1; i4 <= WIDTH_MAN_EXP - 1; i4 = i4 + 1)
15327 temp_result[i4] = 1'b1;
15329 no_multiply = 1'b1; // no multiplication is needed.
15331 else if (zero_dataa)
15333 zero_bit = 1'b1; // Zero
15334 temp_result[WIDTH_MAN_EXP : 0] = 0;
15335 no_multiply = 1'b1;
15337 else if (zero_datab)
15339 zero_bit = 1'b1; // Zero
15340 temp_result[WIDTH_MAN_EXP : 0] = 0;
15341 no_multiply = 1'b1;
15343 else if (inf_dataa)
15345 overflow_bit = 1'b1; // Overflow
15346 temp_result[WIDTH_MAN_EXP : 0] = dataa;
15347 no_multiply = 1'b1;
15349 else if (inf_datab)
15351 overflow_bit = 1'b1; // Overflow
15352 temp_result[WIDTH_MAN_EXP : 0] = datab;
15353 no_multiply = 1'b1;
15355 // if multiplication needed
15356 if (no_multiply == 1'b0)
15358 // Perform exponent operation
15359 exp_result = exp_dataa + exp_datab - (exponential_value(2, width_exp -1) -1);
15360 // First operand for multiplication
15361 mant_dataa[width_man : 0] = {1'b1, dataa[width_man -1 : 0]};
15362 // Second operand for multiplication
15363 mant_datab[width_man : 0] = {1'b1, datab[width_man -1 : 0]};
15364 // Multiply the mantissas using add and shift algorithm
15365 for (i4 = 0; i4 <= width_man; i4 = i4 + 1)
15368 if ((mant_dataa[i4]) == 1'b1)
15370 add_bits(mant_datab, mant_result, cout);
15372 mant_result = mant_result >> 1;
15373 mant_result[2*width_man + 1] = cout;
15376 mant_result_msb = mant_result[2*width_man + 1];
15377 // Normalize the Result
15378 if (mant_result_msb == 1'b1)
15380 sticky_bit = mant_result[0]; // Needed for rounding operation.
15381 mant_result = mant_result >> 1;
15382 exp_result = exp_result + 1;
15384 round_bit = mant_result[width_man - 1];
15385 guard_bit = mant_result[width_man];
15386 no_rounding = 1'b0;
15387 // Check whether should perform rounding or not
15388 if (round_bit == 1'b0)
15390 no_rounding = 1'b1; // No rounding is needed
15394 if (reduced_functionality == "NO")
15396 for(i4 = 0; i4 <= width_man - 2; i4 = i4 + 1)
15398 sticky_bit = sticky_bit | mant_result[i4];
15403 sticky_bit = (mant_result[width_man - 2] &
15406 if ((sticky_bit == 1'b0) && (guard_bit == 1'b0))
15408 no_rounding = 1'b1;
15411 // Perform rounding
15412 if (no_rounding == 1'b0)
15415 for(i4 = width_man; i4 <= 2 * width_man + 1; i4 = i4 + 1)
15419 if (mant_result[i4] == 1'b0)
15421 mant_result[i4] = 1'b1;
15426 mant_result[i4] = 1'b0;
15430 // If the mantissa of the result is 10.00.. after rounding, right shift the
15431 // mantissa of the result by 1 bit and increase the exponent of the result by 1.
15432 if (mant_result[(2 * width_man) + 1] == 1'b1)
15434 mant_result = mant_result >> 1;
15435 exp_result = exp_result + 1;
15438 // Normalize the Result
15439 if ((!bit_all_0(mant_result, 0, (2 * width_man) + 1)) &&
15440 (mant_result[2 * width_man] == 1'b0))
15442 while ((mant_result[2 * width_man] == 1'b0) &&
15445 mant_result = mant_result << 1;
15446 exp_result = exp_result - 1;
15449 else if ((exp_result < 0) && (exp_result >= -(2*width_man)))
15451 while(exp_result != 0)
15453 mant_result = mant_result >> 1;
15454 exp_result = exp_result + 1;
15457 // Set status flag "indefinite" if normal * denormal
15458 // (ignore other status port since we dont care the output
15459 if (den_dataa || den_datab)
15461 indefinite_bit = 1'b1; // Indefinite
15463 else if (exp_result >= (exponential_value(2, width_exp) -1))
15465 overflow_bit = 1'b1; // Overflow
15467 else if (exp_result < 0)
15469 underflow_bit = 1'b1; // Underflow
15470 zero_bit = 1'b1; // Zero
15472 else if (exp_result == 0)
15474 underflow_bit = 1'b1; // Underflow
15476 if (bit_all_0(mant_result, width_man + 1, 2 * width_man))
15478 zero_bit = 1'b1; // Zero
15482 denormal_bit = 1'b1; // Denormal
15485 // Get result's mantissa
15486 if (exp_result < 0) // Result underflow
15488 for(i4 = 0; i4 <= width_man - 1; i4 = i4 + 1)
15490 temp_result[i4] = 1'b0;
15493 else if (exp_result == 0) // Denormalized result
15495 if (reduced_functionality == "NO")
15497 temp_result[width_man - 1 : 0] = mant_result[2 * width_man : width_man + 1];
15501 temp_result[width_man - 1 : 0] = 0;
15505 else if (exp_result >= exponential_value(2, width_exp) -1)
15507 temp_result[width_man - 1 : 0] = {width_man{1'b0}};
15509 else // Normalized result
15511 temp_result[width_man - 1 : 0] = mant_result[(2 * width_man - 1) : width_man];
15513 // Get result's exponent
15514 if (exp_result == 0)
15516 for(i4 = width_man; i4 <= WIDTH_MAN_EXP - 1; i4 = i4 + 1)
15518 temp_result[i4] = 1'b0;
15521 else if (exp_result >= (exponential_value(2, width_exp) -1))
15523 for(i4 = width_man; i4 <= WIDTH_MAN_EXP - 1; i4 = i4 + 1)
15525 temp_result[i4] = 1'b1;
15530 // Convert integer to binary bits
15531 for(i4 = width_man; i4 <= WIDTH_MAN_EXP - 1; i4 = i4 + 1)
15533 if ((exp_result % 2) == 1)
15535 temp_result[i4] = 1'b1;
15539 temp_result[i4] = 1'b0;
15541 exp_result = exp_result / 2;
15544 end // end of if (no_multiply == 1'b0)
15545 // Get result's sign bit
15546 temp_result[WIDTH_MAN_EXP] = dataa[WIDTH_MAN_EXP] ^ datab[WIDTH_MAN_EXP];
15550 // Pipelining registers.
15551 always @(posedge clock or posedge aclr)
15552 begin : PIPELINE_REGS
15555 for (i5 = LATENCY; i5 >= 0; i5 = i5 - 1)
15557 result_pipe[i5] <= {WIDTH_MAN_EXP{1'b0}};
15558 overflow_pipe[i5] <= 1'b0;
15559 underflow_pipe[i5] <= 1'b0;
15560 zero_pipe[i5] <= 1'b1;
15561 denormal_pipe[i5] <= 1'b0;
15562 indefinite_pipe[i5] <= 1'b0;
15563 nan_pipe[i5] <= 1'b0;
15565 // clear all the output ports to 1'b0
15567 else if (clk_en == 1'b1)
15569 result_pipe[0] <= temp_result;
15570 overflow_pipe[0] <= overflow_bit;
15571 underflow_pipe[0] <= underflow_bit;
15572 zero_pipe[0] <= zero_bit;
15573 denormal_pipe[0] <= denormal_bit;
15574 indefinite_pipe[0] <= indefinite_bit;
15575 nan_pipe[0] <= nan_bit;
15577 // Create latency for the output result
15578 for(i5=LATENCY; i5 >= 1; i5 = i5 - 1)
15580 result_pipe[i5] <= result_pipe[i5 - 1];
15581 overflow_pipe[i5] <= overflow_pipe[i5 - 1];
15582 underflow_pipe[i5] <= underflow_pipe[i5 - 1];
15583 zero_pipe[i5] <= zero_pipe[i5 - 1];
15584 denormal_pipe[i5] <= denormal_pipe[i5 - 1];
15585 indefinite_pipe[i5] <= indefinite_pipe[i5 - 1];
15586 nan_pipe[i5] <= nan_pipe[i5 - 1];
15589 end // PIPELINE_REGS
15591 assign result = result_pipe[LATENCY];
15592 assign overflow = overflow_pipe[LATENCY];
15593 assign underflow = underflow_pipe[LATENCY];
15594 assign zero = (reduced_functionality == "NO") ? zero_pipe[LATENCY] : 1'b0;
15595 assign denormal = (reduced_functionality == "NO") ? denormal_pipe[LATENCY] : 1'b0;
15596 assign indefinite = (reduced_functionality == "NO") ? indefinite_pipe[LATENCY] : 1'b0;
15597 assign nan = nan_pipe[LATENCY];
15599 endmodule //altfp_mult
15603 //START_MODULE_NAME-------------------------------------------------------------
15605 // Module Name : altsqrt
15607 // Description : Parameterized integer square root megafunction.
15608 // This module computes q[] and remainder so that
15609 // q[]^2 + remainder[] == radical[] (remainder <= 2 * q[])
15610 // It can support the sequential mode(pipeline > 0) or
15611 // combinational mode (pipeline = 0).
15613 // Limitation : The radical is assumed to be unsigned integer.
15615 // Results expected: Square root of the radical and the remainder.
15617 //END_MODULE_NAME---------------------------------------------------------------
15619 // BEGINNING OF MODULE
15620 `timescale 1 ps / 1 ps
15623 radical, // Input port for the radical
15625 ena, // Clock enable port
15626 aclr, // Asynchronous clear port
15627 q, // Output port for returning the square root of the radical.
15628 remainder // Output port for returning the remainder of the square root.
15631 // GLOBAL PARAMETER DECLARATION
15632 parameter q_port_width = 1; // The width of the q port
15633 parameter r_port_width = 1; // The width of the remainder port
15634 parameter width = 1; // The width of the radical
15635 parameter pipeline = 0; // The latency for the output
15636 parameter lpm_hint= "UNUSED";
15637 parameter lpm_type = "altsqrt";
15639 // INPUT PORT DECLARATION
15640 input [width - 1 : 0] radical;
15645 // OUTPUT PORT DECLARATION
15646 output [q_port_width - 1 : 0] q;
15647 output [r_port_width - 1 : 0] remainder;
15649 // INTERNAL REGISTERS DECLARATION
15650 reg[q_port_width - 1 : 0] q_temp;
15651 reg[q_port_width - 1 : 0] q_pipeline[(pipeline +1) : 0];
15652 reg[r_port_width - 1 : 0] r_temp;
15653 reg[r_port_width - 1 : 0] remainder_pipeline[(pipeline +1) : 0];
15655 // INTERNAL TRI DECLARATION
15660 // LOCAL INTEGER DECLARATION
15665 integer q_value_temp;
15666 integer r_value_temp;
15671 // INITIAL CONSTRUCT BLOCK
15674 // Check for illegal mode
15677 $display("width (%d) must be greater than 0.(ERROR)", width);
15683 // ALWAYS CONSTRUCT BLOCK
15685 // Perform square root calculation.
15686 // In general, below are the steps to calculate the square root and the
15689 // Start of with q = 0 and remainder= 0
15690 // For every iteration, do the same thing:
15691 // 1) Shift in the next 2 bits of the radical into the remainder
15692 // Eg. if the radical is b"101100". For the first iteration,
15693 // the remainder will be equal to b"10".
15694 // 2) Compare it to the 4* q + 1
15695 // 3) if the remainder is greater than or equal to 4*q + 1
15696 // remainder = remainder - (4*q + 1)
15701 begin : SQUARE_ROOT
15705 q_index = (width - 1) / 2;
15708 q_temp = {q_port_width{1'b0}};
15709 r_temp = {r_port_width{1'b0}};
15711 // If the number of the bits of the radical is an odd number,
15712 // Then for the first iteration, only the 1st bit will be shifted
15713 // into the remainder.
15714 // Eg. if the radical is b"11111", then the remainder is b"01".
15715 if((width % 2) == 1)
15719 value2 = (radical[index - 2] === 1'b1) ? 1'b1 : 1'b0;
15721 else if (width > 1)
15723 // Otherwise, for the first iteration, the first two bits will be shifted
15724 // into the remainder.
15725 // Eg. if the radical is b"101111", then the remainder is b"10".
15727 value1 = (radical[index - 1] === 1'b1) ? 1'b1 : 1'b0;
15728 value2 = (radical[index - 2] === 1'b1) ? 1'b1 : 1'b0;
15731 // For every iteration
15732 for(index = index - 2; index >= 0; index = index - 2)
15734 // Get the remainder value by shifting in the next 2 bits
15735 // of the radical into the remainder
15736 r_value_temp = (r_value_temp * 4) + (2 * value1) + value2;
15738 // if remainder >= (4*q + 1)
15739 if (r_value_temp >= ((4 * q_value_temp) + 1))
15741 // remainder = remainder - (4*q + 1)
15742 r_value_temp = r_value_temp - (4 * q_value_temp) - 1;
15744 q_value_temp = (2 * q_value_temp) + 1;
15745 // set the q[q_index] = 1
15746 q_temp[q_index] = 1'b1;
15748 else // if remainder < (4*q + 1)
15751 q_value_temp = 2 * q_value_temp;
15752 // set the q[q_index] = 0
15753 q_temp[q_index] = 1'b0;
15756 // if not the last iteration, get the next 2 bits of the radical
15759 value1 = (radical[index - 1] === 1'b1)? 1: 0;
15760 value2 = (radical[index - 2] === 1'b1)? 1: 0;
15763 // Reduce the current index of q by 1
15764 q_index = q_index - 1;
15768 // Get the binary bits of the remainder by converting integer to
15770 r_temp = r_value_temp;
15773 // store the result to a pipeline(to create the latency)
15774 always @(posedge clk or posedge aclr)
15776 if (aclr) // clear the pipeline for result to 0
15778 for (i1 = 0; i1 < (pipeline + 1); i1 = i1 + 1)
15780 q_pipeline[i1] <= 0;
15781 remainder_pipeline[i1] <= 0;
15786 remainder_pipeline[pipe_ptr] <= r_temp;
15787 q_pipeline[pipe_ptr] <= q_temp;
15790 pipe_ptr <= (pipe_ptr + 1) % pipeline;
15794 // CONTINOUS ASSIGNMENT
15795 assign q = (pipeline > 0) ? q_pipeline[pipe_ptr] : q_temp;
15796 assign remainder = (pipeline > 0) ? remainder_pipeline[pipe_ptr] : r_temp;
15798 endmodule //altsqrt
15801 // START MODULE NAME -----------------------------------------------------------
15803 // Module Name : ALTCLKLOCK
15805 // Description : Phase-Locked Loop (PLL) behavioral model. Supports basic
15806 // PLL features such as multiplication and division of input
15807 // clock frequency and phase shift.
15809 // Limitations : Model supports NORMAL operation mode only. External
15810 // feedback mode and zero-delay-buffer mode are not simulated.
15811 // Applicable to APEX, Mercury and FLEX10KE device families
15814 // Expected results : Up to 4 clock outputs (clock0, clock1, clock2, clock_ext).
15815 // clock2 and clock_ext are for Mercury devices only.
15816 // locked output indicates when PLL locks.
15818 //END MODULE NAME --------------------------------------------------------------
15820 `timescale 1 ps / 1 ps
15822 // MODULE DECLARATION
15823 module altclklock (
15824 inclock, // input reference clock
15825 inclocken, // PLL enable signal
15826 fbin, // feedback input for the PLL
15827 clock0, // output clock 0
15828 clock1, // output clock 1
15829 clock2, // output clock 2 (for Mercury only)
15830 clock_ext, // external output clock (for Mercury only)
15831 locked // PLL lock signal
15834 // GLOBAL PARAMETER DECLARATION
15835 parameter inclock_period = 10000; // units in ps
15836 parameter inclock_settings = "UNUSED";
15837 parameter valid_lock_cycles = 5;
15838 parameter invalid_lock_cycles = 5;
15839 parameter valid_lock_multiplier = 5;
15840 parameter invalid_lock_multiplier = 5;
15841 parameter operation_mode = "NORMAL";
15842 parameter clock0_boost = 1;
15843 parameter clock0_divide = 1;
15844 parameter clock0_settings = "UNUSED";
15845 parameter clock0_time_delay = "0";
15846 parameter clock1_boost = 1;
15847 parameter clock1_divide = 1;
15848 parameter clock1_settings = "UNUSED";
15849 parameter clock1_time_delay = "0";
15850 parameter clock2_boost = 1;
15851 parameter clock2_divide = 1;
15852 parameter clock2_settings = "UNUSED";
15853 parameter clock2_time_delay = "0";
15854 parameter clock_ext_boost = 1;
15855 parameter clock_ext_divide = 1;
15856 parameter clock_ext_settings = "UNUSED";
15857 parameter clock_ext_time_delay = "0";
15858 parameter outclock_phase_shift = 0; // units in ps
15859 parameter intended_device_family = "APEX20KE";
15860 parameter lpm_type = "altclklock";
15861 parameter lpm_hint = "UNUSED";
15863 // INPUT PORT DECLARATION
15868 // OUTPUT PORT DECLARATION
15875 // INTERNAL VARIABLE/REGISTER DECLARATION
15887 reg clk_last_value;
15890 reg [1:0] next_clk_check;
15894 real pll_last_rising_edge;
15895 real pll_last_falling_edge;
15896 real actual_clk_cycle;
15897 real expected_clk_cycle;
15898 real pll_duty_cycle;
15900 real expected_next_clk_edge;
15901 integer pll_rising_edge_count;
15902 integer stop_lock_count;
15903 integer start_lock_count;
15904 integer clk_per_tolerance;
15906 time clk0_phase_delay;
15907 time clk1_phase_delay;
15908 time clk2_phase_delay;
15909 time extclk_phase_delay;
15911 ALTERA_DEVICE_FAMILIES dev ();
15913 // variables for clock synchronizing
15914 time last_synchronizing_rising_edge_for_clk0;
15915 time last_synchronizing_rising_edge_for_clk1;
15916 time last_synchronizing_rising_edge_for_clk2;
15917 time last_synchronizing_rising_edge_for_extclk;
15918 time clk0_synchronizing_period;
15919 time clk1_synchronizing_period;
15920 time clk2_synchronizing_period;
15921 time extclk_synchronizing_period;
15922 integer input_cycles_per_clk0;
15923 integer input_cycles_per_clk1;
15924 integer input_cycles_per_clk2;
15925 integer input_cycles_per_extclk;
15926 integer clk0_cycles_per_sync_period;
15927 integer clk1_cycles_per_sync_period;
15928 integer clk2_cycles_per_sync_period;
15929 integer extclk_cycles_per_sync_period;
15930 integer input_cycle_count_to_sync0;
15931 integer input_cycle_count_to_sync1;
15932 integer input_cycle_count_to_sync2;
15933 integer input_cycle_count_to_sync_extclk;
15935 // variables for shedule_clk0-2, clk_ext
15939 reg schedule_extclk;
15943 reg output_value_ext;
15947 time sched_time_ext;
15955 integer tmp_rem_ext;
15959 integer clk_cnt_ext;
15968 integer cycle_to_adjust0;
15969 integer cycle_to_adjust1;
15970 integer cycle_to_adjust2;
15971 integer cycle_to_adjust_ext;
15983 time high_time_ext;
15989 // Default inclocken and fbin ports to 1 if unused
15990 tri1 inclocken_int;
15993 assign inclocken_int = inclocken;
15994 assign fbin_int = fbin;
15997 // function time_delay - converts time_delay in string format to integer, and
15998 // add result to outclock_phase_shift
16000 function time time_delay;
16003 reg [8*16:1] reg_s;
16007 integer outclock_phase_shift_adj;
16011 // initialize variables
16013 outclock_phase_shift_adj = 0;
16016 for (m = 1; m <= 16; m = m + 1)
16018 tmp = reg_s[128:121];
16019 digit = tmp & 8'b00001111;
16020 reg_s = reg_s << 8;
16021 // Accumulate ascii digits 0-9 only.
16022 if ((tmp >= 48) && (tmp <= 57))
16023 outclock_phase_shift_adj = outclock_phase_shift_adj * 10 + digit;
16025 sign = -1; // Found a '-' character, i.e. number is negative.
16028 // add outclock_phase_shift to time delay
16029 outclock_phase_shift_adj = (sign*outclock_phase_shift_adj) + outclock_phase_shift;
16031 // adjust phase shift so that its value is between 0 and 1 full
16033 while (outclock_phase_shift_adj < 0)
16034 outclock_phase_shift_adj = outclock_phase_shift_adj + inclock_period;
16035 while (outclock_phase_shift_adj >= inclock_period)
16036 outclock_phase_shift_adj = outclock_phase_shift_adj - inclock_period;
16039 time_delay = outclock_phase_shift_adj;
16047 // check for invalid parameters
16048 if (inclock_period <= 0)
16050 $display("ERROR: The period of the input clock (inclock_period) must be greater than 0");
16054 if ((clock0_boost <= 0) || (clock0_divide <= 0)
16055 || (clock1_boost <= 0) || (clock1_divide <= 0)
16056 || (clock2_boost <= 0) || (clock2_divide <= 0)
16057 || (clock_ext_boost <= 0) || (clock_ext_divide <= 0))
16059 if ((clock0_boost <= 0) || (clock0_divide <= 0))
16061 $display("ERROR: The multiplication and division factors for clock0 must be greater than 0.");
16064 if ((clock1_boost <= 0) || (clock1_divide <= 0))
16066 $display("ERROR: The multiplication and division factors for clock1 must be greater than 0.");
16069 if ((clock2_boost <= 0) || (clock2_divide <= 0))
16071 $display("ERROR: The multiplication and division factors for clock2 must be greater than 0.");
16074 if ((clock_ext_boost <= 0) || (clock_ext_divide <= 0))
16076 $display("ERROR: The multiplication and division factors for clock_ext must be greater than 0.");
16081 if ((!dev.IS_FAMILY_FLEX10KE(intended_device_family))
16082 && (!dev.IS_FAMILY_ACEX1K(intended_device_family))
16083 && (!dev.IS_FAMILY_APEX20K(intended_device_family))
16084 && (!dev.IS_FAMILY_APEX20KE(intended_device_family))
16085 && (!dev.IS_FAMILY_APEX20KC(intended_device_family))
16086 && (!dev.IS_FAMILY_EXCALIBUR_ARM(intended_device_family))
16087 && (!dev.IS_FAMILY_APEXII(intended_device_family))
16088 && (!dev.IS_FAMILY_MERCURY(intended_device_family)))
16090 $display("WARNING: Device family specified by the intended_device_family parameter, %s, may not be supported by altclklock", intended_device_family);
16093 stop_lock_count = 0;
16096 // clock synchronizing variables
16097 last_synchronizing_rising_edge_for_clk0 = 0;
16098 last_synchronizing_rising_edge_for_clk1 = 0;
16099 last_synchronizing_rising_edge_for_clk2 = 0;
16100 last_synchronizing_rising_edge_for_extclk = 0;
16101 clk0_synchronizing_period = 0;
16102 clk1_synchronizing_period = 0;
16103 clk2_synchronizing_period = 0;
16104 extclk_synchronizing_period = 0;
16105 input_cycles_per_clk0 = clock0_divide;
16106 input_cycles_per_clk1 = clock1_divide;
16107 input_cycles_per_clk2 = clock2_divide;
16108 input_cycles_per_extclk = clock_ext_divide;
16109 clk0_cycles_per_sync_period = clock0_boost;
16110 clk1_cycles_per_sync_period = clock1_boost;
16111 clk2_cycles_per_sync_period = clock2_boost;
16112 extclk_cycles_per_sync_period = clock_ext_boost;
16113 input_cycle_count_to_sync0 = 0;
16114 input_cycle_count_to_sync1 = 0;
16115 input_cycle_count_to_sync2 = 0;
16116 input_cycle_count_to_sync_extclk = 0;
16121 cycle_to_adjust0 = 0;
16122 cycle_to_adjust1 = 0;
16123 cycle_to_adjust2 = 0;
16124 cycle_to_adjust_ext = 0;
16126 if ((clock0_boost % clock0_divide) == 0)
16128 clk0_cycles_per_sync_period = clock0_boost / clock0_divide;
16129 input_cycles_per_clk0 = 1;
16132 if ((clock1_boost % clock1_divide) == 0)
16134 clk1_cycles_per_sync_period = clock1_boost / clock1_divide;
16135 input_cycles_per_clk1 = 1;
16138 if ((clock2_boost % clock2_divide) == 0)
16140 clk2_cycles_per_sync_period = clock2_boost / clock2_divide;
16141 input_cycles_per_clk2 = 1;
16144 if ((clock_ext_boost % clock_ext_divide) == 0)
16146 extclk_cycles_per_sync_period = clock_ext_boost / clock_ext_divide;
16147 input_cycles_per_extclk = 1;
16150 // convert time delays from string to integer
16151 clk0_phase_delay = time_delay(clock0_time_delay);
16152 clk1_phase_delay = time_delay(clock1_time_delay);
16153 clk2_phase_delay = time_delay(clock2_time_delay);
16154 extclk_phase_delay = time_delay(clock_ext_time_delay);
16156 // 2.5% tolerance of input clock period variation
16157 if(dev.IS_FAMILY_MERCURY(intended_device_family))
16158 clk_per_tolerance = 0.025 * inclock_period;
16160 clk_per_tolerance = 0.1 * inclock_period;
16163 always @(next_clk_check)
16165 if (next_clk_check == 1)
16167 if ((clk_check === 1'b1) || (clk_check === 1'b0))
16168 #((inclk_period+clk_per_tolerance)/2) clk_check = ~clk_check;
16170 #((inclk_period+clk_per_tolerance)/2) clk_check = 1'b1;
16172 else if (next_clk_check == 2)
16174 if ((clk_check === 1'b1) || (clk_check === 1'b0))
16175 #(expected_next_clk_edge - $realtime) clk_check = ~clk_check;
16177 #(expected_next_clk_edge - $realtime) clk_check = 1'b1;
16179 next_clk_check = 0;
16182 always @(inclock or inclocken_int or clk_check)
16187 start_lock_count = 0;
16188 pll_rising_edge_count = 0;
16189 pll_last_rising_edge = 0;
16190 pll_last_falling_edge = 0;
16195 if (inclocken_int == 1'b0)
16198 pll_rising_edge_count = 0;
16200 else if ((inclock == 1'b1) && (clk_last_value !== inclock))
16202 if (pll_lock === 1)
16203 next_clk_check = 1;
16205 if (pll_rising_edge_count == 0) // this is first rising edge
16207 inclk_period = inclock_period;
16208 pll_duty_cycle = inclk_period/2;
16211 else if (pll_rising_edge_count == 1) // this is second rising edge
16213 expected_clk_cycle = inclk_period;
16214 actual_clk_cycle = $realtime - pll_last_rising_edge;
16215 if (actual_clk_cycle < (expected_clk_cycle - clk_per_tolerance) ||
16216 actual_clk_cycle > (expected_clk_cycle + clk_per_tolerance))
16218 $display($realtime, "ps Warning: Inclock_Period Violation");
16220 if (locked == 1'b1)
16222 stop_lock_count = stop_lock_count + 1;
16223 if ((locked == 1'b1) && (stop_lock_count == invalid_lock_cycles))
16226 $display ($realtime, "ps Warning: altclklock out of lock.");
16228 if(dev.IS_FAMILY_APEX20KE(intended_device_family) || dev.IS_FAMILY_APEX20KC(intended_device_family) || dev.IS_FAMILY_EXCALIBUR_ARM(intended_device_family))
16229 start_lock_count = 0;
16231 start_lock_count = 1;
16233 stop_lock_count = 0;
16241 start_lock_count = 1;
16246 if (($realtime - pll_last_falling_edge) < (pll_duty_cycle - clk_per_tolerance/2) ||
16247 ($realtime - pll_last_falling_edge) > (pll_duty_cycle + clk_per_tolerance/2))
16249 $display($realtime, "ps Warning: Duty Cycle Violation");
16256 else if (($realtime - pll_last_rising_edge) < (expected_clk_cycle - clk_per_tolerance) ||
16257 ($realtime - pll_last_rising_edge) > (expected_clk_cycle + clk_per_tolerance))
16259 $display($realtime, "ps Warning: Cycle Violation");
16261 if (locked == 1'b1)
16263 stop_lock_count = stop_lock_count + 1;
16264 if (stop_lock_count == invalid_lock_cycles)
16267 $display ($realtime, "ps Warning: altclklock out of lock.");
16269 if(dev.IS_FAMILY_APEX20KE(intended_device_family) || dev.IS_FAMILY_APEX20KC(intended_device_family) || dev.IS_FAMILY_EXCALIBUR_ARM(intended_device_family))
16270 start_lock_count = 0;
16272 start_lock_count = 1;
16274 stop_lock_count = 0;
16283 start_lock_count = 1;
16289 actual_clk_cycle = $realtime - pll_last_rising_edge;
16291 pll_last_rising_edge = $realtime;
16292 pll_rising_edge_count = pll_rising_edge_count + 1;
16295 if (pll_lock == 1'b1)
16297 input_cycle_count_to_sync0 = input_cycle_count_to_sync0 + 1;
16298 if (input_cycle_count_to_sync0 == input_cycles_per_clk0)
16300 clk0_synchronizing_period = $realtime - last_synchronizing_rising_edge_for_clk0;
16301 last_synchronizing_rising_edge_for_clk0 = $realtime;
16303 input_cycle_count_to_sync0 = 0;
16305 input_cycle_count_to_sync1 = input_cycle_count_to_sync1 + 1;
16306 if (input_cycle_count_to_sync1 == input_cycles_per_clk1)
16308 clk1_synchronizing_period = $realtime - last_synchronizing_rising_edge_for_clk1;
16309 last_synchronizing_rising_edge_for_clk1 = $realtime;
16311 input_cycle_count_to_sync1 = 0;
16313 input_cycle_count_to_sync2 = input_cycle_count_to_sync2 + 1;
16314 if (input_cycle_count_to_sync2 == input_cycles_per_clk2)
16316 clk2_synchronizing_period = $realtime - last_synchronizing_rising_edge_for_clk2;
16317 last_synchronizing_rising_edge_for_clk2 = $realtime;
16319 input_cycle_count_to_sync2 = 0;
16321 input_cycle_count_to_sync_extclk = input_cycle_count_to_sync_extclk + 1;
16322 if (input_cycle_count_to_sync_extclk == input_cycles_per_extclk)
16324 extclk_synchronizing_period = $realtime - last_synchronizing_rising_edge_for_extclk;
16325 last_synchronizing_rising_edge_for_extclk = $realtime;
16326 schedule_extclk = 1;
16327 input_cycle_count_to_sync_extclk = 0;
16332 if (!dev.IS_FAMILY_APEXII(intended_device_family) || (pll_rising_edge_count-1 > 0))
16334 start_lock_count = start_lock_count + 1;
16335 if (start_lock_count >= valid_lock_cycles)
16338 input_cycle_count_to_sync0 = 0;
16339 input_cycle_count_to_sync1 = 0;
16340 input_cycle_count_to_sync2 = 0;
16341 input_cycle_count_to_sync_extclk = 0;
16342 clk0_synchronizing_period = actual_clk_cycle * input_cycles_per_clk0;
16343 clk1_synchronizing_period = actual_clk_cycle * input_cycles_per_clk1;
16344 clk2_synchronizing_period = actual_clk_cycle * input_cycles_per_clk2;
16345 extclk_synchronizing_period = actual_clk_cycle * input_cycles_per_extclk;
16346 last_synchronizing_rising_edge_for_clk0 = $realtime;
16347 last_synchronizing_rising_edge_for_clk1 = $realtime;
16348 last_synchronizing_rising_edge_for_clk2 = $realtime;
16349 last_synchronizing_rising_edge_for_extclk = $realtime;
16353 schedule_extclk = 1;
16359 if(dev.IS_FAMILY_APEXII(intended_device_family))
16360 start_lock_count = 0;
16362 start_lock_count = 1;
16364 else if ((inclock == 1'b0) && (clk_last_value !== inclock))
16368 next_clk_check = 1;
16369 if (($realtime - pll_last_rising_edge) < (pll_duty_cycle - clk_per_tolerance/2) ||
16370 ($realtime - pll_last_rising_edge) > (pll_duty_cycle + clk_per_tolerance/2))
16372 $display($realtime, "ps Warning: Duty Cycle Violation");
16374 if (locked == 1'b1)
16376 stop_lock_count = stop_lock_count + 1;
16377 if (stop_lock_count == invalid_lock_cycles)
16380 $display ($realtime, "ps Warning: altclklock out of lock.");
16382 if(dev.IS_FAMILY_APEX20KE(intended_device_family) || dev.IS_FAMILY_APEX20KC(intended_device_family) || dev.IS_FAMILY_EXCALIBUR_ARM(intended_device_family))
16383 start_lock_count = 0;
16385 start_lock_count = 1;
16387 stop_lock_count = 0;
16398 else if (!dev.IS_FAMILY_APEXII(intended_device_family) || (pll_rising_edge_count > 0))
16399 start_lock_count = start_lock_count + 1;
16400 pll_last_falling_edge = $realtime;
16402 else if (pll_lock == 1)
16404 if (inclock == 1'b1)
16405 expected_next_clk_edge = pll_last_rising_edge + (inclk_period+clk_per_tolerance)/2;
16406 else if (inclock == 'b0)
16407 expected_next_clk_edge = pll_last_falling_edge + (inclk_period+clk_per_tolerance)/2;
16409 expected_next_clk_edge = 0;
16411 if ($realtime < expected_next_clk_edge)
16412 next_clk_check = 2;
16413 else if ($realtime == expected_next_clk_edge)
16414 next_clk_check = 1;
16417 $display($realtime, "ps Warning: Inclock_Period Violation");
16420 if (locked == 1'b1)
16422 stop_lock_count = stop_lock_count + 1;
16423 expected_next_clk_edge = $realtime + (inclk_period/2);
16424 if (stop_lock_count == invalid_lock_cycles)
16427 $display ($realtime, "ps Warning: altclklock out of lock.");
16429 if(dev.IS_FAMILY_APEX20KE(intended_device_family) || dev.IS_FAMILY_APEX20KC(intended_device_family) || dev.IS_FAMILY_EXCALIBUR_ARM(intended_device_family))
16430 start_lock_count = 0;
16432 start_lock_count = 1;
16434 stop_lock_count = 0;
16441 next_clk_check = 2;
16445 clk_last_value = inclock;
16449 always @(posedge schedule_clk0)
16451 // initialise variables
16453 cycle_to_adjust0 = 0;
16454 output_value0 = 1'b1;
16456 rem0 = clk0_synchronizing_period % clk0_cycles_per_sync_period;
16457 ori_per0 = clk0_synchronizing_period / clk0_cycles_per_sync_period;
16459 // schedule <clk0_cycles_per_sync_period> number of clock0 cycles in this
16460 // loop - in order to synchronize the output clock always to the input clock
16461 // to get rid of clock drift for cases where the input clock period is
16462 // not evenly divisible
16463 for (clk_cnt0 = 1; clk_cnt0 <= clk0_cycles_per_sync_period;
16464 clk_cnt0 = clk_cnt0 + 1)
16466 tmp_per0 = ori_per0;
16467 if ((rem0 != 0) && (inc0 <= rem0))
16469 tmp_rem0 = (clk0_cycles_per_sync_period * inc0) % rem0;
16470 cycle_to_adjust0 = (clk0_cycles_per_sync_period * inc0) / rem0;
16472 cycle_to_adjust0 = cycle_to_adjust0 + 1;
16475 // if this cycle is the one to adjust the output clock period, then
16476 // increment the period by 1 unit
16477 if (cycle_to_adjust0 == clk_cnt0)
16479 tmp_per0 = tmp_per0 + 1;
16483 // adjust the high and low cycle period
16484 high_time0 = tmp_per0 / 2;
16485 if ((tmp_per0 % 2) != 0)
16486 high_time0 = high_time0 + 1;
16488 low_time0 = tmp_per0 - high_time0;
16490 // schedule the high and low cycle of 1 output clock period
16491 for (cyc0 = 0; cyc0 <= 1; cyc0 = cyc0 + 1)
16493 // Avoid glitch in vcs when high_time0 and low_time0 is 0
16494 // (due to clk0_synchronizing_period is 0)
16495 if (clk0_synchronizing_period != 0)
16496 clk0_tmp = #(sched_time0) output_value0;
16498 clk0_tmp = #(sched_time0) 1'b0;
16499 output_value0 = ~output_value0;
16500 if (output_value0 == 1'b0)
16502 sched_time0 = high_time0;
16504 else if (output_value0 == 1'b1)
16506 sched_time0 = low_time0;
16511 // drop the schedule_clk0 to 0 so that the "always@(inclock)" block can
16512 // trigger this block again when the correct time comes
16513 schedule_clk0 = #1 1'b0;
16518 if (clk0_phase_delay == 0)
16519 clock0 <= clk0_tmp;
16521 clock0 <= #(clk0_phase_delay) clk0_tmp;
16525 always @(posedge schedule_clk1)
16527 // initialize variables
16529 cycle_to_adjust1 = 0;
16530 output_value1 = 1'b1;
16532 rem1 = clk1_synchronizing_period % clk1_cycles_per_sync_period;
16533 ori_per1 = clk1_synchronizing_period / clk1_cycles_per_sync_period;
16535 // schedule <clk1_cycles_per_sync_period> number of clock1 cycles in this
16536 // loop - in order to synchronize the output clock always to the input clock,
16537 // to get rid of clock drift for cases where the input clock period is
16538 // not evenly divisible
16539 for (clk_cnt1 = 1; clk_cnt1 <= clk1_cycles_per_sync_period;
16540 clk_cnt1 = clk_cnt1 + 1)
16542 tmp_per1 = ori_per1;
16543 if ((rem1 != 0) && (inc1 <= rem1))
16545 tmp_rem1 = (clk1_cycles_per_sync_period * inc1) % rem1;
16546 cycle_to_adjust1 = (clk1_cycles_per_sync_period * inc1) / rem1;
16548 cycle_to_adjust1 = cycle_to_adjust1 + 1;
16551 // if this cycle is the one to adjust the output clock period, then
16552 // increment the period by 1 unit
16553 if (cycle_to_adjust1 == clk_cnt1)
16555 tmp_per1 = tmp_per1 + 1;
16559 // adjust the high and low cycle period
16560 high_time1 = tmp_per1 / 2;
16561 if ((tmp_per1 % 2) != 0)
16562 high_time1 = high_time1 + 1;
16564 low_time1 = tmp_per1 - high_time1;
16566 // schedule the high and low cycle of 1 output clock period
16567 for (cyc1 = 0; cyc1 <= 1; cyc1 = cyc1 + 1)
16569 // Avoid glitch in vcs when high_time1 and low_time1 is 0
16570 // (due to clk1_synchronizing_period is 0)
16571 if (clk1_synchronizing_period != 0)
16572 clk1_tmp = #(sched_time1) output_value1;
16574 clk1_tmp = #(sched_time1) 1'b0;
16575 output_value1 = ~output_value1;
16576 if (output_value1 == 1'b0)
16577 sched_time1 = high_time1;
16578 else if (output_value1 == 1'b1)
16579 sched_time1 = low_time1;
16582 // drop the schedule_clk1 to 0 so that the "always@(inclock)" block can
16583 // trigger this block again when the correct time comes
16584 schedule_clk1 = #1 1'b0;
16589 if (clk1_phase_delay == 0)
16590 clock1 <= clk1_tmp;
16592 clock1 <= #(clk1_phase_delay) clk1_tmp;
16596 always @(posedge schedule_clk2)
16598 // clock2 is only available for Mercury
16599 if (dev.IS_FAMILY_MERCURY(intended_device_family))
16601 // initialize variables
16603 cycle_to_adjust2 = 0;
16604 output_value2 = 1'b1;
16606 rem2 = clk2_synchronizing_period % clk2_cycles_per_sync_period;
16607 ori_per2 = clk2_synchronizing_period / clk2_cycles_per_sync_period;
16609 // schedule <clk2_cycles_per_sync_period> number of clock2 cycles in this
16610 // loop - in order to synchronize the output clock always to the input clock,
16611 // to get rid of clock drift for cases where the input clock period is
16612 // not evenly divisible
16613 for (clk_cnt2 = 1; clk_cnt2 <= clk2_cycles_per_sync_period;
16614 clk_cnt2 = clk_cnt2 + 1)
16616 tmp_per2 = ori_per2;
16617 if ((rem2 != 0) && (inc2 <= rem2))
16619 tmp_rem2 = (clk2_cycles_per_sync_period * inc2) % rem2;
16620 cycle_to_adjust2 = (clk2_cycles_per_sync_period * inc2) / rem2;
16622 cycle_to_adjust2 = cycle_to_adjust2 + 1;
16625 // if this cycle is the one to adjust the output clock period, then
16626 // increment the period by 1 unit
16627 if (cycle_to_adjust2 == clk_cnt2)
16629 tmp_per2 = tmp_per2 + 1;
16633 // adjust the high and low cycle period
16634 high_time2 = tmp_per2 / 2;
16635 if ((tmp_per2 % 2) != 0)
16636 high_time2 = high_time2 + 1;
16638 low_time2 = tmp_per2 - high_time2;
16640 // schedule the high and low cycle of 1 output clock period
16641 for (cyc2 = 0; cyc2 <= 1; cyc2 = cyc2 + 1)
16643 // Avoid glitch in vcs when high_time2 and low_time2 is 0
16644 // (due to clk2_synchronizing_period is 0)
16645 if (clk2_synchronizing_period != 0)
16646 clk2_tmp = #(sched_time2) output_value2;
16648 clk2_tmp = #(sched_time2) 1'b0;
16649 output_value2 = ~output_value2;
16650 if (output_value2 == 1'b0)
16651 sched_time2 = high_time2;
16652 else if (output_value2 == 1'b1)
16653 sched_time2 = low_time2;
16656 // drop the schedule_clk2 to 0 so that the "always@(inclock)" block can
16657 // trigger this block again when the correct time comes
16658 schedule_clk2 = #1 1'b0;
16664 if (clk2_phase_delay == 0)
16665 clock2 <= clk2_tmp;
16667 clock2 <= #(clk2_phase_delay) clk2_tmp;
16670 // clock_ext output
16671 always @(posedge schedule_extclk)
16673 // clock_ext is only available for Mercury
16674 if (dev.IS_FAMILY_MERCURY(intended_device_family))
16676 // initialize variables
16678 cycle_to_adjust_ext = 0;
16679 output_value_ext = 1'b1;
16680 sched_time_ext = 0;
16681 rem_ext = extclk_synchronizing_period % extclk_cycles_per_sync_period;
16682 ori_per_ext = extclk_synchronizing_period/extclk_cycles_per_sync_period;
16684 // schedule <extclk_cycles_per_sync_period> number of clock_ext cycles in this
16685 // loop - in order to synchronize the output clock always to the input clock,
16686 // to get rid of clock drift for cases where the input clock period is
16687 // not evenly divisible
16688 for (clk_cnt_ext = 1; clk_cnt_ext <= extclk_cycles_per_sync_period;
16689 clk_cnt_ext = clk_cnt_ext + 1)
16691 tmp_per_ext = ori_per_ext;
16692 if ((rem_ext != 0) && (inc_ext <= rem_ext))
16694 tmp_rem_ext = (extclk_cycles_per_sync_period * inc_ext) % rem_ext;
16695 cycle_to_adjust_ext = (extclk_cycles_per_sync_period * inc_ext) / rem_ext;
16696 if (tmp_rem_ext != 0)
16697 cycle_to_adjust_ext = cycle_to_adjust_ext + 1;
16700 // if this cycle is the one to adjust the output clock period, then
16701 // increment the period by 1 unit
16702 if (cycle_to_adjust_ext == clk_cnt_ext)
16704 tmp_per_ext = tmp_per_ext + 1;
16705 inc_ext = inc_ext + 1;
16708 // adjust the high and low cycle period
16709 high_time_ext = tmp_per_ext/2;
16710 if ((tmp_per_ext % 2) != 0)
16711 high_time_ext = high_time_ext + 1;
16713 low_time_ext = tmp_per_ext - high_time_ext;
16715 // schedule the high and low cycle of 1 output clock period
16716 for (cyc_ext = 0; cyc_ext <= 1; cyc_ext = cyc_ext + 1)
16718 // Avoid glitch in vcs when high_time_ext and low_time_ext is 0
16719 // (due to extclk_synchronizing_period is 0)
16720 if (extclk_synchronizing_period != 0)
16721 extclk_tmp = #(sched_time_ext) output_value_ext;
16723 extclk_tmp = #(sched_time_ext) 1'b0;
16724 output_value_ext = ~output_value_ext;
16725 if (output_value_ext == 1'b0)
16726 sched_time_ext = high_time_ext;
16727 else if (output_value_ext == 1'b1)
16728 sched_time_ext = low_time_ext;
16731 // drop the schedule_extclk to 0 so that the "always@(inclock)" block
16732 // can trigger this block again when the correct time comes
16733 schedule_extclk = #1 1'b0;
16737 always @(extclk_tmp)
16739 if (extclk_phase_delay == 0)
16740 clock_ext <= extclk_tmp;
16742 clock_ext <= #(extclk_phase_delay) extclk_tmp;
16745 // ACCELERATE OUTPUTS
16746 buf (locked, pll_lock);
16748 endmodule // altclklock
16749 // END OF MODULE ALTCLKLOCK
16751 // START MODULE NAME -----------------------------------------------------------
16753 // Module Name : ALTDDIO_IN
16755 // Description : Double Data Rate (DDR) input behavioural model. Receives
16756 // data on both edges of the reference clock.
16758 // Limitations : Not available for FLEX, MAX, APEX20K and APEX20KE device
16761 // Expected results : Data sampled from the datain port at the rising edge of
16762 // the reference clock (dataout_h) and at the falling edge of
16763 // the reference clock (dataout_l).
16765 //END MODULE NAME --------------------------------------------------------------
16767 `timescale 1 ps / 1 ps
16769 // MODULE DECLARATION
16770 module altddio_in (
16771 datain, // required port, DDR input data
16772 inclock, // required port, input reference clock to sample data by
16773 inclocken, // enable data clock
16774 aset, // asynchronous set
16775 aclr, // asynchronous clear
16776 dataout_h, // data sampled at the rising edge of inclock
16777 dataout_l // data sampled at the falling edge of inclock
16780 // GLOBAL PARAMETER DECLARATION
16781 parameter width = 1; // required parameter
16782 parameter power_up_high = "OFF";
16783 parameter invert_input_clocks = "OFF";
16784 parameter intended_device_family = "MERCURY";
16785 parameter lpm_type = "altddio_in";
16786 parameter lpm_hint = "UNUSED";
16788 // INPUT PORT DECLARATION
16789 input [width-1:0] datain;
16795 // OUTPUT PORT DECLARATION
16796 output [width-1:0] dataout_h;
16797 output [width-1:0] dataout_l;
16799 // REGISTER AND VARIABLE DECLARATION
16800 reg [width-1:0] dataout_h_tmp;
16801 reg [width-1:0] dataout_l_tmp;
16802 reg [width-1:0] datain_latched;
16804 ALTERA_DEVICE_FAMILIES dev ();
16807 tri0 aset; // default aset to 0
16808 tri0 aclr; // default aclr to 0
16809 tri1 inclocken; // default inclocken to 1
16815 // Begin of parameter checking
16818 $display("ERROR: The width parameter must be greater than 0");
16822 if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
16824 $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
16828 if (!(dev.IS_FAMILY_MERCURY(intended_device_family) ||
16829 dev.IS_FAMILY_APEXII(intended_device_family) ||
16830 dev.IS_FAMILY_STRATIX(intended_device_family) ||
16831 dev.IS_FAMILY_STRATIXGX(intended_device_family) ||
16832 dev.IS_FAMILY_CYCLONE(intended_device_family) ||
16833 dev.FEATURE_FAMILY_STRATIXII(intended_device_family) ||
16834 dev.IS_FAMILY_HARDCOPYSTRATIX(intended_device_family) ||
16835 dev.IS_FAMILY_CYCLONEII(intended_device_family)))
16837 $display("ERROR: Megafunction altddio_out is not supported in %s.", intended_device_family);
16840 // End of parameter checking
16842 // if power_up_high parameter is turned on, registers power up
16843 // to '1', otherwise '0'
16844 dataout_h_tmp = (power_up_high == "ON") ? {width{1'b1}} : {width{1'b0}};
16845 dataout_l_tmp = (power_up_high == "ON") ? {width{1'b1}} : {width{1'b0}};
16846 datain_latched = (power_up_high == "ON") ? {width{1'b1}} : {width{1'b0}};
16849 // input reference clock, sample data
16850 always @ (posedge inclock or posedge aclr or posedge aset)
16854 dataout_h_tmp <= {width{1'b0}};
16855 dataout_l_tmp <= {width{1'b0}};
16859 dataout_h_tmp <= {width{1'b1}};
16860 dataout_l_tmp <= {width{1'b1}};
16862 // if not being set or cleared
16863 else if (inclocken == 1'b1)
16865 if (invert_input_clocks == "ON")
16866 datain_latched <= datain;
16869 dataout_h_tmp <= datain;
16870 dataout_l_tmp <= datain_latched;
16875 always @ (negedge inclock or posedge aclr or posedge aset)
16879 datain_latched <= {width{1'b0}};
16883 datain_latched <= {width{1'b1}};
16885 // if not being set or cleared
16888 if (dev.IS_FAMILY_APEXII(intended_device_family) ||
16889 dev.IS_FAMILY_STRATIXGX(intended_device_family) ||
16890 dev.IS_FAMILY_CYCLONE(intended_device_family) ||
16891 dev.IS_FAMILY_STRATIX(intended_device_family) ||
16892 dev.FEATURE_FAMILY_STRATIXII(intended_device_family) ||
16893 dev.IS_FAMILY_HARDCOPYSTRATIX(intended_device_family) ||
16894 dev.IS_FAMILY_CYCLONEII(intended_device_family))
16896 if (inclocken == 1'b1)
16897 if (invert_input_clocks == "ON")
16899 dataout_h_tmp <= datain;
16900 dataout_l_tmp <= datain_latched;
16903 datain_latched <= datain;
16906 else if (dev.IS_FAMILY_MERCURY(intended_device_family))
16908 if (invert_input_clocks == "ON")
16910 dataout_h_tmp <= datain;
16911 dataout_l_tmp <= datain_latched;
16914 datain_latched <= datain;
16918 if (invert_input_clocks == "ON")
16920 dataout_h_tmp <= datain;
16921 dataout_l_tmp <= datain_latched;
16924 datain_latched <= datain;
16929 // assign registers to output ports
16930 assign dataout_l = dataout_l_tmp;
16931 assign dataout_h = dataout_h_tmp;
16933 endmodule // altddio_in
16934 // END MODULE ALTDDIO_IN
16936 // START MODULE NAME -----------------------------------------------------------
16938 // Module Name : ALTDDIO_OUT
16940 // Description : Double Data Rate (DDR) output behavioural model.
16941 // Transmits data on both edges of the reference clock.
16943 // Limitations : Not available for FLEX, MAX, APEX20K and APEX20KE device
16946 // Expected results : Double data rate output on dataout.
16948 //END MODULE NAME --------------------------------------------------------------
16950 `timescale 1 ps / 1 ps
16952 // MODULE DECLARATION
16953 module altddio_out (
16954 datain_h, // required port, data input for the rising edge of outclock
16955 datain_l, // required port, data input for the falling edge of outclock
16956 outclock, // required port, input reference clock to output data by
16957 outclocken, // clock enable signal for outclock
16958 aset, // asynchronous set
16959 aclr, // asynchronous clear
16960 oe, // output enable for dataout
16961 dataout // DDR data output
16964 // GLOBAL PARAMETER DECLARATION
16965 parameter width = 1; // required parameter
16966 parameter power_up_high = "OFF";
16967 parameter oe_reg = "UNUSED";
16968 parameter extend_oe_disable = "UNUSED";
16969 parameter intended_device_family = "MERCURY";
16970 parameter invert_output = "OFF";
16971 parameter lpm_type = "altddio_out";
16972 parameter lpm_hint = "UNUSED";
16974 // INPUT PORT DECLARATION
16975 input [width-1:0] datain_h;
16976 input [width-1:0] datain_l;
16983 // OUTPUT PORT DECLARATION
16984 output [width-1:0] dataout;
16986 // REGISTER, NET AND VARIABLE DECLARATION
16988 wire output_enable;
16991 reg [width-1:0] dataout;
16992 reg [width-1:0] dataout_h;
16993 reg [width-1:0] dataout_l;
16994 reg [width-1:0] dataout_tmp;
16996 ALTERA_DEVICE_FAMILIES dev ();
16999 tri0 aset; // default aset to 0
17000 tri0 aclr; // default aclr to 0
17001 tri1 outclocken; // default outclocken to 1
17002 tri1 oe; // default oe to 1
17007 // Begin of parameter checking
17010 $display("ERROR: The width parameter must be greater than 0");
17014 if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
17016 $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
17020 if (!(dev.IS_FAMILY_MERCURY(intended_device_family) ||
17021 dev.IS_FAMILY_APEXII(intended_device_family) ||
17022 dev.IS_FAMILY_STRATIX(intended_device_family) ||
17023 dev.IS_FAMILY_STRATIXGX(intended_device_family) ||
17024 dev.IS_FAMILY_CYCLONE(intended_device_family) ||
17025 dev.FEATURE_FAMILY_STRATIXII(intended_device_family) ||
17026 dev.IS_FAMILY_HARDCOPYSTRATIX(intended_device_family) ||
17027 dev.IS_FAMILY_CYCLONEII(intended_device_family)))
17029 $display("ERROR: Megafunction altddio_out is not supported in %s.", intended_device_family);
17032 // End of parameter checking
17034 // if power_up_high parameter is turned on, registers power up to '1'
17036 dataout_h = (power_up_high == "ON") ? {width{1'b1}} : {width{1'b0}};
17037 dataout_l = (power_up_high == "ON") ? {width{1'b1}} : {width{1'b0}};
17038 dataout_tmp = (power_up_high == "ON") ? {width{1'b1}} : {width{1'b0}};
17040 if (power_up_high == "ON")
17053 // input reference clock
17054 always @ (posedge outclock or posedge aclr or posedge aset)
17058 dataout_h <= {width{1'b0}};
17059 dataout_l <= {width{1'b0}};
17060 dataout_tmp <= {width{1'b0}};
17066 dataout_h <= {width{1'b1}};
17067 dataout_l <= {width{1'b1}};
17068 dataout_tmp <= {width{1'b1}};
17072 // if clock is enabled
17073 else if (outclocken == 1'b1)
17075 dataout_h <= datain_h;
17076 dataout_l <= datain_l;
17077 dataout_tmp <= datain_h;
17079 // register the output enable signal
17083 dataout_tmp <= dataout_h;
17087 // input reference clock
17088 always @ (negedge outclock or posedge aclr or posedge aset)
17092 oe_reg_ext <= 1'b0;
17096 oe_reg_ext <= 1'b1;
17098 // if not being set or cleared
17101 // if clock is enabled
17102 if (outclocken == 1'b1)
17104 // additional register for output enable signal
17105 oe_reg_ext <= oe_rgd;
17108 dataout_tmp <= dataout_l;
17113 always @(dataout_tmp or output_enable)
17115 // if output is enabled
17116 if (output_enable == 1'b1)
17118 if (dev.FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO(intended_device_family) &&
17119 (invert_output == "ON"))
17120 dataout = ~dataout_tmp;
17122 dataout = dataout_tmp;
17124 else // output is disabled
17125 dataout = {width{1'bZ}};
17128 // output enable signal
17129 // Mercury does not support extend_oe_disable and oe_reg parameters
17130 assign output_enable = (dev.IS_FAMILY_APEXII(intended_device_family) ||
17131 dev.IS_FAMILY_STRATIX(intended_device_family)||
17132 dev.IS_FAMILY_STRATIXGX(intended_device_family) ||
17133 dev.IS_FAMILY_CYCLONE(intended_device_family) ||
17134 dev.FEATURE_FAMILY_STRATIXII(intended_device_family) ||
17135 dev.IS_FAMILY_HARDCOPYSTRATIX(intended_device_family) ||
17136 dev.IS_FAMILY_CYCLONEII(intended_device_family))
17140 assign apexii_oe = (extend_oe_disable == "ON")
17141 ? (oe_reg_ext & oe_rgd)
17142 : ((oe_reg == "REGISTERED") && (extend_oe_disable != "ON"))
17146 endmodule // altddio_out
17147 // END MODULE ALTDDIO_OUT
17149 // START MODULE NAME -----------------------------------------------------------
17151 // Module Name : ALTDDIO_BIDIR
17153 // Description : Double Data Rate (DDR) bi-directional behavioural model.
17154 // Transmits and receives data on both edges of the reference
17157 // Limitations : Not available for FLEX, MAX, APEX20K and APEX20KE device
17160 // Expected results : Data output sampled from padio port on rising edge of
17161 // inclock signal (dataout_h) and falling edge of inclock
17162 // signal (dataout_l). Combinatorial output fed by padio
17163 // directly (combout).
17165 //END MODULE NAME --------------------------------------------------------------
17167 `timescale 1 ps / 1 ps
17169 // MODULE DECLARATION
17170 module altddio_bidir (
17171 datain_h, // required port, input data to be output of padio port at the
17172 // rising edge of outclock
17173 datain_l, // required port, input data to be output of padio port at the
17174 // falling edge of outclock
17175 inclock, // required port, input reference clock to sample data by
17176 inclocken, // inclock enable
17177 outclock, // required port, input reference clock to register data output
17178 outclocken, // outclock enable
17179 aset, // asynchronour set
17180 aclr, // asynchronous clear
17181 oe, // output enable for padio port
17182 dataout_h, // data sampled from the padio port at the rising edge of inclock
17183 dataout_l, // data sampled from the padio port at the falling edge of
17185 combout, // combinatorial output directly fed by padio
17186 dqsundelayedout, // undelayed DQS signal to the PLD core
17187 padio // bidirectional DDR port
17190 // GLOBAL PARAMETER DECLARATION
17191 parameter width = 1; // required parameter
17192 parameter power_up_high = "OFF";
17193 parameter oe_reg = "UNUSED";
17194 parameter extend_oe_disable = "UNUSED";
17195 parameter implement_input_in_lcell = "UNUSED";
17196 parameter invert_output = "OFF";
17197 parameter intended_device_family = "MERCURY";
17198 parameter lpm_type = "altddio_bidir";
17199 parameter lpm_hint = "UNUSED";
17201 // INPUT PORT DECLARATION
17202 input [width-1:0] datain_h;
17203 input [width-1:0] datain_l;
17212 // OUTPUT PORT DECLARATION
17213 output [width-1:0] dataout_h;
17214 output [width-1:0] dataout_l;
17215 output [width-1:0] combout;
17216 output [width-1:0] dqsundelayedout;
17217 // BIDIRECTIONAL PORT DECLARATION
17218 inout [width-1:0] padio;
17232 // Begin of parameter checking
17235 $display("ERROR: The width parameter must be greater than 0");
17238 // End of parameter checking
17242 // COMPONENT INSTANTIATION
17247 .inclocken(inclocken),
17250 .dataout_h(dataout_h),
17251 .dataout_l(dataout_l)
17253 defparam u1.width = width,
17254 u1.intended_device_family = intended_device_family,
17255 u1.power_up_high = power_up_high;
17259 .datain_h(datain_h),
17260 .datain_l(datain_l),
17261 .outclock(outclock),
17263 .outclocken(outclocken),
17268 defparam u2.width = width,
17269 u2.power_up_high = power_up_high,
17270 u2.intended_device_family = intended_device_family,
17271 u2.oe_reg = oe_reg,
17272 u2.extend_oe_disable = extend_oe_disable,
17273 u2.invert_output = invert_output;
17275 // padio feeds combout port directly
17276 assign combout = padio;
17277 assign dqsundelayedout = padio;
17278 endmodule // altddio_bidir
17279 // END MODULE ALTDDIO_BIDIR
17281 // START MODULE NAME -----------------------------------------------------------
17283 // Module Name : HSSI_PLL
17285 // Description : This is the Phase Locked Loop (PLL) model used by altcdr_rx
17286 // and altcdr_tx. Simple PLL model with 1 clock input (clk) and
17287 // 2 clock outputs (clk0 & clk1).
17289 // Limitations : Only capable of multiplying and dividing the input clock
17290 // frequency. There is no support for phase shifts, uneven duty
17291 // cycles or other fancy PLL features, since the Mercury CDR
17292 // does not need these features.
17294 // Expected results : 2 output clocks - clk0 and clk1. Locked output indicates
17295 // when the PLL locks.
17297 //END MODULE NAME --------------------------------------------------------------
17299 `timescale 1 ps / 1 ps
17301 // MODULE DECLARATION
17303 clk, // input clock
17304 areset, // asynchronous reset
17305 clk0, // output clock0
17306 clk1, // output clock1
17307 locked // PLL lock signal
17310 // GLOBAL PARAMETER DECLARATION
17311 parameter clk0_multiply_by = 1;
17312 parameter clk1_divide_by = 1;
17313 parameter input_frequency = 1000; // period in ps
17315 // INPUT PORT DECLARATION
17319 // OUTPUT PORT DECLARATION
17324 // INTERNAL SIGNAL/REGISTER DECLARATION
17331 reg clk_last_value;
17334 reg [1:0] next_clk_check;
17337 // INTERNAL VARIABLE DECLARATION
17338 real pll_last_rising_edge;
17339 real pll_last_falling_edge;
17340 real actual_clk_cycle;
17341 real expected_clk_cycle;
17342 real pll_duty_cycle;
17346 real expected_next_clk_edge;
17348 integer pll_rising_edge_count;
17349 integer stop_lock_count;
17350 integer start_lock_count;
17351 integer first_clk0_cycle;
17352 integer first_clk1_cycle;
17353 integer lock_on_rise;
17354 integer lock_on_fall;
17355 integer clk_per_tolerance;
17359 // variables for clock synchronizing
17360 integer last_synchronizing_rising_edge_for_clk0;
17361 integer last_synchronizing_rising_edge_for_clk1;
17362 integer clk0_synchronizing_period;
17363 integer clk1_synchronizing_period;
17369 integer input_cycles_per_clk0;
17370 integer input_cycles_per_clk1;
17371 integer clk0_cycles_per_sync_period;
17372 integer clk1_cycles_per_sync_period;
17373 integer input_cycle_count_to_sync0;
17374 integer input_cycle_count_to_sync1;
17376 integer sched_time0;
17377 integer sched_time1;
17388 integer cycle_to_adjust0;
17389 integer cycle_to_adjust1;
17392 integer high_time0;
17393 integer high_time1;
17401 pll_rising_edge_count = 0;
17403 stop_lock_count = 0;
17404 start_lock_count = 0;
17405 clk_last_value = clk_in;
17406 first_clk0_cycle = 1;
17407 first_clk1_cycle = 1;
17411 pll_last_rising_edge = 0;
17412 pll_last_falling_edge = 0;
17417 last_synchronizing_rising_edge_for_clk0 = 0;
17418 last_synchronizing_rising_edge_for_clk1 = 0;
17419 clk0_synchronizing_period = 0;
17420 clk1_synchronizing_period = 0;
17423 input_cycles_per_clk0 = 1;
17424 input_cycles_per_clk1 = clk1_divide_by;
17425 clk0_cycles_per_sync_period = clk0_multiply_by;
17426 clk1_cycles_per_sync_period = clk0_multiply_by;
17427 input_cycle_count_to_sync0 = 0;
17428 input_cycle_count_to_sync1 = 0;
17431 cycle_to_adjust0 = 0;
17432 cycle_to_adjust1 = 0;
17435 // trigger input clock checking for the purpose of detecting an input clock that
17436 // has flatlined or that violates the specified input frequency or 50% duty
17437 // cycle - with tolerance
17438 always @(next_clk_check)
17440 if (next_clk_check == 1)
17442 #((inclk_period+clk_per_tolerance)/2) clk_check = ~clk_check;
17444 else if (next_clk_check == 2)
17446 #(expected_next_clk_edge - $realtime) clk_check = ~clk_check;
17448 next_clk_check = 0;
17451 // same as initial block
17452 // reset all variables, registers and signals on positive edge of areset
17453 always @(posedge areset)
17455 pll_rising_edge_count = 0;
17457 stop_lock_count = 0;
17458 start_lock_count = 1;
17459 clk_last_value = 0;
17460 first_clk0_cycle = 1;
17461 first_clk1_cycle = 1;
17467 pll_last_rising_edge = 0;
17468 pll_last_falling_edge = 0;
17473 // on change of input clock or clock check trigger,
17474 // monitor for duty cycle/input frequency violation
17475 // schedule clk0 and clk1 output, handles the PLL locking
17476 always @(clk_in or clk_check)
17478 if (areset !== 1'b1)
17480 // rising edge of the clock
17481 if ((clk_in === 1'b1) && (clk_last_value !== clk_in))
17483 if (pll_lock === 1'b1)
17484 next_clk_check = 1;
17485 if (pll_rising_edge_count == 0) // this is first rising edge
17487 inclk_period = input_frequency;
17488 pll_duty_cycle = inclk_period/2;
17489 clk_per_tolerance = 0.025 * inclk_period;
17491 clk0_period = inclk_period / clk0_multiply_by;
17492 clk1_period = inclk_period / clk0_multiply_by * clk1_divide_by;
17494 pll_last_rising_edge = $realtime;
17496 else if (pll_rising_edge_count == 1) // this is second rising edge
17498 expected_clk_cycle = inclk_period;
17499 actual_clk_cycle = $realtime - pll_last_rising_edge;
17501 // input frequency violation check
17502 if (actual_clk_cycle < (expected_clk_cycle - clk_per_tolerance) ||
17503 actual_clk_cycle > (expected_clk_cycle + clk_per_tolerance))
17505 $display($realtime, "Warning: Input frequency Violation");
17507 if (locked === 1'b1)
17509 stop_lock_count = stop_lock_count + 1;
17510 // PLL breaks its lock
17511 if ((locked === 1'b1) && (stop_lock_count == lock_low))
17514 start_lock_count = 1;
17515 stop_lock_count = 0;
17523 // Duty cycle violation check
17524 if (($realtime - pll_last_falling_edge) < (pll_duty_cycle - (clk_per_tolerance/2)) ||
17525 ($realtime - pll_last_falling_edge) > (pll_duty_cycle + (clk_per_tolerance/2)))
17527 $display($realtime, "Warning: Duty Cycle Violation");
17534 // input frequency violation check
17535 else if (($realtime - pll_last_rising_edge) < (expected_clk_cycle - clk_per_tolerance) ||
17536 ($realtime - pll_last_rising_edge) > (expected_clk_cycle + clk_per_tolerance))
17538 $display($realtime, "Warning: Cycle Violation");
17540 if (locked === 1'b1)
17542 stop_lock_count = stop_lock_count + 1;
17543 // PLL breaks its lock
17544 if (stop_lock_count == lock_low)
17547 start_lock_count = 1;
17548 stop_lock_count = 0;
17556 actual_clk_cycle = $realtime - pll_last_rising_edge;
17558 pll_last_rising_edge = $realtime;
17559 pll_rising_edge_count = pll_rising_edge_count + 1;
17561 // if no violation is detected, schedule clk0 and clk1
17564 if (pll_lock === 1'b1)
17566 input_cycle_count_to_sync0 = input_cycle_count_to_sync0 + 1;
17567 if (input_cycle_count_to_sync0 == input_cycles_per_clk0)
17569 clk0_synchronizing_period = $realtime - last_synchronizing_rising_edge_for_clk0;
17570 last_synchronizing_rising_edge_for_clk0 = $realtime;
17572 input_cycle_count_to_sync0 = 0;
17575 input_cycle_count_to_sync1 = input_cycle_count_to_sync1 + 1;
17576 if (input_cycle_count_to_sync1 == input_cycles_per_clk1)
17578 clk1_synchronizing_period = $realtime - last_synchronizing_rising_edge_for_clk1;
17579 last_synchronizing_rising_edge_for_clk1 = $realtime;
17581 input_cycle_count_to_sync1 = 0;
17585 start_lock_count = start_lock_count + 1;
17586 if (start_lock_count >= (lock_high + 1))
17589 input_cycle_count_to_sync0 = 0;
17590 input_cycle_count_to_sync1 = 0;
17592 if (last_synchronizing_rising_edge_for_clk0 == 0)
17594 clk0_synchronizing_period = actual_clk_cycle;
17597 clk0_synchronizing_period = $realtime - last_synchronizing_rising_edge_for_clk0;
17599 if (last_synchronizing_rising_edge_for_clk1 == 0)
17600 clk1_synchronizing_period = actual_clk_cycle * clk1_divide_by;
17602 clk1_synchronizing_period = $realtime - last_synchronizing_rising_edge_for_clk1;
17604 last_synchronizing_rising_edge_for_clk0 = $realtime;
17605 last_synchronizing_rising_edge_for_clk1 = $realtime;
17612 start_lock_count = 1;
17614 // falling edge of input clock
17615 else if ((clk_in === 1'b0) && (clk_last_value !== clk_in))
17617 if (pll_lock === 1'b1)
17619 next_clk_check = 1;
17620 if (($realtime - pll_last_rising_edge) < (pll_duty_cycle - (clk_per_tolerance/2)) ||
17621 ($realtime - pll_last_rising_edge) > (pll_duty_cycle + (clk_per_tolerance/2)))
17623 $display($realtime, "Warning: Duty Cycle Violation");
17625 if (locked === 1'b1)
17627 stop_lock_count = stop_lock_count + 1;
17628 if (stop_lock_count == lock_low)
17631 start_lock_count = 1;
17632 stop_lock_count = 0;
17642 start_lock_count = start_lock_count + 1;
17644 pll_last_falling_edge = $realtime;
17646 else if (pll_lock === 1'b1) // perform clock check
17648 if (clk_in === 1'b1)
17649 expected_next_clk_edge = pll_last_rising_edge + ((inclk_period+clk_per_tolerance)/2);
17650 else if (clk_in === 1'b0)
17651 expected_next_clk_edge = pll_last_falling_edge + ((inclk_period+clk_per_tolerance)/2);
17653 expected_next_clk_edge = 0;
17656 if ($realtime < expected_next_clk_edge)
17657 next_clk_check = 2;
17658 else if ($realtime == expected_next_clk_edge)
17659 next_clk_check = 1;
17662 $display($realtime, "Warning: Input frequency Violation");
17664 if (locked === 1'b1)
17666 stop_lock_count = stop_lock_count + 1;
17667 expected_next_clk_edge = $realtime + (inclk_period/2);
17668 // PLL breaks its lock
17669 if (stop_lock_count == lock_low)
17672 start_lock_count = 1;
17673 stop_lock_count = 0;
17678 next_clk_check = 2;
17682 clk_last_value = clk_in;
17686 // schedule clk0 output
17687 always @(posedge schedule_clk0)
17690 cycle_to_adjust0 = 0;
17691 output_value0 = 1'b1;
17693 rem0 = clk0_synchronizing_period % clk0_cycles_per_sync_period;
17694 for (i0 = 1; i0 <= clk0_cycles_per_sync_period; i0 = i0 + 1)
17696 tmp_per0 = clk0_synchronizing_period/clk0_cycles_per_sync_period;
17697 if (rem0 != 0 && l0 <= rem0)
17699 tmp_rem0 = (clk0_cycles_per_sync_period * l0) % rem0;
17700 cycle_to_adjust0 = (clk0_cycles_per_sync_period * l0) / rem0;
17702 cycle_to_adjust0 = cycle_to_adjust0 + 1;
17704 if (cycle_to_adjust0 == i0)
17706 tmp_per0 = tmp_per0 + 1;
17709 high_time0 = tmp_per0/2;
17710 if (tmp_per0 % 2 != 0)
17711 high_time0 = high_time0 + 1;
17712 low_time0 = tmp_per0 - high_time0;
17713 for (j0 = 0; j0 <= 1; j0 = j0 + 1)
17715 clk0_tmp = #(sched_time0) output_value0;
17716 output_value0 = ~output_value0;
17717 if (output_value0 === 1'b0)
17718 sched_time0 = high_time0;
17719 else if (output_value0 === 1'b1)
17720 sched_time0 = low_time0;
17723 schedule_clk0 = #1 1'b0;
17731 // schedule clk1 output
17732 always @(posedge schedule_clk1)
17735 cycle_to_adjust1 = 0;
17736 output_value1 = 1'b1;
17738 rem1 = clk1_synchronizing_period % clk1_cycles_per_sync_period;
17739 for (i1 = 1; i1 <= clk1_cycles_per_sync_period; i1 = i1 + 1)
17741 tmp_per1 = clk1_synchronizing_period/clk1_cycles_per_sync_period;
17742 if (rem1 != 0 && l1 <= rem1)
17744 tmp_rem1 = (clk1_cycles_per_sync_period * l1) % rem1;
17745 cycle_to_adjust1 = (clk1_cycles_per_sync_period * l1) / rem1;
17747 cycle_to_adjust1 = cycle_to_adjust1 + 1;
17749 if (cycle_to_adjust1 == i1)
17751 tmp_per1 = tmp_per1 + 1;
17754 high_time1 = tmp_per1/2;
17755 if (tmp_per1 % 2 != 0)
17756 high_time1 = high_time1 + 1;
17757 low_time1 = tmp_per1 - high_time1;
17758 for (j1 = 0; j1 <= 1; j1 = j1 + 1)
17760 clk1_tmp = #(sched_time1) output_value1;
17761 output_value1 = ~output_value1;
17762 if (output_value1 === 1'b0)
17763 sched_time1 = high_time1;
17764 else if (output_value1 === 1'b1)
17765 sched_time1 = low_time1;
17768 schedule_clk1 <= #1 1'b0;
17776 buf (locked, pll_lock);
17778 endmodule // hssi_pll
17781 // START MODULE NAME -----------------------------------------------------------
17783 // Module Name : MF_RAM7X20_SYN
17785 // Description : This is the RAM model used by HSSI_FIFO for writing and reading
17788 // Limitations : Reading from the RAM is address-triggered,
17789 // writing is clock-triggered
17790 // RAM depth is fixed to 7, maximum width is 20
17792 // Expected results : data output from the RAM
17794 //END MODULE NAME --------------------------------------------------------------
17796 `timescale 1ps / 1ps
17798 module MF_ram7x20_syn (
17799 wclk, // write clock
17800 rst_l, // active low asynchronous reset
17801 addr_wr, // write address
17802 addr_rd, // read address
17803 data_in, // data input to the RAM
17804 we, // write enable
17806 data_out // data output from the RAM
17809 // GLOBAL PARAMETER DECLARATION
17810 parameter ram_width = 20;
17812 // INPUT PORT DECLARATION
17814 input rst_l; // active low
17815 input [2:0] addr_wr;
17816 input [2:0] addr_rd;
17817 input [19:0] data_in;
17821 // OUTPUT PORT DECLARATION
17822 output [19:0] data_out;
17824 // INTERNAL REGISTER/SIGNAL DECLARATION
17825 reg [ram_width-1:0] data_out_i;
17826 reg [ram_width-1:0] ram_array_d_0, ram_array_d_1, ram_array_d_2,
17827 ram_array_d_3, ram_array_d_4, ram_array_d_5,
17829 ram_array_q_0, ram_array_q_1, ram_array_q_2,
17830 ram_array_q_3, ram_array_q_4, ram_array_q_5,
17832 wire [ram_width-1:0] data_reg_0, data_reg_1, data_reg_2,
17833 data_reg_3, data_reg_4, data_reg_5, data_reg_6;
17835 // Modelling the read port
17836 // Assuming address triggered operation only
17838 data_reg_0 = ( addr_wr == 3'b000 ) ? data_in : ram_array_q_0,
17839 data_reg_1 = ( addr_wr == 3'b001 ) ? data_in : ram_array_q_1,
17840 data_reg_2 = ( addr_wr == 3'b010 ) ? data_in : ram_array_q_2,
17841 data_reg_3 = ( addr_wr == 3'b011 ) ? data_in : ram_array_q_3,
17842 data_reg_4 = ( addr_wr == 3'b100 ) ? data_in : ram_array_q_4,
17843 data_reg_5 = ( addr_wr == 3'b101 ) ? data_in : ram_array_q_5,
17844 data_reg_6 = ( addr_wr == 3'b110 ) ? data_in : ram_array_q_6;
17846 assign data_out = re ? data_out_i : 20'b0;
17848 always @(ram_array_q_0 or ram_array_q_1 or
17849 ram_array_q_2 or ram_array_q_3 or
17850 ram_array_q_4 or ram_array_q_5 or
17851 ram_array_q_6 or addr_rd or we or addr_wr)
17854 3'b000 : data_out_i = ram_array_q_0;
17855 3'b001 : data_out_i = ram_array_q_1;
17856 3'b010 : data_out_i = ram_array_q_2;
17857 3'b011 : data_out_i = ram_array_q_3;
17858 3'b100 : data_out_i = ram_array_q_4;
17859 3'b101 : data_out_i = ram_array_q_5;
17860 3'b110 : data_out_i = ram_array_q_6;
17861 default: data_out_i = data_out_i;
17865 // Modelling the write port
17866 always @(posedge wclk or negedge rst_l)
17868 if(~rst_l) // reset
17870 ram_array_q_0 <= 0;
17871 ram_array_q_1 <= 0;
17872 ram_array_q_2 <= 0;
17873 ram_array_q_3 <= 0;
17874 ram_array_q_4 <= 0;
17875 ram_array_q_5 <= 0;
17876 ram_array_q_6 <= 0;
17880 ram_array_q_0 <= ram_array_d_0;
17881 ram_array_q_1 <= ram_array_d_1;
17882 ram_array_q_2 <= ram_array_d_2;
17883 ram_array_q_3 <= ram_array_d_3;
17884 ram_array_q_4 <= ram_array_d_4;
17885 ram_array_q_5 <= ram_array_d_5;
17886 ram_array_q_6 <= ram_array_d_6;
17891 data_reg_0 or data_reg_1 or
17892 data_reg_2 or data_reg_3 or
17893 data_reg_4 or data_reg_5 or
17895 ram_array_q_0 or ram_array_q_1 or
17896 ram_array_q_2 or ram_array_q_3 or
17897 ram_array_q_4 or ram_array_q_5 or
17900 if (we) // write enabled
17902 ram_array_d_0 <= data_reg_0;
17903 ram_array_d_1 <= data_reg_1;
17904 ram_array_d_2 <= data_reg_2;
17905 ram_array_d_3 <= data_reg_3;
17906 ram_array_d_4 <= data_reg_4;
17907 ram_array_d_5 <= data_reg_5;
17908 ram_array_d_6 <= data_reg_6;
17912 ram_array_d_0 <= ram_array_q_0;
17913 ram_array_d_1 <= ram_array_q_1;
17914 ram_array_d_2 <= ram_array_q_2;
17915 ram_array_d_3 <= ram_array_q_3;
17916 ram_array_d_4 <= ram_array_q_4;
17917 ram_array_d_5 <= ram_array_q_5;
17918 ram_array_d_6 <= ram_array_q_6;
17922 endmodule // MF_ram7x20_syn
17925 // START MODULE NAME -----------------------------------------------------------
17927 // Module Name : HSSI_FIFO
17929 // Description : The FIFO model used by altcdr_rx and altcdr_tx to synchronize
17930 // data between 2 clock domains
17932 // Limitations : FIFO depth is limited to 7 words only,
17933 // the overflow and empty signals are active low in this model
17935 // Expected results : data read from the FIFO, empty and overflow signals
17936 // (active low) to indicate when FIFO is empty or full
17938 //END MODULE NAME --------------------------------------------------------------
17940 `timescale 1 ps / 1 ps
17941 `define CNTBIT 3 // 3 bit counter for FIFO read/write addresses
17944 datain, // data input to the FIFO
17945 clk0, // FIFO write clock
17946 clk1, // FIFO read clock
17947 we, // FIFO write enable
17948 re, // FIFO read enable
17949 reset, // FIFO asynchronous reset
17950 dataout, // data output from the FIFO
17951 empty, // active low FIFO empty signal
17952 overflow // active low FIFO full signal
17955 // GLOBAL PARAMETER DECLARATION
17956 parameter channel_width = 1;
17958 // INPUT PORT DECLARATION
17959 input [channel_width-1:0] datain;
17966 // OUTPUT PORT DECLARATION
17967 output [channel_width-1:0] dataout;
17971 // INTERNAL REGISTER/SIGNAL DECLARATION
17972 wire [19:0] ram_dataout;
17973 wire [19:0] data_out;
17974 reg [19:0] ram_datain;
17975 reg [19:0] dataout_tmp;
17982 // The following are for asynchronous fifo use
17983 reg [`CNTBIT-1:0] wrPtr0; // write pointer synchronizer
17984 reg [`CNTBIT-1:0] wrPtr1; // write pointer synchronizer
17985 reg [`CNTBIT-1:0] wrPtr2; // write pointer synchronizer
17986 reg [`CNTBIT-1:0] wrPtr,rdPtr; // writer pointer, read pointer
17987 reg [`CNTBIT-1:0] wrAddr; // writer address
17988 reg [`CNTBIT-1:0] preRdPtr,preRdPtr1,preRdPtr2;
17989 wire [`CNTBIT-1:0] rdAddr = rdPtr; // read address
17990 reg ram_we; // we for ram
17992 // Empty/Full checking
17993 wire fullFlag = (wrPtr0 == preRdPtr2)? 1 : 0;
17994 wire emptyFlag = (rdPtr == wrPtr2 && fullFlag == 'b0)? 1: 0;
17995 wire overflow_tmp_b;
17996 wire empty_tmp_b = !emptyFlag;
18004 buf (clk0_in, clk0);
18005 buf (clk1_in, clk1);
18008 buf (reset_in, reset);
18010 assign overflow_tmp_b = (reset_in)? 1'b0 : !fullFlag;
18012 // instantiate the 7x20 RAM for reading and writing data
18013 MF_ram7x20_syn ram_7x20_syn(
18015 .rst_l (!reset_in),
18018 .data_in (ram_datain),
18020 .re (re && empty_tmp_b),
18021 .data_out (ram_dataout)
18023 defparam ram_7x20_syn.ram_width = channel_width;
18025 // initialize the FIFO read and write pointers
18028 dataout_tmp = 20'b0;
18029 for (i = 0; i < `CNTBIT; i = i + 1)
18036 preRdPtr[i] = 1'b0;
18037 preRdPtr1[i] = 1'b0;
18038 preRdPtr2[i] = 1'b0;
18044 // output data on postive edge of read clock (clk1)
18045 always @(posedge clk1_in or posedge reset_in )
18047 if (reset_in === 1'b1)
18049 else if ((re_in === 1'b1) && (empty_tmp_b === 1'b1))
18050 dataout_tmp <= ram_dataout; // memory output latch
18052 dataout_tmp <= dataout_tmp;
18055 // Update the write pointer and send input data to the RAM
18056 // Delay the write pointer update until we have given the RAM the
18057 // write strobe. This prevents the not empty flag from going true
18058 // before the data actually makes it safely into the RAM
18059 always @(posedge clk0_in or posedge reset_in)
18061 if(reset_in === 1'b1) // reset
18064 ram_datain <= 20'b0;
18067 else if ((we_in === 1'b1) && (overflow_tmp_b === 1'b1))
18069 ram_datain <= datain;
18070 wrAddr <= wrPtr0; // wrLow for memory
18071 wrPtr0 <= wrPtr0 + 1;
18078 ram_datain <= ram_datain;
18084 always @(posedge clk0_in or posedge reset_in)
18086 if(reset_in === 1'b1)
18093 always @(posedge clk0_in or posedge reset_in)
18095 if (reset_in === 1'b1)
18097 else if ((we_in === 1'b1) && (overflow_tmp_b === 1'b1))
18103 // update read pointer
18104 always @(posedge clk1_in or posedge reset_in)
18106 if(reset_in === 1'b1)
18111 else if ((re_in === 1'b1) && (empty_tmp_b === 1'b1))
18113 rdPtr <= rdPtr + 1;
18120 // the following lines are for async. fifo.
18121 always @(posedge clk1_in or posedge reset_in)
18123 if (reset_in === 1'b1)
18130 wrPtr1 <= wrPtr; // sync. wrPtr to read clock
18135 always @(posedge clk0_in or posedge reset_in)
18137 if (reset_in === 1'b1)
18144 preRdPtr1 <= preRdPtr; // sync. RdPtr to write clock
18145 preRdPtr2 <= preRdPtr1;
18149 assign dataout = dataout_tmp;
18151 and (empty, empty_tmp_b, 1'b1);
18152 and (overflow, overflow_tmp_b, 1'b1);
18154 endmodule // hssi_fifo
18157 // START MODULE NAME -----------------------------------------------------------
18159 // Module Name : HSSI_RX
18161 // Description : This is the receiver model used by altcdr_rx. Performs
18162 // deserialization of input data.
18164 // Limitations : Assumes that the clock is already perfectly synchronized to the
18167 // Expected results: data output from the deserializer, slow clock (clkout)
18168 // generated by the RX, run length violation flag (rlv), and
18169 // locked output to indicate when the RX has failed to lock
18170 // onto the input data signal (not simulated)
18172 //END MODULE NAME --------------------------------------------------------------
18174 `timescale 1 ps / 1 ps
18178 coreclk, // slow (core) clock
18179 datain, // data input to the RX
18180 areset, // asynchronous reset
18181 feedback,// data feedback port
18182 fbkcntl, // feedback control port
18183 dataout, // data output from the RX
18184 clkout, // slow clock generated by the RX
18185 rlv, // run length violation flag
18186 locked // RX lost of lock indicator
18189 // GLOBAL PARAMETER DECLARATION
18190 parameter channel_width = 1;
18191 parameter operation_mode = "CDR";
18192 parameter run_length = 1;
18194 // INPUT PORT DECLARATION
18202 // OUTPUT PORT DECLARATION
18203 output [channel_width-1:0] dataout;
18208 // INTERNAL VARIABLE/SIGNAL/REGISTER DECLARATION
18212 reg clk_last_value;
18213 reg coreclk_last_value;
18214 reg clkout_last_value;
18215 reg [channel_width-1:0] deser_data_arr;
18221 reg [19:0] dataout_tmp;
18225 wire [19:0] data_out;
18234 tri0 areset, feedback, fbkcntl;
18237 buf (coreclk_in, coreclk);
18238 buf (datain_buf, datain);
18239 buf (fbin_in, feedback);
18240 buf (fbena_in, fbkcntl);
18241 buf (areset_in, areset);
18247 clk_count = channel_width;
18248 clk_last_value = 0;
18249 coreclk_last_value = 0;
18255 dataout_tmp = 20'b0;
18256 last_datain = 1'bx;
18257 data_changed = 1'b0;
18260 // deserialize incoming data, generate clkout and check for run length violation
18261 always @(clk_in or coreclk_in or areset_in or fbena_in)
18263 if (areset_in === 1'b1) // reset
18266 dataout_tmp = 20'b0;
18270 last_datain = 1'bx;
18272 data_changed = 1'b0;
18273 clk_count = channel_width;
18274 for (i = channel_width - 1; i >= 0; i = i - 1)
18275 deser_data_arr[i] = 1'b0;
18279 if (fbena_in === 1'b1)
18280 datain_in = fbin_in;
18282 datain_in = datain_buf;
18283 if ((clk_in === 1'b1) && (clk_last_value !== clk_in))
18285 if (clk_count == channel_width)
18288 clkout_tmp = !clkout_last_value;
18290 else if (clk_count == (channel_width+1)/2)
18291 clkout_tmp = !clkout_last_value;
18292 else if (clk_count < channel_width)
18293 clkout_tmp = clkout_last_value;
18294 clk_count = clk_count + 1;
18296 //rlv (run length violation) checking
18297 if (operation_mode == "CDR")
18299 if (last_datain !== datain_in)
18301 data_changed = 1'b1;
18302 last_datain = datain_in;
18304 else // data not changed - increment rlv_count
18306 rlv_count = rlv_count + 1;
18307 data_changed = 1'b0;
18310 if (rlv_count > run_length)
18322 if ((coreclk_in === 1'b1) && (coreclk_last_value !== coreclk_in))
18324 // output the rlv status with the rising edge of the coreclk
18325 if (operation_mode == "CDR")
18327 if (rlv_flag === 1'b1)
18330 if (rlv_set === 1'b0)
18338 // deserialize the data
18339 if ((clk_in === 1'b0) && (clk_last_value !== clk_in))
18341 if ((clk_count == 3))
18342 dataout_tmp[channel_width-1:0] = deser_data_arr;
18344 for (i = channel_width - 1; i >= 1; i = i - 1)
18345 deser_data_arr[i] = deser_data_arr[i-1];
18347 deser_data_arr[0] = datain_in;
18350 clk_last_value = clk_in;
18351 coreclk_last_value = coreclk_in;
18352 clkout_last_value = clkout_tmp;
18355 assign dataout = dataout_tmp;
18357 and (rlv, rlv_tmp, 1'b1);
18358 and (locked, locked_tmp, 1'b1);
18359 and (clkout, clkout_tmp, 1'b1);
18361 endmodule // hssi_rx
18363 // START MODULE NAME -----------------------------------------------------------
18365 // Module Name : HSSI_TX
18367 // Description : The transmitter module used by altcdr_tx. Performs
18368 // serialization of output data.
18372 // Expected results : Serial data output (dataout) and generated slow clock
18375 //END MODULE NAME --------------------------------------------------------------
18377 `timescale 1 ps / 1 ps
18379 // MODULE DECLARATION
18382 datain, // parallel input data
18383 areset, // asynchronous reset
18384 dataout, // serial data output
18385 clkout // generated clock
18388 // GLOBAL PARAMETER DECLARATION
18389 parameter channel_width = 1;
18391 // INPUT PORT DECLARATION
18393 input [channel_width-1:0] datain;
18396 // OUTPUT PORT DECLARATION
18400 // INTERNAL VARIABLE/REGISTER DECLARATION
18402 integer fast_clk_count;
18403 reg clk_in_last_value;
18405 reg clkout_last_value;
18408 reg [19:0] regdata;
18413 buf (areset_in, areset);
18418 fast_clk_count = channel_width;
18419 clk_in_last_value = 0;
18420 dataout_tmp = 1'b0;
18421 clkout_last_value = 0;
18425 always @(clk_in or areset_in)
18428 if (areset_in == 1'b1)
18430 dataout_tmp = 1'b0;
18432 fast_clk_count = channel_width;
18433 for (i = channel_width-1; i >= 0; i = i - 1) // resets register
18435 for (i = channel_width-1; i >= 0; i = i - 1) // resets register
18438 else // serialize incoming parallel data and generate slow clock
18440 // rising edge of fast clock
18441 if ((clk_in === 1'b1) && (clk_in_last_value !== clk_in))
18443 // slow clock generation
18444 if (fast_clk_count == channel_width)
18446 fast_clk_count = 0;
18447 clkout_tmp = !clkout_last_value;
18449 else if (fast_clk_count == (channel_width+1)/2)
18450 clkout_tmp = !clkout_last_value;
18451 else if (fast_clk_count < channel_width)
18452 clkout_tmp = clkout_last_value;
18454 fast_clk_count = fast_clk_count + 1;
18456 // 3rd rising edge, start to shift out
18457 if (fast_clk_count == 3)
18459 for (i = channel_width-1; i >= 0; i = i - 1)
18460 regdata[i] = indata[i];
18463 // send the MSB of regdata out
18464 dataout_tmp = regdata[channel_width-1];
18466 for (i = channel_width-1; i > 0; i = i - 1)
18467 regdata[i] = regdata[i-1];
18469 // falling edge of fast clock
18470 if ((clk_in === 1'b0) && (clk_in_last_value !== clk_in))
18472 if (fast_clk_count == 3) // loading at the 3rd falling edge
18478 clk_in_last_value = clk_in;
18479 clkout_last_value = clkout_tmp;
18482 and (dataout, dataout_tmp, 1'b1);
18483 and (clkout, clkout_tmp, 1'b1);
18485 endmodule // hssi_tx
18487 // START MODULE NAME -----------------------------------------------------------
18489 // Module Name : ALTCDR_RX
18491 // Description : Clock Data Recovery (CDR) Receiver behavioral model. Consists
18492 // of CDR receiver for deserialization, a Phase Locked Loop (PLL)
18495 // Limitations : Available for the Mercury device family only
18497 // Expected results : Deserialized data output (rx_out), recovered global data
18498 // clock (rx_outclock), PLL lock signal, RX lost of lock signal,
18499 // RX run length violation signal, RX FIFO full and empty
18500 // signals (active high), recovered clock per channel
18503 //END MODULE NAME --------------------------------------------------------------
18505 `timescale 1 ps / 1 ps
18507 // MODULE DECLARATION
18509 rx_in, // required port, data input
18510 rx_inclock, // required port, input reference clock
18511 rx_coreclock, // required port, core clock
18512 rx_aclr, // asynchronous reset for the RX and FIFO
18513 rx_pll_aclr, // asynchronous reset for the PLL
18514 rx_fifo_rden, // FIFO read enable
18515 rx_out, // data output
18516 rx_outclock, // global clock recovered from channel 0
18517 rx_pll_locked,// PLL lock signal
18518 rx_locklost, // RX lock of lost wrt input data
18519 rx_rlv, // data run length violation flag
18520 rx_full, // FIFO full signal
18521 rx_empty, // FIFO empty signal
18522 rx_rec_clk // recovered clock from each channel
18525 // GLOBAL PARAMETER DECLARATION
18526 parameter number_of_channels = 1;
18527 parameter deserialization_factor = 3; // Valid deserialization_factor
18528 parameter inclock_period = 20000; // 20000ps = 50MHz
18529 parameter inclock_boost = 1;
18530 parameter run_length = 62; // default based on SONET requirements
18531 parameter bypass_fifo = "OFF";
18532 parameter intended_device_family = "MERCURY";
18533 parameter lpm_type = "altcdr_rx";
18534 parameter lpm_hint = "UNUSED";
18536 // Constant Declaration
18538 parameter RUN_LENGTH_MAX = 62; // Mercury Max.Run Length
18541 // INPUT PORT DECLARATION
18542 input [number_of_channels-1:0] rx_in;
18544 input rx_coreclock;
18547 input [number_of_channels-1:0] rx_fifo_rden;
18549 // OUTPUT PORT DECLARATION
18550 output [deserialization_factor*number_of_channels-1:0] rx_out;
18551 output rx_outclock;
18552 output rx_pll_locked;
18553 output [number_of_channels-1:0] rx_locklost;
18554 output [number_of_channels-1:0] rx_rlv;
18555 output [number_of_channels-1:0] rx_full;
18556 output [number_of_channels-1:0] rx_empty;
18557 output [number_of_channels-1:0] rx_rec_clk;
18559 // INTERNAL SIGNAL/VARIABLE DECLARATION
18561 wire [17:0] i_rx_full;
18562 wire [17:0] i_rx_empty;
18563 wire [17:0] i_rx_locked;
18564 wire [17:0] w_rx_clkout;
18565 wire [17:0] i_rx_rlv;
18567 wire [deserialization_factor-1:0] w_rx_out00;
18568 wire [deserialization_factor-1:0] w_rx_out01;
18569 wire [deserialization_factor-1:0] w_rx_out02;
18570 wire [deserialization_factor-1:0] w_rx_out03;
18571 wire [deserialization_factor-1:0] w_rx_out04;
18572 wire [deserialization_factor-1:0] w_rx_out05;
18573 wire [deserialization_factor-1:0] w_rx_out06;
18574 wire [deserialization_factor-1:0] w_rx_out07;
18575 wire [deserialization_factor-1:0] w_rx_out08;
18576 wire [deserialization_factor-1:0] w_rx_out09;
18577 wire [deserialization_factor-1:0] w_rx_out10;
18578 wire [deserialization_factor-1:0] w_rx_out11;
18579 wire [deserialization_factor-1:0] w_rx_out12;
18580 wire [deserialization_factor-1:0] w_rx_out13;
18581 wire [deserialization_factor-1:0] w_rx_out14;
18582 wire [deserialization_factor-1:0] w_rx_out15;
18583 wire [deserialization_factor-1:0] w_rx_out16;
18584 wire [deserialization_factor-1:0] w_rx_out17;
18585 wire [deserialization_factor-1:0] i_fifo_out00;
18586 wire [deserialization_factor-1:0] i_fifo_out01;
18587 wire [deserialization_factor-1:0] i_fifo_out02;
18588 wire [deserialization_factor-1:0] i_fifo_out03;
18589 wire [deserialization_factor-1:0] i_fifo_out04;
18590 wire [deserialization_factor-1:0] i_fifo_out05;
18591 wire [deserialization_factor-1:0] i_fifo_out06;
18592 wire [deserialization_factor-1:0] i_fifo_out07;
18593 wire [deserialization_factor-1:0] i_fifo_out08;
18594 wire [deserialization_factor-1:0] i_fifo_out09;
18595 wire [deserialization_factor-1:0] i_fifo_out10;
18596 wire [deserialization_factor-1:0] i_fifo_out11;
18597 wire [deserialization_factor-1:0] i_fifo_out12;
18598 wire [deserialization_factor-1:0] i_fifo_out13;
18599 wire [deserialization_factor-1:0] i_fifo_out14;
18600 wire [deserialization_factor-1:0] i_fifo_out15;
18601 wire [deserialization_factor-1:0] i_fifo_out16;
18602 wire [deserialization_factor-1:0] i_fifo_out17;
18604 tri0 [17:0] i_rx_in;
18605 wire [deserialization_factor*18-1:0] i_rx_out;
18606 wire [deserialization_factor*18-1:0] i_w_rx_out;
18614 // Default values for inputs
18615 tri0 rx_aclr_pulldown, rx_aclr;
18616 tri0 rx_pll_aclr_pulldown, rx_pll_aclr;
18617 tri1 [17:0] rx_fifo_rden_pullup;
18623 // Begin of parameter checking
18624 if (number_of_channels <= 0)
18626 $display("ERROR: The number_of_channels parameter must be greater than 0");
18630 if (run_length > RUN_LENGTH_MAX)
18632 $display("ERROR: The run_length parameter must be greater than %d", RUN_LENGTH_MAX);
18636 if (!(((deserialization_factor >= 3 ) && (deserialization_factor <= 12)) ||
18637 (deserialization_factor == 14) || (deserialization_factor == 16) ||
18638 (deserialization_factor == 18) || (deserialization_factor == 20)))
18640 $display("ERROR: Illegal value for deserialization_factor parameter (%d) -- value ", deserialization_factor);
18641 $display(" must be in the range 3 to 12, inclusive, or must be one of 14, 16, 18, or 20");
18646 // End of parameter checking
18651 assign rx_aclr_pulldown = rx_aclr;
18652 assign rx_pll_aclr_pulldown = rx_pll_aclr;
18653 assign rx_fifo_rden_pullup = rx_fifo_rden;
18655 //-----------------------------------------------------------------------
18656 // Instantiate the HSSI_RX to deserialize data - maximum of 18 channels
18658 .datain (i_rx_in[00]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown),
18659 .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock),
18660 .locked (i_rx_locked[00]),
18661 .dataout (w_rx_out00), .clkout (w_rx_clkout[00]), .rlv (i_rx_rlv[00]) );
18663 rx00.channel_width = deserialization_factor,
18664 rx00.operation_mode = "CDR",
18665 rx00.run_length = run_length;
18668 .datain (i_rx_in[01]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown),
18669 .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock),
18670 .locked (i_rx_locked[01]),
18671 .dataout (w_rx_out01), .clkout (w_rx_clkout[01]), .rlv (i_rx_rlv[01]) );
18673 rx01.channel_width = deserialization_factor,
18674 rx01.operation_mode = "CDR",
18675 rx01.run_length = run_length;
18678 .datain (i_rx_in[02]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown),
18679 .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock),
18680 .locked (i_rx_locked[02]),
18681 .dataout (w_rx_out02), .clkout (w_rx_clkout[02]), .rlv (i_rx_rlv[02]) );
18683 rx02.channel_width = deserialization_factor,
18684 rx02.operation_mode = "CDR",
18685 rx02.run_length = run_length;
18688 .datain (i_rx_in[03]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown),
18689 .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock),
18690 .locked (i_rx_locked[03]),
18691 .dataout (w_rx_out03), .clkout (w_rx_clkout[03]), .rlv (i_rx_rlv[03]) );
18693 rx03.channel_width = deserialization_factor,
18694 rx03.operation_mode = "CDR",
18695 rx03.run_length = run_length;
18698 .datain (i_rx_in[04]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown),
18699 .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock),
18700 .locked (i_rx_locked[04]),
18701 .dataout (w_rx_out04), .clkout (w_rx_clkout[04]), .rlv (i_rx_rlv[04]) );
18703 rx04.channel_width = deserialization_factor,
18704 rx04.operation_mode = "CDR",
18705 rx04.run_length = run_length;
18708 .datain (i_rx_in[05]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown),
18709 .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock),
18710 .locked (i_rx_locked[05]),
18711 .dataout (w_rx_out05), .clkout (w_rx_clkout[05]), .rlv (i_rx_rlv[05]) );
18713 rx05.channel_width = deserialization_factor,
18714 rx05.operation_mode = "CDR",
18715 rx05.run_length = run_length;
18718 .datain (i_rx_in[06]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown),
18719 .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock),
18720 .locked (i_rx_locked[06]),
18721 .dataout (w_rx_out06), .clkout (w_rx_clkout[06]), .rlv (i_rx_rlv[06]) );
18723 rx06.channel_width = deserialization_factor,
18724 rx06.operation_mode = "CDR",
18725 rx06.run_length = run_length;
18728 .datain (i_rx_in[07]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown),
18729 .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock),
18730 .locked (i_rx_locked[07]),
18731 .dataout (w_rx_out07), .clkout (w_rx_clkout[07]), .rlv (i_rx_rlv[07]) );
18733 rx07.channel_width = deserialization_factor,
18734 rx07.operation_mode = "CDR",
18735 rx07.run_length = run_length;
18738 .datain (i_rx_in[08]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown),
18739 .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock),
18740 .locked (i_rx_locked[08]),
18741 .dataout (w_rx_out08), .clkout (w_rx_clkout[08]), .rlv (i_rx_rlv[08]) );
18743 rx08.channel_width = deserialization_factor,
18744 rx08.operation_mode = "CDR",
18745 rx08.run_length = run_length;
18748 .datain (i_rx_in[09]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown),
18749 .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock),
18750 .locked (i_rx_locked[09]),
18751 .dataout (w_rx_out09), .clkout (w_rx_clkout[09]), .rlv (i_rx_rlv[09]) );
18753 rx09.channel_width = deserialization_factor,
18754 rx09.operation_mode = "CDR",
18755 rx09.run_length = run_length;
18758 .datain (i_rx_in[10]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown),
18759 .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock),
18760 .locked (i_rx_locked[10]),
18761 .dataout (w_rx_out10), .clkout (w_rx_clkout[10]), .rlv (i_rx_rlv[10]) );
18763 rx10.channel_width = deserialization_factor,
18764 rx10.operation_mode = "CDR",
18765 rx10.run_length = run_length;
18768 .datain (i_rx_in[11]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown),
18769 .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock),
18770 .locked (i_rx_locked[11]),
18771 .dataout (w_rx_out11), .clkout (w_rx_clkout[11]), .rlv (i_rx_rlv[11]) );
18773 rx11.channel_width = deserialization_factor,
18774 rx11.operation_mode = "CDR",
18775 rx11.run_length = run_length;
18778 .datain (i_rx_in[12]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown),
18779 .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock),
18780 .locked (i_rx_locked[12]),
18781 .dataout (w_rx_out12), .clkout (w_rx_clkout[12]), .rlv (i_rx_rlv[12]) );
18783 rx12.channel_width = deserialization_factor,
18784 rx12.operation_mode = "CDR",
18785 rx12.run_length = run_length;
18788 .datain (i_rx_in[13]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown),
18789 .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock),
18790 .locked (i_rx_locked[13]),
18791 .dataout (w_rx_out13), .clkout (w_rx_clkout[13]), .rlv (i_rx_rlv[13]) );
18793 rx13.channel_width = deserialization_factor,
18794 rx13.operation_mode = "CDR",
18795 rx13.run_length = run_length;
18798 .datain (i_rx_in[14]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown),
18799 .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock),
18800 .locked (i_rx_locked[14]),
18801 .dataout (w_rx_out14), .clkout (w_rx_clkout[14]), .rlv (i_rx_rlv[14]) );
18803 rx14.channel_width = deserialization_factor,
18804 rx14.operation_mode = "CDR",
18805 rx14.run_length = run_length;
18808 .datain (i_rx_in[15]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown),
18809 .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock),
18810 .locked (i_rx_locked[15]),
18811 .dataout (w_rx_out15), .clkout (w_rx_clkout[15]), .rlv (i_rx_rlv[15]) );
18813 rx15.channel_width = deserialization_factor,
18814 rx15.operation_mode = "CDR",
18815 rx15.run_length = run_length;
18818 .datain (i_rx_in[16]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown),
18819 .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock),
18820 .locked (i_rx_locked[16]),
18821 .dataout (w_rx_out16), .clkout (w_rx_clkout[16]), .rlv (i_rx_rlv[16]) );
18823 rx16.channel_width = deserialization_factor,
18824 rx16.operation_mode = "CDR",
18825 rx16.run_length = run_length;
18828 .datain (i_rx_in[17]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown),
18829 .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock),
18830 .locked (i_rx_locked[17]),
18831 .dataout (w_rx_out17), .clkout (w_rx_clkout[17]), .rlv (i_rx_rlv[17]) );
18833 rx17.channel_width = deserialization_factor,
18834 rx17.operation_mode = "CDR",
18835 rx17.run_length = run_length;
18838 //----------------------------------------------------------
18839 // Instantiate HSSI_PLL - use the same PLL for all channels
18842 .clk (rx_inclock), .areset (rx_pll_aclr_pulldown),
18843 .clk0 (w_rx_inclk0), .clk1 (), .locked (i_pll_locked) );
18845 pll.clk0_multiply_by = inclock_boost,
18846 pll.input_frequency = inclock_period;
18848 //----------------------------------------------------------
18849 // Instantiate HSSI_FIFOs
18852 .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[00]),
18853 .clk0 (w_rx_clkout[00]), .datain (w_rx_out00),
18854 .we (vcc), .reset (rx_aclr_pulldown),
18855 .overflow (i_rx_full[00]), .empty (i_rx_empty[00]),
18856 .dataout (i_fifo_out00) );
18858 fifo00.channel_width = deserialization_factor;
18861 .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[01]),
18862 .clk0 (w_rx_clkout[01]), .datain (w_rx_out01),
18863 .we (vcc), .reset (rx_aclr_pulldown),
18864 .overflow (i_rx_full[01]), .empty (i_rx_empty[01]),
18865 .dataout (i_fifo_out01) );
18867 fifo01.channel_width = deserialization_factor;
18870 .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[02]),
18871 .clk0 (w_rx_clkout[02]), .datain (w_rx_out02),
18872 .we (vcc), .reset (rx_aclr_pulldown),
18873 .overflow (i_rx_full[02]), .empty (i_rx_empty[02]),
18874 .dataout (i_fifo_out02) );
18876 fifo02.channel_width = deserialization_factor;
18879 .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[03]),
18880 .clk0 (w_rx_clkout[03]), .datain (w_rx_out03),
18881 .we (vcc), .reset (rx_aclr_pulldown),
18882 .overflow (i_rx_full[03]), .empty (i_rx_empty[03]),
18883 .dataout (i_fifo_out03) );
18885 fifo03.channel_width = deserialization_factor;
18888 .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[04]),
18889 .clk0 (w_rx_clkout[04]), .datain (w_rx_out04),
18890 .we (vcc), .reset (rx_aclr_pulldown),
18891 .overflow (i_rx_full[04]), .empty (i_rx_empty[04]),
18892 .dataout (i_fifo_out04) );
18894 fifo04.channel_width = deserialization_factor;
18897 .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[05]),
18898 .clk0 (w_rx_clkout[05]), .datain (w_rx_out05),
18899 .we (vcc), .reset (rx_aclr_pulldown),
18900 .overflow (i_rx_full[05]), .empty (i_rx_empty[05]),
18901 .dataout (i_fifo_out05) );
18903 fifo05.channel_width = deserialization_factor;
18906 .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[06]),
18907 .clk0 (w_rx_clkout[06]), .datain (w_rx_out06),
18908 .we (vcc), .reset (rx_aclr_pulldown),
18909 .overflow (i_rx_full[06]), .empty (i_rx_empty[06]),
18910 .dataout (i_fifo_out06) );
18912 fifo06.channel_width = deserialization_factor;
18915 .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[07]),
18916 .clk0 (w_rx_clkout[07]), .datain (w_rx_out07),
18917 .we (vcc), .reset (rx_aclr_pulldown),
18918 .overflow (i_rx_full[07]), .empty (i_rx_empty[07]),
18919 .dataout (i_fifo_out07) );
18921 fifo07.channel_width = deserialization_factor;
18924 .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[08]),
18925 .clk0 (w_rx_clkout[08]), .datain (w_rx_out08),
18926 .we (vcc), .reset (rx_aclr_pulldown),
18927 .overflow (i_rx_full[08]), .empty (i_rx_empty[08]),
18928 .dataout (i_fifo_out08) );
18930 fifo08.channel_width = deserialization_factor;
18933 .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[09]),
18934 .clk0 (w_rx_clkout[09]), .datain (w_rx_out09),
18935 .we (vcc), .reset (rx_aclr_pulldown),
18936 .overflow (i_rx_full[09]), .empty (i_rx_empty[09]),
18937 .dataout (i_fifo_out09) );
18939 fifo09.channel_width = deserialization_factor;
18942 .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[10]),
18943 .clk0 (w_rx_clkout[10]), .datain (w_rx_out10),
18944 .we (vcc), .reset (rx_aclr_pulldown),
18945 .overflow (i_rx_full[10]), .empty (i_rx_empty[10]),
18946 .dataout (i_fifo_out10) );
18948 fifo10.channel_width = deserialization_factor;
18951 .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[11]),
18952 .clk0 (w_rx_clkout[11]), .datain (w_rx_out11),
18953 .we (vcc), .reset (rx_aclr_pulldown),
18954 .overflow (i_rx_full[11]), .empty (i_rx_empty[11]),
18955 .dataout (i_fifo_out11) );
18957 fifo11.channel_width = deserialization_factor;
18960 .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[12]),
18961 .clk0 (w_rx_clkout[12]), .datain (w_rx_out12),
18962 .we (vcc), .reset (rx_aclr_pulldown),
18963 .overflow (i_rx_full[12]), .empty (i_rx_empty[12]),
18964 .dataout (i_fifo_out12) );
18966 fifo12.channel_width = deserialization_factor;
18969 .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[13]),
18970 .clk0 (w_rx_clkout[13]), .datain (w_rx_out13),
18971 .we (vcc), .reset (rx_aclr_pulldown),
18972 .overflow (i_rx_full[13]), .empty (i_rx_empty[13]),
18973 .dataout (i_fifo_out13) );
18975 fifo13.channel_width = deserialization_factor;
18978 .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[14]),
18979 .clk0 (w_rx_clkout[14]), .datain (w_rx_out14),
18980 .we (vcc), .reset (rx_aclr_pulldown),
18981 .overflow (i_rx_full[14]), .empty (i_rx_empty[14]),
18982 .dataout (i_fifo_out14) );
18984 fifo14.channel_width = deserialization_factor;
18987 .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[15]),
18988 .clk0 (w_rx_clkout[15]), .datain (w_rx_out15),
18989 .we (vcc), .reset (rx_aclr_pulldown),
18990 .overflow (i_rx_full[15]), .empty (i_rx_empty[15]),
18991 .dataout (i_fifo_out15) );
18993 fifo15.channel_width = deserialization_factor;
18996 .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[16]),
18997 .clk0 (w_rx_clkout[16]), .datain (w_rx_out16),
18998 .we (vcc), .reset (rx_aclr_pulldown),
18999 .overflow (i_rx_full[16]), .empty (i_rx_empty[16]),
19000 .dataout (i_fifo_out16) );
19002 fifo16.channel_width = deserialization_factor;
19005 .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[17]),
19006 .clk0 (w_rx_clkout[17]), .datain (w_rx_out17),
19007 .we (vcc), .reset (rx_aclr_pulldown),
19008 .overflow (i_rx_full[17]), .empty (i_rx_empty[17]),
19009 .dataout (i_fifo_out17) );
19011 fifo17.channel_width = deserialization_factor;
19014 //--------------------------
19016 assign i_rx_in[number_of_channels - 1 : 0] = rx_in[number_of_channels - 1 : 0];
19018 //--------------------------
19020 // assign FIFO outputs to i_rx_out wire - for the case when FIFO is not bypassed
19021 assign i_rx_out[01*deserialization_factor-1:00*deserialization_factor]
19023 assign i_rx_out[02*deserialization_factor-1:01*deserialization_factor]
19025 assign i_rx_out[03*deserialization_factor-1:02*deserialization_factor]
19027 assign i_rx_out[04*deserialization_factor-1:03*deserialization_factor]
19029 assign i_rx_out[05*deserialization_factor-1:04*deserialization_factor]
19031 assign i_rx_out[06*deserialization_factor-1:05*deserialization_factor]
19033 assign i_rx_out[07*deserialization_factor-1:06*deserialization_factor]
19035 assign i_rx_out[08*deserialization_factor-1:07*deserialization_factor]
19037 assign i_rx_out[09*deserialization_factor-1:08*deserialization_factor]
19039 assign i_rx_out[10*deserialization_factor-1:09*deserialization_factor]
19041 assign i_rx_out[11*deserialization_factor-1:10*deserialization_factor]
19043 assign i_rx_out[12*deserialization_factor-1:11*deserialization_factor]
19045 assign i_rx_out[13*deserialization_factor-1:12*deserialization_factor]
19047 assign i_rx_out[14*deserialization_factor-1:13*deserialization_factor]
19049 assign i_rx_out[15*deserialization_factor-1:14*deserialization_factor]
19051 assign i_rx_out[16*deserialization_factor-1:15*deserialization_factor]
19053 assign i_rx_out[17*deserialization_factor-1:16*deserialization_factor]
19055 assign i_rx_out[18*deserialization_factor-1:17*deserialization_factor]
19058 // assign RX outputs to i_w_rx_out wire - for the case when FIFO is bypassed
19059 assign i_w_rx_out[01*deserialization_factor-1:00*deserialization_factor]
19061 assign i_w_rx_out[02*deserialization_factor-1:01*deserialization_factor]
19063 assign i_w_rx_out[03*deserialization_factor-1:02*deserialization_factor]
19065 assign i_w_rx_out[04*deserialization_factor-1:03*deserialization_factor]
19067 assign i_w_rx_out[05*deserialization_factor-1:04*deserialization_factor]
19069 assign i_w_rx_out[06*deserialization_factor-1:05*deserialization_factor]
19071 assign i_w_rx_out[07*deserialization_factor-1:06*deserialization_factor]
19073 assign i_w_rx_out[08*deserialization_factor-1:07*deserialization_factor]
19075 assign i_w_rx_out[09*deserialization_factor-1:08*deserialization_factor]
19077 assign i_w_rx_out[10*deserialization_factor-1:09*deserialization_factor]
19079 assign i_w_rx_out[11*deserialization_factor-1:10*deserialization_factor]
19081 assign i_w_rx_out[12*deserialization_factor-1:11*deserialization_factor]
19083 assign i_w_rx_out[13*deserialization_factor-1:12*deserialization_factor]
19085 assign i_w_rx_out[14*deserialization_factor-1:13*deserialization_factor]
19087 assign i_w_rx_out[15*deserialization_factor-1:14*deserialization_factor]
19089 assign i_w_rx_out[16*deserialization_factor-1:15*deserialization_factor]
19091 assign i_w_rx_out[17*deserialization_factor-1:16*deserialization_factor]
19093 assign i_w_rx_out[18*deserialization_factor-1:17*deserialization_factor]
19096 // assign the correct signals to the output ports
19097 assign rx_out = (deserialization_factor == 1) ? rx_in :
19098 (bypass_fifo == "OFF") ? i_rx_out[deserialization_factor*number_of_channels-1:0] : i_w_rx_out;
19099 assign rx_outclock = (deserialization_factor > 1) ? w_rx_clkout[00] : rx_inclock;
19100 assign rx_locklost = (deserialization_factor > 1) ? i_rx_locked[number_of_channels-1:0] : {(number_of_channels){1'b1}};
19101 assign rx_full = (deserialization_factor == 1) ? 0 :
19102 (bypass_fifo == "OFF") ? ~ i_rx_full[number_of_channels-1:0] : {number_of_channels{1'bX}};
19103 assign rx_empty = (deserialization_factor == 1) ? 0 :
19104 (bypass_fifo == "OFF") ? ~ i_rx_empty[number_of_channels-1:0] : {number_of_channels{1'bX}};
19105 assign rx_rlv = (deserialization_factor > 1) ? i_rx_rlv : 0;
19106 assign rx_pll_locked = i_pll_locked;
19107 assign rx_rec_clk = w_rx_clkout;
19109 endmodule // altcdr_rx
19111 // START MODULE NAME -----------------------------------------------------------
19113 // Module Name : ALTCDR_TX
19115 // Description : The Clock Data Recovery (CDR) transmitter behavioral
19116 // model. Consists of CDR transmitter for serialization,
19119 // Limitations : Available for the Mercury device family only
19121 // Expected results : Serial data output (tx_out), generated slow clock
19122 // (tx_clkout), FIFO full signal (tx_full), FIFO empty signal
19123 // (tx_empty), PLL lock signal (tx_pll_locked)
19125 //END MODULE NAME --------------------------------------------------------------
19127 `timescale 1 ps / 1 ps
19129 // MODULE DECLARATION
19131 tx_in, // required port, parallel data input
19132 tx_inclock, // required port, input reference clock
19133 tx_coreclock, // required port, input core clock
19134 tx_aclr, // asynchronous clear for TX and FIFO
19135 tx_pll_aclr, // asynchronous clear for the PLL
19136 tx_fifo_wren, // write enable for the FIFO
19137 tx_out, // serial data output
19138 tx_outclock, // generated slow clock
19139 tx_pll_locked, // PLL lock signal
19140 tx_full, // FIFO full indicator
19141 tx_empty // FIFO empty indicator
19144 // GLOBAL PARAMETER DECLARATION
19145 parameter number_of_channels = 1;
19146 parameter deserialization_factor = 3; // Valid deserialization_factor
19147 parameter inclock_period = 0; // units in ps
19148 parameter inclock_boost = 1;
19149 parameter bypass_fifo = "OFF";
19150 parameter intended_device_family = "MERCURY";
19151 parameter lpm_type = "altcdr_tx";
19152 parameter lpm_hint = "UNUSED";
19154 // LOCAL PARAMETER DECLARATION
19155 parameter MAX_DATA_WIDTH = deserialization_factor - 1;
19157 // INPUT PORT DECLARATION
19158 input [deserialization_factor*number_of_channels-1:0] tx_in;
19160 input tx_coreclock;
19163 input [number_of_channels-1:0] tx_fifo_wren;
19165 // OUTPUT PORT DECLARATION
19166 output [number_of_channels-1:0] tx_out;
19167 output tx_outclock;
19168 output tx_pll_locked;
19169 output [number_of_channels-1:0] tx_full;
19170 output [number_of_channels-1:0] tx_empty;
19172 // Default values for inputs -- pullup/pulldown
19173 tri0 tx_aclr_pulldown;
19174 tri0 tx_pll_aclr_pulldown;
19175 tri1 [17:0] tx_fifo_wren_pullup;
19177 // INTERNAL VARIABLE/REGISTER DECLARATION
19180 wire i_tx_pll_locked;
19181 wire [17:0] i_tx_full;
19182 wire [17:0] i_tx_empty;
19183 wire [17:0] w_tx_out;
19184 wire [17:0] w_tx_clkout;
19185 wire [MAX_DATA_WIDTH:0] txin00;
19186 wire [MAX_DATA_WIDTH:0] txin01;
19187 wire [MAX_DATA_WIDTH:0] txin02;
19188 wire [MAX_DATA_WIDTH:0] txin03;
19189 wire [MAX_DATA_WIDTH:0] txin04;
19190 wire [MAX_DATA_WIDTH:0] txin05;
19191 wire [MAX_DATA_WIDTH:0] txin06;
19192 wire [MAX_DATA_WIDTH:0] txin07;
19193 wire [MAX_DATA_WIDTH:0] txin08;
19194 wire [MAX_DATA_WIDTH:0] txin09;
19195 wire [MAX_DATA_WIDTH:0] txin10;
19196 wire [MAX_DATA_WIDTH:0] txin11;
19197 wire [MAX_DATA_WIDTH:0] txin12;
19198 wire [MAX_DATA_WIDTH:0] txin13;
19199 wire [MAX_DATA_WIDTH:0] txin14;
19200 wire [MAX_DATA_WIDTH:0] txin15;
19201 wire [MAX_DATA_WIDTH:0] txin16;
19202 wire [MAX_DATA_WIDTH:0] txin17;
19203 wire [MAX_DATA_WIDTH:0] i_fifo_out00;
19204 wire [MAX_DATA_WIDTH:0] i_fifo_out01;
19205 wire [MAX_DATA_WIDTH:0] i_fifo_out02;
19206 wire [MAX_DATA_WIDTH:0] i_fifo_out03;
19207 wire [MAX_DATA_WIDTH:0] i_fifo_out04;
19208 wire [MAX_DATA_WIDTH:0] i_fifo_out05;
19209 wire [MAX_DATA_WIDTH:0] i_fifo_out06;
19210 wire [MAX_DATA_WIDTH:0] i_fifo_out07;
19211 wire [MAX_DATA_WIDTH:0] i_fifo_out08;
19212 wire [MAX_DATA_WIDTH:0] i_fifo_out09;
19213 wire [MAX_DATA_WIDTH:0] i_fifo_out10;
19214 wire [MAX_DATA_WIDTH:0] i_fifo_out11;
19215 wire [MAX_DATA_WIDTH:0] i_fifo_out12;
19216 wire [MAX_DATA_WIDTH:0] i_fifo_out13;
19217 wire [MAX_DATA_WIDTH:0] i_fifo_out14;
19218 wire [MAX_DATA_WIDTH:0] i_fifo_out15;
19219 wire [MAX_DATA_WIDTH:0] i_fifo_out16;
19220 wire [MAX_DATA_WIDTH:0] i_fifo_out17;
19221 wire [MAX_DATA_WIDTH:0] i_tx_in00;
19222 wire [MAX_DATA_WIDTH:0] i_tx_in01;
19223 wire [MAX_DATA_WIDTH:0] i_tx_in02;
19224 wire [MAX_DATA_WIDTH:0] i_tx_in03;
19225 wire [MAX_DATA_WIDTH:0] i_tx_in04;
19226 wire [MAX_DATA_WIDTH:0] i_tx_in05;
19227 wire [MAX_DATA_WIDTH:0] i_tx_in06;
19228 wire [MAX_DATA_WIDTH:0] i_tx_in07;
19229 wire [MAX_DATA_WIDTH:0] i_tx_in08;
19230 wire [MAX_DATA_WIDTH:0] i_tx_in09;
19231 wire [MAX_DATA_WIDTH:0] i_tx_in10;
19232 wire [MAX_DATA_WIDTH:0] i_tx_in11;
19233 wire [MAX_DATA_WIDTH:0] i_tx_in12;
19234 wire [MAX_DATA_WIDTH:0] i_tx_in13;
19235 wire [MAX_DATA_WIDTH:0] i_tx_in14;
19236 wire [MAX_DATA_WIDTH:0] i_tx_in15;
19237 wire [MAX_DATA_WIDTH:0] i_tx_in16;
19238 wire [MAX_DATA_WIDTH:0] i_tx_in17;
19239 wire [359:0] tx_in_int; // 360 = 18 channels * 20 bits (18=maximum number of channels, 20=maximum channel width)
19245 // Begin of parameter checking
19246 if (number_of_channels <= 0)
19248 $display("ERROR: The number_of_channels parameter must be greater than 0");
19252 if (!(((deserialization_factor >= 3 ) && (deserialization_factor <= 12)) ||
19253 (deserialization_factor == 14) || (deserialization_factor == 16) ||
19254 (deserialization_factor == 18) || (deserialization_factor == 20)))
19256 $display("ERROR: Illegal value for deserialization_factor parameter (%d) -- value ", deserialization_factor);
19257 $display(" must be in the range 3 to 12, inclusive, or must be one of 14, 16, 18, or 20");
19262 // End of parameter checking
19268 assign tx_aclr_pulldown = tx_aclr;
19269 assign tx_pll_aclr_pulldown = tx_pll_aclr;
19270 assign tx_fifo_wren_pullup = tx_fifo_wren;
19272 // COMPONENT INSTANTIATION
19274 //-------------------------------------------------------------
19275 // Instantiate HSSI_TX - maximum of 18 channels
19277 .datain (txin00), .clk (w_tx_clk), .areset (tx_aclr_pulldown),
19278 .dataout (w_tx_out[00]), .clkout (w_tx_clkout[00]) );
19280 tx00.channel_width = deserialization_factor;
19283 .datain (txin01), .clk (w_tx_clk), .areset (tx_aclr_pulldown),
19284 .dataout (w_tx_out[01]), .clkout (w_tx_clkout[01]) );
19286 tx01.channel_width = deserialization_factor;
19289 .datain (txin02), .clk (w_tx_clk), .areset (tx_aclr_pulldown),
19290 .dataout (w_tx_out[02]), .clkout (w_tx_clkout[02]) );
19292 tx02.channel_width = deserialization_factor;
19295 .datain (txin03), .clk (w_tx_clk), .areset (tx_aclr_pulldown),
19296 .dataout (w_tx_out[03]), .clkout (w_tx_clkout[03]) );
19298 tx03.channel_width = deserialization_factor;
19301 .datain (txin04), .clk (w_tx_clk), .areset (tx_aclr_pulldown),
19302 .dataout (w_tx_out[04]), .clkout (w_tx_clkout[04]) );
19304 tx04.channel_width = deserialization_factor;
19307 .datain (txin05), .clk (w_tx_clk), .areset (tx_aclr_pulldown),
19308 .dataout (w_tx_out[05]), .clkout (w_tx_clkout[05]) );
19310 tx05.channel_width = deserialization_factor;
19313 .datain (txin06), .clk (w_tx_clk), .areset (tx_aclr_pulldown),
19314 .dataout (w_tx_out[06]), .clkout (w_tx_clkout[06]) );
19316 tx06.channel_width = deserialization_factor;
19319 .datain (txin07), .clk (w_tx_clk), .areset (tx_aclr_pulldown),
19320 .dataout (w_tx_out[07]), .clkout (w_tx_clkout[07]) );
19322 tx07.channel_width = deserialization_factor;
19325 .datain (txin08), .clk (w_tx_clk), .areset (tx_aclr_pulldown),
19326 .dataout (w_tx_out[08]), .clkout (w_tx_clkout[08]) );
19328 tx08.channel_width = deserialization_factor;
19331 .datain (txin09), .clk (w_tx_clk), .areset (tx_aclr_pulldown),
19332 .dataout (w_tx_out[09]), .clkout (w_tx_clkout[09]) );
19334 tx09.channel_width = deserialization_factor;
19337 .datain (txin10), .clk (w_tx_clk), .areset (tx_aclr_pulldown),
19338 .dataout (w_tx_out[10]), .clkout (w_tx_clkout[10]) );
19340 tx10.channel_width = deserialization_factor;
19343 .datain (txin11), .clk (w_tx_clk), .areset (tx_aclr_pulldown),
19344 .dataout (w_tx_out[11]), .clkout (w_tx_clkout[11]) );
19346 tx11.channel_width = deserialization_factor;
19349 .datain (txin12), .clk (w_tx_clk), .areset (tx_aclr_pulldown),
19350 .dataout (w_tx_out[12]), .clkout (w_tx_clkout[12]) );
19352 tx12.channel_width = deserialization_factor;
19355 .datain (txin13), .clk (w_tx_clk), .areset (tx_aclr_pulldown),
19356 .dataout (w_tx_out[13]), .clkout (w_tx_clkout[13]) );
19358 tx13.channel_width = deserialization_factor;
19361 .datain (txin14), .clk (w_tx_clk), .areset (tx_aclr_pulldown),
19362 .dataout (w_tx_out[14]), .clkout (w_tx_clkout[14]) );
19364 tx14.channel_width = deserialization_factor;
19367 .datain (txin15), .clk (w_tx_clk), .areset (tx_aclr_pulldown),
19368 .dataout (w_tx_out[15]), .clkout (w_tx_clkout[15]) );
19370 tx15.channel_width = deserialization_factor;
19373 .datain (txin16), .clk (w_tx_clk), .areset (tx_aclr_pulldown),
19374 .dataout (w_tx_out[16]), .clkout (w_tx_clkout[16]) );
19376 tx16.channel_width = deserialization_factor;
19379 .datain (txin17), .clk (w_tx_clk), .areset (tx_aclr_pulldown),
19380 .dataout (w_tx_out[17]), .clkout (w_tx_clkout[17]) );
19382 tx17.channel_width = deserialization_factor;
19385 //---------------------------------------------------------
19386 // Instantiate HSSI_PLL - use the same PLL for all channels
19389 .clk (tx_inclock), .areset (tx_pll_aclr_pulldown),
19390 .clk0 (w_tx_clk), .clk1 (w_tx_clk1), .locked (i_tx_pll_locked) );
19392 pll0.clk0_multiply_by = inclock_boost,
19393 pll0.input_frequency = inclock_period;
19396 //--------------------------------------------------------
19397 // Instantiate HSSI_FIFO - maximum of 18 channels
19400 .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[00]),
19401 .reset (tx_aclr_pulldown), .re (1'b1),
19402 .clk1 (w_tx_clkout[00]), .datain (i_tx_in00),
19403 .overflow (i_tx_full[00]), .empty (i_tx_empty[00]),
19404 .dataout (i_fifo_out00) );
19406 fifo00.channel_width = deserialization_factor;
19409 .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[01]),
19410 .reset (tx_aclr_pulldown), .re (1'b1),
19411 .clk1 (w_tx_clkout[01]), .datain (i_tx_in01),
19412 .overflow (i_tx_full[01]), .empty (i_tx_empty[01]),
19413 .dataout (i_fifo_out01) );
19415 fifo01.channel_width = deserialization_factor;
19418 .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[02]),
19419 .reset (tx_aclr_pulldown), .re (1'b1),
19420 .clk1 (w_tx_clkout[02]), .datain (i_tx_in02),
19421 .overflow (i_tx_full[02]), .empty (i_tx_empty[02]),
19422 .dataout (i_fifo_out02) );
19424 fifo02.channel_width = deserialization_factor;
19427 .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[03]),
19428 .reset (tx_aclr_pulldown), .re (1'b1),
19429 .clk1 (w_tx_clkout[03]), .datain (i_tx_in03),
19430 .overflow (i_tx_full[03]), .empty (i_tx_empty[03]),
19431 .dataout (i_fifo_out03) );
19433 fifo03.channel_width = deserialization_factor;
19436 .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[04]),
19437 .reset (tx_aclr_pulldown), .re (1'b1),
19438 .clk1 (w_tx_clkout[04]), .datain (i_tx_in04),
19439 .overflow (i_tx_full[04]), .empty (i_tx_empty[04]),
19440 .dataout (i_fifo_out04) );
19442 fifo04.channel_width = deserialization_factor;
19445 .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[05]),
19446 .reset (tx_aclr_pulldown), .re (1'b1),
19447 .clk1 (w_tx_clkout[05]), .datain (i_tx_in05),
19448 .overflow (i_tx_full[05]), .empty (i_tx_empty[05]),
19449 .dataout (i_fifo_out05) );
19451 fifo05.channel_width = deserialization_factor;
19454 .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[06]),
19455 .reset (tx_aclr_pulldown), .re (1'b1),
19456 .clk1 (w_tx_clkout[06]), .datain (i_tx_in06),
19457 .overflow (i_tx_full[06]), .empty (i_tx_empty[06]),
19458 .dataout (i_fifo_out06) );
19460 fifo06.channel_width = deserialization_factor;
19463 .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[07]),
19464 .reset (tx_aclr_pulldown), .re (1'b1),
19465 .clk1 (w_tx_clkout[07]), .datain (i_tx_in07),
19466 .overflow (i_tx_full[07]), .empty (i_tx_empty[07]),
19467 .dataout (i_fifo_out07) );
19469 fifo07.channel_width = deserialization_factor;
19472 .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[08]),
19473 .reset (tx_aclr_pulldown), .re (1'b1),
19474 .clk1 (w_tx_clkout[08]), .datain (i_tx_in08),
19475 .overflow (i_tx_full[08]), .empty (i_tx_empty[08]),
19476 .dataout (i_fifo_out08) );
19478 fifo08.channel_width = deserialization_factor;
19481 .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[09]),
19482 .reset (tx_aclr_pulldown), .re (1'b1),
19483 .clk1 (w_tx_clkout[09]), .datain (i_tx_in09),
19484 .overflow (i_tx_full[09]), .empty (i_tx_empty[09]),
19485 .dataout (i_fifo_out09) );
19487 fifo09.channel_width = deserialization_factor;
19490 .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[10]),
19491 .reset (tx_aclr_pulldown), .re (1'b1),
19492 .clk1 (w_tx_clkout[10]), .datain (i_tx_in10),
19493 .overflow (i_tx_full[10]), .empty (i_tx_empty[10]),
19494 .dataout (i_fifo_out10) );
19496 fifo10.channel_width = deserialization_factor;
19499 .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[11]),
19500 .reset (tx_aclr_pulldown), .re (1'b1),
19501 .clk1 (w_tx_clkout[11]), .datain (i_tx_in11),
19502 .overflow (i_tx_full[11]), .empty (i_tx_empty[11]),
19503 .dataout (i_fifo_out11) );
19505 fifo11.channel_width = deserialization_factor;
19508 .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[12]),
19509 .reset (tx_aclr_pulldown), .re (1'b1),
19510 .clk1 (w_tx_clkout[12]), .datain (i_tx_in12),
19511 .overflow (i_tx_full[12]), .empty (i_tx_empty[12]),
19512 .dataout (i_fifo_out12) );
19514 fifo12.channel_width = deserialization_factor;
19517 .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[13]),
19518 .reset (tx_aclr_pulldown), .re (1'b1),
19519 .clk1 (w_tx_clkout[13]), .datain (i_tx_in13),
19520 .overflow (i_tx_full[13]), .empty (i_tx_empty[13]),
19521 .dataout (i_fifo_out13) );
19523 fifo13.channel_width = deserialization_factor;
19526 .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[14]),
19527 .reset (tx_aclr_pulldown), .re (1'b1),
19528 .clk1 (w_tx_clkout[14]), .datain (i_tx_in14),
19529 .overflow (i_tx_full[14]), .empty (i_tx_empty[14]),
19530 .dataout (i_fifo_out14) );
19532 fifo14.channel_width = deserialization_factor;
19535 .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[15]),
19536 .reset (tx_aclr_pulldown), .re (1'b1),
19537 .clk1 (w_tx_clkout[15]), .datain (i_tx_in15),
19538 .overflow (i_tx_full[15]), .empty (i_tx_empty[15]),
19539 .dataout (i_fifo_out15) );
19541 fifo15.channel_width = deserialization_factor;
19544 .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[16]),
19545 .reset (tx_aclr_pulldown), .re (1'b1),
19546 .clk1 (w_tx_clkout[16]), .datain (i_tx_in16),
19547 .overflow (i_tx_full[16]), .empty (i_tx_empty[16]),
19548 .dataout (i_fifo_out16) );
19550 fifo16.channel_width = deserialization_factor;
19553 .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[17]),
19554 .reset (tx_aclr_pulldown), .re (1'b1),
19555 .clk1 (w_tx_clkout[17]), .datain (i_tx_in17),
19556 .overflow (i_tx_full[17]), .empty (i_tx_empty[17]),
19557 .dataout (i_fifo_out17) );
19559 fifo17.channel_width = deserialization_factor;
19562 //--------------------------
19565 assign tx_in_int[deserialization_factor*number_of_channels-1: 0] =
19566 tx_in[deserialization_factor*number_of_channels-1:0];
19569 tx_in_int[(01*deserialization_factor)-1:00*deserialization_factor];
19571 tx_in_int[(02*deserialization_factor)-1:01*deserialization_factor];
19573 tx_in_int[(03*deserialization_factor)-1:02*deserialization_factor];
19575 tx_in_int[(04*deserialization_factor)-1:03*deserialization_factor];
19577 tx_in_int[(05*deserialization_factor)-1:04*deserialization_factor];
19579 tx_in_int[(06*deserialization_factor)-1:05*deserialization_factor];
19581 tx_in_int[(07*deserialization_factor)-1:06*deserialization_factor];
19583 tx_in_int[(08*deserialization_factor)-1:07*deserialization_factor];
19585 tx_in_int[(09*deserialization_factor)-1:08*deserialization_factor];
19587 tx_in_int[(10*deserialization_factor)-1:09*deserialization_factor];
19589 tx_in_int[(11*deserialization_factor)-1:10*deserialization_factor];
19591 tx_in_int[(12*deserialization_factor)-1:11*deserialization_factor];
19593 tx_in_int[(13*deserialization_factor)-1:12*deserialization_factor];
19595 tx_in_int[(14*deserialization_factor)-1:13*deserialization_factor];
19597 tx_in_int[(15*deserialization_factor)-1:14*deserialization_factor];
19599 tx_in_int[(16*deserialization_factor)-1:15*deserialization_factor];
19601 tx_in_int[(17*deserialization_factor)-1:16*deserialization_factor];
19603 tx_in_int[(18*deserialization_factor)-1:17*deserialization_factor];
19606 //------------------------------------------------------------------
19607 // select the input for hssi_tx - from FIFO or from data input directly
19608 assign txin00 = (bypass_fifo == "OFF") ? i_fifo_out00 : i_tx_in00;
19609 assign txin01 = (bypass_fifo == "OFF") ? i_fifo_out01 : i_tx_in01;
19610 assign txin02 = (bypass_fifo == "OFF") ? i_fifo_out02 : i_tx_in02;
19611 assign txin03 = (bypass_fifo == "OFF") ? i_fifo_out03 : i_tx_in03;
19612 assign txin04 = (bypass_fifo == "OFF") ? i_fifo_out04 : i_tx_in04;
19613 assign txin05 = (bypass_fifo == "OFF") ? i_fifo_out05 : i_tx_in05;
19614 assign txin06 = (bypass_fifo == "OFF") ? i_fifo_out06 : i_tx_in06;
19615 assign txin07 = (bypass_fifo == "OFF") ? i_fifo_out07 : i_tx_in07;
19616 assign txin08 = (bypass_fifo == "OFF") ? i_fifo_out08 : i_tx_in08;
19617 assign txin09 = (bypass_fifo == "OFF") ? i_fifo_out09 : i_tx_in09;
19618 assign txin10 = (bypass_fifo == "OFF") ? i_fifo_out10 : i_tx_in10;
19619 assign txin11 = (bypass_fifo == "OFF") ? i_fifo_out11 : i_tx_in11;
19620 assign txin12 = (bypass_fifo == "OFF") ? i_fifo_out12 : i_tx_in12;
19621 assign txin13 = (bypass_fifo == "OFF") ? i_fifo_out13 : i_tx_in13;
19622 assign txin14 = (bypass_fifo == "OFF") ? i_fifo_out14 : i_tx_in14;
19623 assign txin15 = (bypass_fifo == "OFF") ? i_fifo_out15 : i_tx_in15;
19624 assign txin16 = (bypass_fifo == "OFF") ? i_fifo_out16 : i_tx_in16;
19625 assign txin17 = (bypass_fifo == "OFF") ? i_fifo_out17 : i_tx_in17;
19627 //-----------------------------------------------
19628 // assign the correct signals to the output ports
19630 assign tx_out = (deserialization_factor > 1) ?
19631 w_tx_out[number_of_channels-1:0]
19634 assign tx_outclock = (deserialization_factor > 1) ?
19638 assign tx_full = (deserialization_factor == 1) ?
19640 : (bypass_fifo == "OFF") ?
19641 ~i_tx_full[number_of_channels-1:0]
19642 : {number_of_channels{1'bX}};
19644 assign tx_empty = (deserialization_factor == 1) ?
19646 : (bypass_fifo == "OFF") ?
19647 ~i_tx_empty[number_of_channels-1:0]
19648 : {number_of_channels{1'bX}};
19650 assign tx_pll_locked = i_tx_pll_locked;
19652 endmodule // altcdr_tx
19654 //START_MODULE_NAME----------------------------------------------------
19656 // Module Name : altlvds_rx
19658 // Description : Low Voltage Differential Signaling (LVDS) receiver
19659 // megafunction. The altlvds_rx megafunction implements a
19660 // deserialization receiver. LVDS is a high speed IO interface
19661 // that uses inputs without a reference voltage. LVDS uses
19662 // two wires carrying differential values to create a single
19663 // channel. These wires are connected to two pins on
19664 // supported device to create a single LVDS channel
19666 // Limitation : Only available for APEX20KE, APEXII, MERCURY, STRATIX,
19667 // STRATIX GX, Stratix II, Cyclone and Cyclone II families.
19669 // Results expected: output clock, deserialized output data and pll locked
19672 //END_MODULE_NAME----------------------------------------------------
19674 // BEGINNING OF MODULE
19675 `timescale 1 ps / 1 ps
19677 // MODULE DECLARATION
19678 module altlvds_rx (
19690 rx_channel_data_align,
19701 // GLOBAL PARAMETER DECLARATION
19702 parameter number_of_channels = 1;
19703 parameter deserialization_factor = 4;
19704 parameter registered_output = "ON";
19705 parameter inclock_period = 10000;
19706 parameter inclock_boost = deserialization_factor;
19707 parameter cds_mode = "UNUSED";
19708 parameter intended_device_family = "APEX20KE";
19709 parameter input_data_rate =0;
19710 parameter inclock_data_alignment = "EDGE_ALIGNED";
19711 parameter registered_data_align_input = "ON";
19712 parameter common_rx_tx_pll = "ON";
19713 parameter enable_dpa_mode = "OFF";
19714 parameter enable_dpa_fifo = "ON";
19715 parameter use_dpll_rawperror = "OFF";
19716 parameter use_coreclock_input = "OFF";
19717 parameter dpll_lock_count = 0;
19718 parameter dpll_lock_window = 0;
19719 parameter outclock_resource = "AUTO";
19720 parameter data_align_rollover = deserialization_factor;
19721 parameter lose_lock_on_one_change ="OFF" ;
19722 parameter reset_fifo_at_first_lock ="ON" ;
19723 parameter use_external_pll = "OFF";
19724 parameter implement_in_les = "OFF";
19725 parameter port_rx_data_align = "PORT_CONNECTIVITY";
19726 parameter lpm_hint = "UNUSED";
19727 parameter lpm_type = "altlvds_rx";
19729 // Specifies whether the source of the input clock is from a PLL
19730 parameter clk_src_is_pll = "off";
19732 // LOCAL PARAMETER DECLARATION
19734 // A APEX20KE type of LVDS?
19735 parameter APEX20KE_RX_STYLE = ((intended_device_family == "APEX20KE") ||
19736 (intended_device_family == "APEX20KC") ||
19737 (intended_device_family == "EXCALIBUR_ARM") ||
19738 (intended_device_family == "EXCALIBUR_MIPS"))
19741 // A APEXII type of LVDS?
19742 parameter APEXII_RX_STYLE = ((intended_device_family == "APEXII") ||
19743 (intended_device_family == "APEX II"))
19746 // A MERCURY type of LVDS?
19747 parameter MERCURY_RX_STYLE = ((intended_device_family == "MERCURY") ||
19748 (intended_device_family == "Mercury"))
19751 // A STRATIX type of LVDS?
19752 parameter STRATIX_RX_STYLE = (((intended_device_family == "Stratix") ||
19753 (intended_device_family == "STRATIX") ||
19754 (intended_device_family == "HardCopy Stratix") ||
19755 (intended_device_family == "HARDCOPY STRATIX") ||
19756 (intended_device_family == "hardcopy stratix") ||
19757 (intended_device_family == "HardcopyStratix") ||
19758 (intended_device_family == "HARDCOPYSTRATIX") ||
19759 (intended_device_family == "hardcopystratix")) ||
19760 (((intended_device_family == "STRATIXGX") ||
19761 (intended_device_family == "STRATIX-GX") ||
19762 (intended_device_family == "Stratix GX")) &&
19763 (enable_dpa_mode == "OFF")))
19766 // A STRATIXGX DPA type of LVDS?
19767 parameter STRATIXGX_DPA_RX_STYLE =
19768 (((intended_device_family == "STRATIXGX") ||
19769 (intended_device_family == "STRATIX-GX") ||
19770 (intended_device_family == "Stratix GX")) &&
19771 (enable_dpa_mode == "ON"))
19774 // A STRATIX II type of LVDS?
19775 parameter STRATIXII_RX_STYLE = ((intended_device_family == "Stratix II") ||
19776 (intended_device_family == "StratixII") ||
19777 (intended_device_family == "HardCopy II") ||
19778 (intended_device_family == "HardCopyII") ||
19779 (intended_device_family == "HARDCOPY II") ||
19780 (intended_device_family == "HARDCOPYII") ||
19781 (intended_device_family == "hardcopy ii") ||
19782 (intended_device_family == "hardcopyii") ||
19783 (intended_device_family == "Stratix II GX") ||
19784 (intended_device_family == "STRATIX II GX") ||
19785 (intended_device_family == "stratix ii gx") ||
19786 (intended_device_family == "StratixIIGX") ||
19787 (intended_device_family == "STRATIXIIGX") ||
19788 (intended_device_family == "stratixiigx"))
19791 // A Cyclone type of LVDS?
19792 parameter CYCLONE_RX_STYLE = ((intended_device_family == "Cyclone") ||
19793 (intended_device_family == "CYCLONE") ||
19794 (intended_device_family == "cyclone"))
19797 // A Cyclone II type of LVDS?
19798 parameter CYCLONEII_RX_STYLE = ((intended_device_family == "Cyclone II") ||
19799 (intended_device_family == "CYCLONE II") ||
19800 (intended_device_family == "cyclone ii") ||
19801 (intended_device_family == "Cycloneii") ||
19802 (intended_device_family == "CYCLONEII") ||
19803 (intended_device_family == "cycloneii"))
19806 // Is the device family has flexible LVDS?
19807 parameter FAMILY_HAS_FLEXIBLE_LVDS = ((CYCLONE_RX_STYLE == 1) ||
19808 (CYCLONEII_RX_STYLE == 1) ||
19809 (((STRATIX_RX_STYLE == 1) ||
19810 (STRATIXII_RX_STYLE == 1)) &&
19811 (implement_in_les == "ON")))
19814 // Is the family has Stratix style PLL
19815 parameter FAMILY_HAS_STRATIX_STYLE_PLL = ((STRATIX_RX_STYLE == 1) ||
19816 (STRATIXGX_DPA_RX_STYLE == 1) ||
19817 (CYCLONE_RX_STYLE == 1))
19820 // Is the family has Stratix style PLL
19821 parameter FAMILY_HAS_STRATIXII_STYLE_PLL = ((STRATIXII_RX_STYLE == 1) ||
19822 (CYCLONEII_RX_STYLE == 1))
19825 // Parameter to check whether the selected lvds trasmitter use hold register
19827 parameter RX_NEED_HOLD_REG = (((APEX20KE_RX_STYLE == 1) &&
19828 (deserialization_factor == 4 )) ||
19829 ((APEXII_RX_STYLE == 1) &&
19830 (deserialization_factor == 4)) ||
19831 ((MERCURY_RX_STYLE == 1) &&
19832 (deserialization_factor > 2) &&
19833 (deserialization_factor < 7)))
19836 // calculate clock boost for device family other than STRATIX, STRATIX GX
19838 parameter INT_CLOCK_BOOST = (APEX20KE_RX_STYLE == 1)
19839 ? deserialization_factor :
19840 ( (inclock_boost == 0)
19841 ? deserialization_factor
19844 // M value for stratix/stratix II/Cyclone/Cyclone II PLL
19845 parameter PLL_M_VALUE = (((input_data_rate * inclock_period)
19846 + (5 * 100000)) / 1000000);
19848 // D value for Stratix/Stratix II/Cyclone/Cyclone II PLL
19849 parameter PLL_D_VALUE = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
19850 ? ((input_data_rate !=0) && (inclock_period !=0)
19855 // calculate clock boost for STRATIX, STRATIX GX and STRATIX II
19856 parameter STRATIX_INCLOCK_BOOST = ((input_data_rate !=0) &&
19857 (inclock_period !=0))
19859 ((inclock_boost == 0)
19860 ? deserialization_factor
19863 // phase_shift delay. Add 0.5 to the calculated result to round up result to
19864 // the nearest integer.
19865 parameter PHASE_SHIFT =
19866 (inclock_data_alignment == "EDGE_ALIGNED")
19868 (inclock_data_alignment == "CENTER_ALIGNED")
19869 ? (0.5 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5 :
19870 (inclock_data_alignment == "45_DEGREES")
19871 ? (0.125 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5 :
19872 (inclock_data_alignment == "90_DEGREES")
19873 ? (0.25 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5 :
19874 (inclock_data_alignment == "135_DEGREES")
19875 ? (0.375 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5 :
19876 (inclock_data_alignment == "180_DEGREES")
19877 ? (0.5 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5 :
19878 (inclock_data_alignment == "225_DEGREES")
19879 ? (0.625 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5 :
19880 (inclock_data_alignment == "270_DEGREES")
19881 ? (0.75 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5 :
19882 (inclock_data_alignment == "315_DEGREES")
19883 ? (0.875 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5
19886 // parameter for Stratix II inclock phase shift.
19887 parameter STXII_PHASE_SHIFT = PHASE_SHIFT -
19888 (0.5 * inclock_period / STRATIX_INCLOCK_BOOST);
19890 parameter REGISTER_WIDTH = deserialization_factor * number_of_channels;
19892 // input clock period for PLL.
19893 parameter CLOCK_PERIOD = (deserialization_factor > 2)
19897 // INPUT PORT DECLARATION
19898 input [number_of_channels -1 :0] rx_in;
19902 input rx_pll_enable;
19903 input rx_data_align;
19904 input [number_of_channels -1 :0] rx_reset;
19905 input [number_of_channels -1 :0] rx_dpll_reset;
19906 input [number_of_channels -1 :0] rx_dpll_hold;
19907 input [number_of_channels -1 :0] rx_dpll_enable;
19908 input [number_of_channels -1 :0] rx_fifo_reset;
19909 input [number_of_channels -1 :0] rx_channel_data_align;
19910 input [number_of_channels -1 :0] rx_cda_reset;
19911 input [number_of_channels -1 :0] rx_coreclk;
19914 // OUTPUT PORT DECLARATION
19915 output [REGISTER_WIDTH -1: 0] rx_out;
19916 output rx_outclock;
19918 output [number_of_channels -1: 0] rx_dpa_locked;
19919 output [number_of_channels -1: 0] rx_cda_max;
19922 // INTERNAL REGISTERS DECLARATION
19923 reg [REGISTER_WIDTH -1 : 0] pattern;
19924 reg [REGISTER_WIDTH -1 : 0] rx_shift_reg;
19925 reg [REGISTER_WIDTH -1 : 0] rx_parallel_load_reg;
19926 reg [REGISTER_WIDTH -1 : 0] rx_out_reg;
19927 reg [REGISTER_WIDTH -1 : 0] rx_out_hold;
19928 reg [number_of_channels-1 : 0] deskew_done;
19931 reg rx_mercury_slow_clock;
19932 reg [deserialization_factor-1 : 0] temp;
19933 reg [9 : 0] deskew_pattern;
19934 reg [number_of_channels -1 : 0] rx_reg_clk_pre;
19935 reg rx_data_align_reg;
19937 // for x2 mode (deserialization_factor = 2)
19938 reg [REGISTER_WIDTH -1 : 0] rx_ddio_in;
19939 reg [number_of_channels -1 : 0] rx_in_latched;
19941 // INTERNAL WIRE DECLARATION
19942 wire [REGISTER_WIDTH -1 : 0] rx_out_int;
19943 wire [REGISTER_WIDTH -1 : 0] stratix_dataout;
19944 wire [REGISTER_WIDTH -1 : 0] stratixgx_dataout;
19945 wire [REGISTER_WIDTH -1 : 0] stratixii_dataout;
19946 wire [REGISTER_WIDTH -1 : 0] flvds_dataout;
19947 wire [number_of_channels -1 : 0] stratixgx_dpa_locked;
19948 wire [number_of_channels -1 : 0] stratixii_dpa_locked;
19951 wire rx_locked_int;
19952 wire rx_outclk_int;
19954 wire rx_data_align_clk;
19955 wire [number_of_channels -1 : 0] rx_reg_clk;
19956 wire altclklock_inclock;
19957 wire altclklock_fastclk;
19958 wire altclklock_slowclk;
19959 wire altclklock_locked;
19960 wire[1:0] stratix_pll_inclock;
19961 wire[1:0] stratixii_pll_inclock;
19962 wire[5:0] stratix_pll_outclock;
19963 wire[5:0] stratixii_pll_outclock;
19964 wire stratix_pll_enable;
19965 wire stratixii_pll_enable;
19966 wire stratix_pll_areset;
19967 wire stratixii_pll_areset;
19968 wire stratixii_sclkout0;
19969 wire stratixii_sclkout1;
19970 wire stratix_locked;
19971 wire stratixii_locked;
19972 wire stratix_enable0;
19973 wire stratix_enable1;
19974 wire stratixii_enable0;
19975 wire stratixii_enable1;
19977 wire unused_clk_ext;
19978 wire stratix_fastclk;
19979 wire stratix_slowclk;
19980 wire stratixgx_fastclk;
19981 wire stratixgx_slowclk;
19982 wire[number_of_channels -1 :0] stratixgx_coreclk;
19983 wire stratixii_fastclk;
19984 wire stratixii_enable;
19985 wire flvds_fastclk;
19986 wire flvds_slowclk;
19987 wire flvds_syncclk;
19988 wire rx_data_align_int;
19989 wire rx_data_align_pulldown;
19990 wire[number_of_channels -1 :0] rx_channel_data_align_int;
19992 // INTERNAL TRI DECLARATION
19994 tri1 rx_pll_enable;
19995 tri0[number_of_channels -1 :0] rx_reset;
19996 tri0[number_of_channels -1 :0] rx_dpll_reset;
19997 tri0[number_of_channels -1 :0] rx_dpll_hold;
19998 tri1[number_of_channels -1 :0] rx_dpll_enable;
19999 tri0[number_of_channels -1 :0] rx_fifo_reset;
20000 tri0[number_of_channels -1 :0] rx_cda_reset;
20001 tri0[number_of_channels -1 :0] rx_coreclk;
20004 // LOCAL INTEGER DECLARATION
20005 integer count [number_of_channels-1 : 0];
20016 integer posedge_count;
20017 integer negedge_count;
20019 integer start_data;
20020 integer check_deskew_pattern;
20022 // COMPONENT INSTANTIATIONS
20023 ALTERA_DEVICE_FAMILIES dev ();
20025 // FUNCTION DECLARATIONS
20027 // check whether the same pattern is found in the given input data
20028 // for a particular channel.
20029 function pattern_match;
20030 input input_data, deskrew_pattern, dfactor, channel_num;
20031 integer dfactor, channel_num;
20032 reg[(20*10)-1 : 0] input_data;
20033 reg[9 : 0] deskrew_pattern;
20034 reg[9 : 0] input_pattern;
20040 for (i = 0; i < deserialization_factor; i = i + 1)
20042 if(input_data[dfactor*channel_num +i] !== deskrew_pattern[i])
20048 endfunction // pattern_match
20050 // INITIAL CONSTRUCT BLOCK
20052 begin : INITIALIZATION
20058 rx_data_align_reg = 1'b0;
20059 rx_mercury_slow_clock = 1'b0;
20061 deskew_done = {number_of_channels{1'b1}};
20062 rx_in_latched = {number_of_channels{1'b0}};
20064 for (i = 0; i < number_of_channels; i = i + 1)
20067 rx_out_reg = {REGISTER_WIDTH{1'b0}};
20068 rx_out_hold = {REGISTER_WIDTH{1'b0}};
20069 rx_shift_reg = {REGISTER_WIDTH{1'b0}};
20070 rx_parallel_load_reg = {REGISTER_WIDTH{1'b0}};
20071 rx_ddio_in = {REGISTER_WIDTH{1'b0}};
20073 // Check for illegal mode settings
20074 if ((APEX20KE_RX_STYLE == 1) && (deserialization_factor != 1) &&
20075 (deserialization_factor != 4) && (deserialization_factor != 7) &&
20076 (deserialization_factor != 8))
20078 $display ($time, "ps Error: APEX20KE does not support the specified deserialization factor!");
20081 else if ((MERCURY_RX_STYLE == 1) &&
20082 (deserialization_factor != 1) && (deserialization_factor != 2) &&
20083 (((deserialization_factor > 12) && (deserialization_factor != 14) &&
20084 (deserialization_factor != 16) && (deserialization_factor != 18) &&
20085 (deserialization_factor != 20)) || (deserialization_factor<3)))
20087 $display ($time, "ps Error: MERCURY does not support the specified deserialization factor!");
20090 else if ((APEXII_RX_STYLE == 1) &&
20091 ((deserialization_factor > 10) || (deserialization_factor < 4)) &&
20092 (deserialization_factor != 1) && (deserialization_factor != 2))
20094 $display ($time, "ps Error: APEXII does not support the specified deserialization factor!");
20097 else if ((STRATIX_RX_STYLE == 1) &&
20098 (deserialization_factor != 1) && (deserialization_factor != 2) &&
20099 ((deserialization_factor > 10) || (deserialization_factor < 4)))
20101 $display ($time, "ps Error: STRATIX or STRATIXGX in non DPA mode does not support the specified deserialization factor!");
20104 else if ((STRATIXGX_DPA_RX_STYLE == 1) && (deserialization_factor != 8) && (deserialization_factor != 10))
20106 $display ($time, "ps Error: STRATIXGX in DPA mode does not support the specified deserialization factor!");
20110 if ((STRATIXII_RX_STYLE == 1) &&
20111 (deserialization_factor > 10))
20113 $display ($time, "ps Error: STRATIX II does not support the specified deserialization factor!");
20117 if ((STRATIXII_RX_STYLE == 1) &&
20118 (data_align_rollover > 11))
20120 $display ($time, "ps Error: STRATIX II does not support data align rollover values > 11 !");
20124 if (CYCLONE_RX_STYLE == 1)
20126 if ((use_external_pll == "ON") &&
20127 (deserialization_factor != 1) && (deserialization_factor != 2) &&
20128 (deserialization_factor != 4) && (deserialization_factor != 6) &&
20129 (deserialization_factor != 8) && (deserialization_factor != 10))
20131 $display ($time, "ps Error: Cyclone does not support the specified deserialization factor when use_external_pll is 'ON'!");
20134 else if ((deserialization_factor > 10) || (deserialization_factor == 3))
20136 $display ($time, "ps Error: Cyclone does not support the specified deserialization factor when use_external_pll is 'OFF'!");
20141 if (CYCLONEII_RX_STYLE == 1)
20143 if ((use_external_pll == "ON") &&
20144 (deserialization_factor != 1) && (deserialization_factor != 2) &&
20145 (deserialization_factor != 4) && (deserialization_factor != 6) &&
20146 (deserialization_factor != 8) && (deserialization_factor != 10))
20148 $display ($time, "ps Error: Cyclone II does not support the specified deserialization factor when use_external_pll is 'ON'!");
20151 else if ((deserialization_factor > 10) || (deserialization_factor == 3))
20153 $display ($time, "ps Error: Cyclone II does not support the specified deserialization factor when use_external_pll is 'OFF'!");
20158 if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
20160 $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
20164 // Initialise calibration pattern variables. Only for APEX20KE and APEXII
20165 if ((APEX20KE_RX_STYLE == 1) &&
20166 ((deserialization_factor == 4) || (deserialization_factor == 7) ||
20167 (deserialization_factor == 8)))
20169 check_deskew_pattern = 1;
20170 case (deserialization_factor)
20171 8: deskew_pattern[7:0] = 8'b00111100;
20172 7: deskew_pattern[6:0] = 7'b0011100;
20173 4: deskew_pattern[3:0] = 4'b1100;
20178 if (((APEXII_RX_STYLE == 1)) && (deserialization_factor <= 10) &&
20179 (deserialization_factor >= 4))
20181 check_deskew_pattern = 1;
20182 if (cds_mode == "SINGLE_BIT")
20184 case (deserialization_factor)
20185 10: deskew_pattern[9:0] = 10'b0000011111;
20186 9: deskew_pattern[8:0] = 9'b000001111;
20187 8: deskew_pattern[7:0] = 8'b00001111;
20188 7: deskew_pattern[6:0] = 7'b0000111;
20189 6: deskew_pattern[5:0] = 6'b000111;
20190 5: deskew_pattern[4:0] = 5'b00011;
20191 4: deskew_pattern[3:0] = 4'b0011;
20197 case (deserialization_factor)
20198 10: deskew_pattern[9:0] = 10'b0101010101;
20199 9: deskew_pattern[8:0] = 9'b010101010;
20200 8: deskew_pattern[7:0] = 8'b01010101;
20201 7: deskew_pattern[6:0] = 7'b0101010;
20202 6: deskew_pattern[5:0] = 6'b010101;
20203 5: deskew_pattern[4:0] = 5'b01010;
20204 4: deskew_pattern[3:0] = 4'b0101;
20209 else check_deskew_pattern = 0;
20211 end //INITIALIZATION
20213 // NCSIM will only assigns 1'bZ to unconnected port at time 0fs + 1
20216 if ((STRATIXII_RX_STYLE == 1) &&
20217 (rx_channel_data_align === {number_of_channels{1'bZ}}) &&
20218 (rx_data_align !== 1'bZ))
20220 $display("Warning : Data alignment on Stratix II devices introduces one bit of latency for each assertion of the data alignment signal. In comparison, Stratix and Stratix GX devices remove one bit of latency for each assertion.");
20224 // COMPONENT INSTANTIATIONS
20226 // pll for device families other than Stratix, Stratix GX and Stratix II
20228 .inclock(altclklock_inclock),
20229 .inclocken(rx_pll_enable),
20231 .clock0(altclklock_fastclk),
20232 .clock1(altclklock_slowclk),
20233 .clock2(unused_clk2),
20234 .clock_ext(unused_clk_ext),
20235 .locked(altclklock_locked));
20238 u0.inclock_period = CLOCK_PERIOD,
20239 u0.clock0_boost = INT_CLOCK_BOOST,
20240 u0.clock1_boost = INT_CLOCK_BOOST,
20241 u0.clock1_divide = deserialization_factor,
20242 u0.valid_lock_cycles = (APEXII_RX_STYLE == 1) ? 1 :
20243 (MERCURY_RX_STYLE == 1) ? 3 : 5,
20244 u0.intended_device_family = ((APEX20KE_RX_STYLE == 1 ) ||
20245 (APEXII_RX_STYLE == 1 ) ||
20246 (MERCURY_RX_STYLE == 1 ))
20247 ? intended_device_family
20250 // pll for Stratix and Stratix GX
20251 MF_stratix_pll u1 (
20252 .inclk(stratix_pll_inclock), // Required
20253 .ena(stratix_pll_enable),
20254 .areset(stratix_pll_areset),
20255 .clkena(6'b111111),
20256 .clk (stratix_pll_outclock),
20257 .locked(stratix_locked),
20265 .comparator(rx_data_align_int),
20268 .enable0(stratix_enable0),
20269 .enable1(stratix_enable1),
20275 u1.pll_type = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
20278 u1.inclk0_input_frequency = CLOCK_PERIOD,
20279 u1.inclk1_input_frequency = CLOCK_PERIOD,
20280 u1.valid_lock_multiplier = 1,
20281 u1.clk0_multiply_by = STRATIX_INCLOCK_BOOST,
20282 u1.clk0_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
20285 u1.clk1_multiply_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) &&
20286 (deserialization_factor%2 == 1)
20287 ? STRATIX_INCLOCK_BOOST
20289 u1.clk1_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) &&
20290 (deserialization_factor%2 == 1)
20291 ? PLL_D_VALUE*deserialization_factor
20293 u1.clk2_multiply_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) &&
20294 (deserialization_factor%2 == 1)
20295 ? STRATIX_INCLOCK_BOOST *2
20296 : STRATIX_INCLOCK_BOOST,
20297 u1.clk2_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
20298 ? ((deserialization_factor%2 == 0)
20299 ? PLL_D_VALUE*deserialization_factor/2
20300 : PLL_D_VALUE*deserialization_factor)
20301 : deserialization_factor,
20302 u1.clk0_phase_shift_num = PHASE_SHIFT,
20303 u1.clk1_phase_shift_num = (FAMILY_HAS_FLEXIBLE_LVDS == 1) &&
20304 (deserialization_factor%2 == 1)
20307 u1.clk2_phase_shift_num = PHASE_SHIFT,
20308 u1.simulation_type = "functional",
20312 // pll for Stratix II
20313 MF_stratixii_pll u2 (
20314 .inclk(stratixii_pll_inclock), // Required
20315 .ena(stratixii_pll_enable),
20316 .areset(stratixii_pll_areset),
20317 .clk (stratixii_pll_outclock ),
20318 .locked(stratixii_locked),
20328 .enable0(stratixii_enable0),
20329 .enable1(stratixii_enable1),
20334 .sclkout({stratixii_sclkout1, stratixii_sclkout0}),
20339 u2.pll_type = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
20342 u2.vco_multiply_by = STRATIX_INCLOCK_BOOST,
20343 u2.vco_divide_by = 1,
20344 u2.inclk0_input_frequency = CLOCK_PERIOD,
20345 u2.inclk1_input_frequency = CLOCK_PERIOD,
20346 u2.clk0_multiply_by = STRATIX_INCLOCK_BOOST,
20347 u2.clk0_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
20349 : deserialization_factor,
20350 u2.clk1_multiply_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) &&
20351 (deserialization_factor%2 == 1)
20352 ? STRATIX_INCLOCK_BOOST
20354 u2.clk1_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) &&
20355 (deserialization_factor%2 == 1)
20356 ? PLL_D_VALUE*deserialization_factor
20358 u2.clk2_multiply_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) &&
20359 (deserialization_factor%2 == 1)
20360 ? STRATIX_INCLOCK_BOOST *2
20361 : STRATIX_INCLOCK_BOOST,
20362 u2.clk2_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
20363 ? ((deserialization_factor%2 == 0)
20364 ? PLL_D_VALUE*deserialization_factor/2
20365 : PLL_D_VALUE*deserialization_factor)
20366 : deserialization_factor,
20367 u2.clk0_phase_shift_num = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
20369 : STXII_PHASE_SHIFT,
20370 u2.clk1_phase_shift_num = (FAMILY_HAS_FLEXIBLE_LVDS == 1) &&
20371 (deserialization_factor%2 == 1)
20374 u2.clk2_phase_shift_num = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
20376 : STXII_PHASE_SHIFT,
20377 u2.sclkout0_phase_shift = STXII_PHASE_SHIFT,
20378 u2.simulation_type = "functional",
20382 // Stratix lvds receiver
20383 stratix_lvds_rx u3 (
20385 .rx_fastclk(stratix_fastclk),
20386 .rx_enable0(stratix_enable0),
20387 .rx_enable1(stratix_enable1),
20388 .rx_out(stratix_dataout));
20391 u3.number_of_channels = number_of_channels,
20392 u3.deserialization_factor = deserialization_factor;
20394 // Stratixgx lvds receiver with DPA mode
20395 stratixgx_dpa_lvds_rx u4 (
20397 .rx_fastclk(stratixgx_fastclk),
20398 .rx_slowclk(stratixgx_slowclk),
20399 .rx_coreclk(stratixgx_coreclk),
20400 .rx_locked(stratix_locked),
20401 .rx_reset(rx_reset),
20402 .rx_dpll_reset(rx_dpll_reset),
20403 .rx_channel_data_align(rx_channel_data_align_int),
20404 .rx_out(stratixgx_dataout),
20405 .rx_dpa_locked(stratixgx_dpa_locked));
20408 u4.number_of_channels = number_of_channels,
20409 u4.deserialization_factor = deserialization_factor,
20410 u4.use_coreclock_input = use_coreclock_input,
20411 u4.enable_dpa_fifo = enable_dpa_fifo,
20412 u4.registered_output = registered_output;
20415 // Stratix II lvds receiver
20416 stratixii_lvds_rx u5 (
20418 .rx_reset(rx_reset),
20419 .rx_fastclk(stratixii_fastclk),
20420 .rx_enable(stratixii_enable),
20421 .rx_locked(stratixii_locked),
20422 .rx_dpll_reset(rx_dpll_reset),
20423 .rx_dpll_hold(rx_dpll_hold),
20424 .rx_dpll_enable(rx_dpll_enable),
20425 .rx_fifo_reset(rx_fifo_reset),
20426 .rx_channel_data_align(rx_channel_data_align_int),
20427 .rx_cda_reset(rx_cda_reset),
20428 .rx_out(stratixii_dataout),
20429 .rx_dpa_locked(stratixii_dpa_locked),
20430 .rx_cda_max(rx_cda_max));
20433 u5.number_of_channels = number_of_channels,
20434 u5.deserialization_factor = deserialization_factor,
20435 u5.enable_dpa_mode = enable_dpa_mode,
20436 u5.data_align_rollover = data_align_rollover,
20437 u5.lose_lock_on_one_change = lose_lock_on_one_change,
20438 u5.reset_fifo_at_first_lock = reset_fifo_at_first_lock;
20440 // flexible lvds receiver
20441 flexible_lvds_rx u6 (
20443 .rx_fastclk(flvds_fastclk),
20444 .rx_slowclk(flvds_slowclk),
20445 .rx_syncclk(flvds_syncclk),
20446 .rx_locked(rx_locked_int),
20447 .rx_out(flvds_dataout));
20450 u6.number_of_channels = number_of_channels,
20451 u6.deserialization_factor = deserialization_factor,
20452 u6.use_extra_ddio_register = (CYCLONE_RX_STYLE == 1) ||
20453 (CYCLONEII_RX_STYLE == 1) ? "YES" : "NO",
20454 u6.use_extra_pll_clk = (CYCLONE_RX_STYLE == 1) ||
20455 (CYCLONEII_RX_STYLE == 1) ? "NO" : "YES";
20459 // ALWAYS CONSTRUCT BLOCK
20461 // For x2 mode. Data input is sampled in both the rising edge and falling
20462 // edge of input clock.
20463 always @(posedge rx_inclock)
20465 if (deserialization_factor == 2)
20467 for (i1 = 0; i1 <= number_of_channels-1; i1 = i1+1)
20469 rx_ddio_in[(i1*2)+1] <= rx_in[i1];
20470 rx_ddio_in[(i1*2)] <= rx_in_latched[i1];
20475 always @(negedge rx_inclock)
20476 begin : DDIO_IN_LATCH
20477 if ((deserialization_factor == 2) && ($time > 0))
20479 rx_in_latched <= rx_in;
20481 end // DDIO_IN_LATCH
20483 // Activate calibration mode
20484 always @ (posedge rx_deskew)
20485 begin : CALIBRATION
20486 deskew_done <= {number_of_channels{1'b0}};
20491 always @ (posedge rx_slowclk)
20493 negedge_count <= 0;
20495 // In order to assure that the circuit is capturing data accurately
20496 // the user must calibrate the LVDS data channels by asserting a
20497 // deskew signal and applying the appropriate calibration value for
20498 // 3 clock cycles to deskew the channel after 3 clock cycles.
20499 if (check_deskew_pattern == 1)
20501 if (calibrate == 1'b1)
20503 for (j = 0; j <= number_of_channels-1; j = j+1)
20505 if (pattern_match(pattern, deskew_pattern[deserialization_factor-1:0], deserialization_factor, j) ||
20506 (pattern_match(pattern, ~deskew_pattern[deserialization_factor-1:0], deserialization_factor, j) &&
20507 (APEXII_RX_STYLE == 1) &&
20508 (cds_mode == "MULTIPLE_BIT")))
20510 count[j] <= count[j] + 1;
20513 deskew_done[j] <= 1'b1;
20523 if (rx_deskew == 0)
20528 // Fast clock (on falling edge)
20529 always @ (negedge rx_fastclk)
20530 begin : FAST_CLOCK_NEGEDGE
20531 if(rx_locked_int == 1)
20534 negedge_count <= negedge_count + 1;
20536 // For APEX and Mercury families, load data on the
20537 // 3rd negative edge of the fast clock
20538 if (negedge_count == 2)
20541 if (rx_deskew == 0)
20542 rx_parallel_load_reg <= rx_shift_reg;
20546 for (i4= 0; i4 < number_of_channels; i4 = i4+1)
20548 if (deskew_done[i4] == 1)
20550 if(APEXII_RX_STYLE == 1)
20552 for (x=deserialization_factor-1; x >0; x=x-1)
20553 rx_shift_reg[x + (i4 * deserialization_factor)] <= rx_shift_reg [x-1 + (i4 * deserialization_factor)];
20554 rx_shift_reg[i4 * deserialization_factor] <= rx_in[i4];
20557 // Data gets shifted into MSB first
20558 rx_shift_reg[(i4+1)*deserialization_factor-1] <= rx_in[i4];
20562 if(APEXII_RX_STYLE == 1)
20564 for (x=deserialization_factor-1; x >0; x=x-1)
20565 pattern[x + (i4 * deserialization_factor)] <= pattern [x-1 + (i4 * deserialization_factor)];
20566 pattern[i4 * deserialization_factor] <= rx_in[i4];
20569 pattern[(i4+1)*deserialization_factor-1] <= rx_in[i4];
20570 rx_shift_reg[(i4+1)*deserialization_factor-1] <= 'bx;
20577 // Loading input data to shift register
20578 sample <= (sample + 1) % deserialization_factor;
20580 for (i4= 0; i4 < number_of_channels; i4 = i4+1)
20582 if (deskew_done[i4] == 1)
20584 if(APEXII_RX_STYLE == 1)
20586 for (x=deserialization_factor-1; x >0; x=x-1)
20587 rx_shift_reg[x + (i4 * deserialization_factor)] <= rx_shift_reg [x-1 + (i4 * deserialization_factor)];
20588 rx_shift_reg[i4 * deserialization_factor] <= rx_in[i4];
20591 // Data gets shifted into MSB first
20592 rx_shift_reg[(i4+1)*deserialization_factor-sample-1] <= rx_in[i4];
20596 if(APEXII_RX_STYLE == 1)
20598 for (x=deserialization_factor-1; x >0; x=x-1)
20599 pattern[x + (i4 * deserialization_factor)] <= pattern [x-1 + (i4 * deserialization_factor)];
20600 pattern[i4 * deserialization_factor] <= rx_in[i4];
20603 pattern[(i4+1)*deserialization_factor-sample-1] <= rx_in[i4];
20604 rx_shift_reg[(i4+1)*deserialization_factor-sample-1] <= 'bx;
20611 // Fast clock (on rising edge)
20612 always @ (posedge rx_fastclk)
20613 begin : FAST_CLOCK_POSEDGE
20614 if(rx_locked_int == 1)
20616 if (deserialization_factor > 2)
20618 posedge_count <= (posedge_count+1) % deserialization_factor;
20620 // Generating slow clock for MERCURY
20621 if (posedge_count % ((deserialization_factor+1)/2) == 0)
20623 rx_mercury_slow_clock <= ~rx_mercury_slow_clock;
20629 // synchronization register
20630 always @ (posedge rx_reg_clk)
20631 begin : SYNC_REGISTER
20632 rx_out_reg <= rx_out_int;
20633 end // SYNC_REGISTER
20636 always @ (negedge rx_hold_clk)
20637 begin : HOLD_REGISTER
20638 if (deserialization_factor > 1)
20640 rx_out_hold <= rx_parallel_load_reg;
20642 end // HOLD_REGISTER
20644 // Registering rx_data_align signal for stratix II lvds_rx.
20645 always @ (posedge rx_data_align_clk)
20647 rx_data_align_reg <= rx_data_align_pulldown;
20650 // CONTINOUS ASSIGNMENT
20651 assign rx_out = (STRATIXGX_DPA_RX_STYLE == 1)
20652 ? stratixgx_dataout :
20653 (registered_output == "ON")
20657 assign rx_out_int = (deserialization_factor == 1)
20659 (deserialization_factor == 2)
20661 (FAMILY_HAS_FLEXIBLE_LVDS == 1)
20663 (STRATIX_RX_STYLE == 1)
20664 ? stratix_dataout :
20665 (STRATIXII_RX_STYLE == 1)
20666 ? stratixii_dataout :
20667 (RX_NEED_HOLD_REG == 1)
20669 : rx_parallel_load_reg;
20671 assign rx_reg_clk = (use_external_pll == "ON")
20673 : {number_of_channels{rx_outclk_int}};
20675 assign rx_hold_clk = rx_outclk_int;
20677 assign rx_outclock = rx_outclk_int;
20679 assign rx_outclk_int = (deserialization_factor <= 2)
20681 (MERCURY_RX_STYLE == 1)
20682 ? rx_mercury_slow_clock
20685 assign rx_slowclk = ((STRATIX_RX_STYLE == 1) ||
20686 (STRATIXGX_DPA_RX_STYLE == 1) ||
20687 (CYCLONE_RX_STYLE == 1))
20688 ? stratix_pll_outclock[2] :
20689 ((STRATIXII_RX_STYLE == 1) ||
20690 (CYCLONEII_RX_STYLE == 1))
20691 ? stratixii_pll_outclock[2]
20692 : altclklock_slowclk;
20694 assign rx_fastclk = altclklock_fastclk;
20696 assign rx_locked = (deserialization_factor > 2)
20700 assign rx_locked_int = ((STRATIX_RX_STYLE == 1) ||
20701 (STRATIXGX_DPA_RX_STYLE == 1) ||
20702 (CYCLONE_RX_STYLE == 1))
20704 ((STRATIXII_RX_STYLE == 1) ||
20705 (CYCLONEII_RX_STYLE == 1))
20707 : altclklock_locked;
20709 assign rx_dpa_locked = (STRATIXGX_DPA_RX_STYLE == 1)
20710 ? stratixgx_dpa_locked :
20711 (STRATIXII_RX_STYLE == 1)
20712 ? stratixii_dpa_locked
20713 : {number_of_channels{1'b1}};
20715 assign rx_data_align_pulldown = (port_rx_data_align == "PORT_USED")
20717 (port_rx_data_align == "PORT_UNUSED")
20719 (rx_data_align !== 1'bz)
20723 assign rx_data_align_int = (registered_data_align_input == "ON")
20724 ? rx_data_align_reg
20725 : rx_data_align_pulldown;
20727 assign rx_channel_data_align_int =
20728 (rx_channel_data_align !== {number_of_channels{1'bZ}})
20729 ? rx_channel_data_align :
20730 (STRATIXII_RX_STYLE == 1)
20731 ? {number_of_channels{rx_data_align_int}}
20732 : {number_of_channels{1'b0}};
20734 assign rx_data_align_clk = ((STRATIX_RX_STYLE == 1) ||
20735 (STRATIXGX_DPA_RX_STYLE == 1))
20736 ? stratix_pll_outclock[2] :
20737 (STRATIXII_RX_STYLE == 1)
20738 ? stratixii_pll_outclock[2]
20741 assign altclklock_inclock = (APEX20KE_RX_STYLE == 1) ||
20742 (APEXII_RX_STYLE == 1) ||
20743 (MERCURY_RX_STYLE == 1)
20747 assign stratix_pll_inclock[1:0] = (FAMILY_HAS_STRATIX_STYLE_PLL == 1)
20748 ? {1'b0, rx_inclock}
20751 assign stratix_pll_enable = (FAMILY_HAS_STRATIX_STYLE_PLL == 1)
20755 assign stratix_pll_areset = (FAMILY_HAS_STRATIX_STYLE_PLL == 1)
20759 assign stratix_fastclk = (STRATIX_RX_STYLE == 1) && (implement_in_les == "OFF")
20760 ? stratix_pll_outclock[0]
20763 assign stratix_slowclk = (STRATIX_RX_STYLE == 1) && (implement_in_les == "OFF")
20764 ? stratix_pll_outclock[2]
20767 assign stratixgx_fastclk = (STRATIXGX_DPA_RX_STYLE == 1) && (implement_in_les == "OFF")
20768 ? stratix_pll_outclock[0]
20771 assign stratixgx_slowclk = (STRATIXGX_DPA_RX_STYLE == 1) && (implement_in_les == "OFF")
20772 ? stratix_pll_outclock[2]
20775 assign stratixgx_coreclk = (STRATIXGX_DPA_RX_STYLE == 1) && (implement_in_les == "OFF")
20777 : {number_of_channels{1'b0}};
20779 assign stratixii_pll_inclock[1:0] = (FAMILY_HAS_STRATIXII_STYLE_PLL == 1)
20780 ? {1'b0, rx_inclock}
20783 assign stratixii_pll_enable = (FAMILY_HAS_STRATIXII_STYLE_PLL == 1)
20787 assign stratixii_pll_areset = (FAMILY_HAS_STRATIXII_STYLE_PLL == 1)
20790 assign stratixii_fastclk = (STRATIXII_RX_STYLE == 0) && (implement_in_les == "OFF")
20792 (use_external_pll == "ON")
20794 : stratixii_sclkout0;
20796 assign stratixii_enable = (STRATIXII_RX_STYLE == 0) && (implement_in_les == "OFF")
20798 (use_external_pll == "ON")
20800 : stratixii_enable0;
20802 assign flvds_fastclk = ((FAMILY_HAS_FLEXIBLE_LVDS == 1) &&
20803 (FAMILY_HAS_STRATIX_STYLE_PLL == 1))
20804 ? ((use_external_pll == "ON")
20806 : stratix_pll_outclock[0]) :
20807 ((FAMILY_HAS_FLEXIBLE_LVDS == 1) &&
20808 (FAMILY_HAS_STRATIXII_STYLE_PLL == 1))
20809 ? ((use_external_pll == "ON")
20811 : stratixii_pll_outclock[0])
20814 assign flvds_slowclk = ((FAMILY_HAS_FLEXIBLE_LVDS == 1) &&
20815 (FAMILY_HAS_STRATIX_STYLE_PLL == 1))
20816 ? ((use_external_pll == "ON")
20818 : stratix_pll_outclock[2]) :
20819 ((FAMILY_HAS_FLEXIBLE_LVDS == 1) &&
20820 (FAMILY_HAS_STRATIXII_STYLE_PLL == 1))
20821 ? ((use_external_pll == "ON")
20823 : stratixii_pll_outclock[2])
20826 assign flvds_syncclk = ((FAMILY_HAS_FLEXIBLE_LVDS == 1) &&
20827 (FAMILY_HAS_STRATIX_STYLE_PLL == 1))
20828 ? ((use_external_pll == "ON")
20830 : stratix_pll_outclock[1]) :
20831 ((FAMILY_HAS_FLEXIBLE_LVDS == 1) &&
20832 (FAMILY_HAS_STRATIXII_STYLE_PLL == 1))
20833 ? ((use_external_pll == "ON")
20835 : stratixii_pll_outclock[1])
20838 endmodule // altlvds_rx
20841 //START_MODULE_NAME----------------------------------------------------
20843 // Module Name : stratix_lvds_rx
20845 // Description : Stratix lvds receiver
20847 // Limitation : Only available to Stratix and stratix GX (NON DPA mode)
20850 // Results expected: Deserialized output data.
20852 //END_MODULE_NAME----------------------------------------------------
20854 // BEGINNING OF MODULE
20855 `timescale 1 ps / 1 ps
20857 // MODULE DECLARATION
20858 module stratix_lvds_rx (
20859 rx_in, // input serial data
20860 rx_fastclk, // fast clock from pll
20863 rx_out // deserialized output data
20866 // GLOBAL PARAMETER DECLARATION
20867 parameter number_of_channels = 1;
20868 parameter deserialization_factor = 4;
20870 // LOCAL PARAMETER DECLARATION
20871 parameter REGISTER_WIDTH = deserialization_factor*number_of_channels;
20873 // INPUT PORT DECLARATION
20874 input [number_of_channels -1 :0] rx_in;
20879 // OUTPUT PORT DECLARATION
20880 output [REGISTER_WIDTH -1: 0] rx_out;
20882 // INTERNAL REGISTERS DECLARATION
20883 reg [REGISTER_WIDTH -1 : 0] rx_shift_reg;
20884 reg [REGISTER_WIDTH -1 : 0] rx_parallel_load_reg;
20885 reg [REGISTER_WIDTH -1 : 0] rx_out_hold;
20891 // INTERNAL WIRE DECLARATION
20894 // LOCAL INTEGER DECLARATION
20898 // INITIAL CONSTRUCT BLOCK
20900 begin : INITIALIZATION
20901 rx_shift_reg = {REGISTER_WIDTH{1'b0}};
20902 rx_parallel_load_reg = {REGISTER_WIDTH{1'b0}};
20903 rx_out_hold = {REGISTER_WIDTH{1'b0}};
20904 end //INITIALIZATION
20906 // ALWAYS CONSTRUCT BLOCK
20908 // registering load enable signal
20909 always @ (posedge rx_fastclk)
20910 begin : LOAD_ENABLE
20911 enable0_reg1 <= enable0_reg;
20912 enable0_reg <= rx_enable0;
20913 enable1_reg <= rx_enable1;
20916 // Fast clock (on falling edge)
20917 always @ (negedge rx_fastclk)
20918 begin : NEGEDGE_FAST_CLOCK
20920 // load data when the registered load enable signal is high
20921 if (enable0_neg == 1)
20922 rx_parallel_load_reg <= rx_shift_reg;
20924 // Loading input data to shift register
20925 for (i1= 0; i1 < number_of_channels; i1 = i1+1)
20927 for (x=deserialization_factor-1; x >0; x=x-1)
20928 rx_shift_reg[x + (i1 * deserialization_factor)] <= rx_shift_reg [x-1 + (i1 * deserialization_factor)];
20929 rx_shift_reg[i1 * deserialization_factor] <= rx_in[i1];
20932 enable0_neg <= enable0_reg1;
20934 end // NEGEDGE_FAST_CLOCK
20936 // Holding register
20937 always @ (posedge rx_hold_clk)
20938 begin : HOLD_REGISTER
20939 rx_out_hold <= rx_parallel_load_reg;
20940 end // HOLD_REGISTER
20942 // CONTINOUS ASSIGNMENT
20943 assign rx_out = rx_out_hold;
20944 assign rx_hold_clk = enable1_reg;
20947 endmodule // stratix_lvds_rx
20950 //START_MODULE_NAME----------------------------------------------------
20952 // Module Name : stratixgx_dpa_lvds_rx
20954 // Description : Stratix GX lvds receiver.
20956 // Limitation : Only available in Stratix GX families.
20958 // Results expected: Deserialized output data and dpa locked signal.
20960 //END_MODULE_NAME----------------------------------------------------
20962 // BEGINNING OF MODULE
20963 `timescale 1 ps / 1 ps
20965 // MODULE DECLARATION
20966 module stratixgx_dpa_lvds_rx (
20974 rx_channel_data_align,
20979 // GLOBAL PARAMETER DECLARATION
20980 parameter number_of_channels = 1;
20981 parameter deserialization_factor = 4;
20982 parameter use_coreclock_input = "OFF";
20983 parameter enable_dpa_fifo = "ON";
20984 parameter registered_output = "ON";
20986 // LOCAL PARAMETER DECLARATION
20987 parameter REGISTER_WIDTH = deserialization_factor*number_of_channels;
20989 // INPUT PORT DECLARATION
20990 input [number_of_channels -1 :0] rx_in;
20994 input [number_of_channels -1 :0] rx_coreclk;
20995 input [number_of_channels -1 :0] rx_reset;
20996 input [number_of_channels -1 :0] rx_dpll_reset;
20997 input [number_of_channels -1 :0] rx_channel_data_align;
20999 // OUTPUT PORT DECLARATION
21000 output [REGISTER_WIDTH -1: 0] rx_out;
21001 output [number_of_channels -1: 0] rx_dpa_locked;
21003 // INTERNAL REGISTERS DECLARATION
21005 reg [REGISTER_WIDTH -1 : 0] rx_shift_reg;
21006 reg [REGISTER_WIDTH -1 : 0] rx_parallel_load_reg;
21007 reg [number_of_channels -1 : 0] rx_in_reg;
21008 reg [number_of_channels -1 : 0] dpa_in;
21009 reg [number_of_channels -1 : 0] retime_data;
21011 reg [REGISTER_WIDTH -1 : 0] ram_array0;
21012 reg [REGISTER_WIDTH -1 : 0] ram_array1;
21013 reg [REGISTER_WIDTH -1 : 0] ram_array2;
21014 reg [REGISTER_WIDTH -1 : 0] ram_array3;
21015 reg [2 : 0] wrPtr [number_of_channels -1 : 0];
21016 reg [2 : 0] rdPtr [number_of_channels -1 : 0];
21017 reg [3 : 0] bitslip_count [number_of_channels -1 : 0];
21018 reg [3 : 0] bitslip_count_pre [number_of_channels -1 : 0];
21020 reg [REGISTER_WIDTH -1 : 0] rxpdat2;
21021 reg [REGISTER_WIDTH -1 : 0] rxpdat3;
21022 reg [REGISTER_WIDTH -1 : 0] rxpdatout;
21023 reg [REGISTER_WIDTH -1 : 0] fifo_data_out;
21024 reg [REGISTER_WIDTH -1 : 0] rx_out_reg;
21025 reg [number_of_channels -1 : 0] dpagclk_pre;
21026 reg [number_of_channels -1 : 0] rx_channel_data_align_pre;
21027 reg [number_of_channels -1 : 0] fifo_write_clk_pre;
21028 reg [number_of_channels -1 : 0] clkout_tmp;
21029 reg [number_of_channels -1 : 0] sync_reset;
21031 // INTERNAL WIRE DECLARATION
21032 wire [number_of_channels -1:0] dpagclk;
21033 wire[number_of_channels -1:0] fifo_write_clk;
21034 wire [REGISTER_WIDTH -1 : 0] rx_out_int;
21035 wire [REGISTER_WIDTH -1 : 0] serdes_data_out;
21036 wire [REGISTER_WIDTH -1 : 0] fifo_data_in;
21037 wire [REGISTER_WIDTH -1 : 0] rxpdat1;
21039 // INTERNAL TRI DECLARATION
21040 tri0[number_of_channels -1 :0] rx_reset;
21041 tri0[number_of_channels -1 :0] rx_dpll_reset;
21042 tri0[number_of_channels -1 :0] rx_channel_data_align;
21043 tri0[number_of_channels -1 :0] rx_coreclk;
21045 // LOCAL INTEGER DECLARATION
21062 integer negedge_count;
21064 integer fastclk_posedge_count [number_of_channels -1: 0];
21065 integer fastclk_negedge_count [number_of_channels - 1 : 0];
21066 integer bitslip_count_reg [number_of_channels -1: 0];
21069 // COMPONENT INSTANTIATIONS
21070 // ALTERA_DEVICE_FAMILIES dev ();
21072 // INITIAL CONSTRUCT BLOCK
21074 begin : INITIALIZATION
21075 rxpdat2 = {REGISTER_WIDTH{1'b0}};
21076 rxpdat3 = {REGISTER_WIDTH{1'b0}};
21077 rxpdatout = {REGISTER_WIDTH{1'b0}};
21078 rx_out_reg = {REGISTER_WIDTH{1'b0}};
21080 ram_array0 = {REGISTER_WIDTH{1'b0}};
21081 ram_array1 = {REGISTER_WIDTH{1'b0}};
21082 ram_array2 = {REGISTER_WIDTH{1'b0}};
21083 ram_array3 = {REGISTER_WIDTH{1'b0}};
21085 rx_in_reg = {number_of_channels{1'b0}};
21086 dpa_in = {number_of_channels{1'b0}};
21087 retime_data = {number_of_channels{1'b0}};
21089 rx_channel_data_align_pre = {number_of_channels{1'b0}};
21090 clkout_tmp = {number_of_channels{1'b0}};
21091 sync_reset = {number_of_channels{1'b0}};
21093 rx_shift_reg = {REGISTER_WIDTH{1'b0}};
21094 rx_parallel_load_reg = {REGISTER_WIDTH{1'b0}};
21095 fifo_data_out = {REGISTER_WIDTH{1'b0}};
21097 for (i = 0; i < number_of_channels; i = i + 1)
21101 bitslip_count[i] = 0;
21102 bitslip_count_reg[i] = 0;
21103 fastclk_posedge_count[i] = 0;
21104 fastclk_negedge_count[i] = 0;
21107 end //INITIALIZATION
21110 // ALWAYS CONSTRUCT BLOCK
21112 //deserializer logic
21113 always @ (posedge dpagclk)
21114 begin : DPA_SERDES_SLOWCLK
21116 for(i0 = 0; i0 <=number_of_channels -1; i0=i0+1)
21118 if ((dpagclk[i0] == 1'b1) && (dpagclk_pre[i0] == 1'b0))
21121 if ((rx_reset[i0] == 1'b1) || (rx_dpll_reset[i0] == 1'b1))
21122 sync_reset[i0] <= 1'b1;
21124 sync_reset[i0] <= 1'b0;
21126 // add 1 ps delay to ensure that when the rising edge of
21127 // global clock(core clock) happens at the same time of falling
21128 // edge of fast clock, the count for the next falling edge of
21129 // fast clock is start at 1.
21130 fastclk_negedge_count[i0] <= #1 0;
21133 end // DPA_SERDES_SLOW_CLOCK
21136 always @ (posedge rx_fastclk)
21137 begin : DPA_SERDES_POSEDGE_FASTCLK
21138 for(i1 = 0; i1 <=number_of_channels -1; i1=i1+1)
21140 if (fastclk_negedge_count[i1] == 2)
21141 rx_parallel_load_reg <= rx_shift_reg;
21143 if (sync_reset[i1] == 1'b1)
21145 fastclk_posedge_count[i1] <= 0;
21146 clkout_tmp[i1] <= 1'b0;
21150 if (fastclk_posedge_count[i1] % (deserialization_factor / 2) == 0)
21152 fastclk_posedge_count[i1] <= 1;
21153 clkout_tmp[i1] <= !clkout_tmp[i1];
21156 fastclk_posedge_count[i1] <= (fastclk_posedge_count[i1] + 1) % deserialization_factor;
21159 end // DPA_SERDES_POSEDGE_FAST_CLOCK
21161 always @ (negedge rx_fastclk)
21162 begin : DPA_SERDES_NEGEDGE_FAST_CLOCK
21163 if (rx_fastclk == 1'b0)
21165 for (i2 = 0; i2 <= number_of_channels -1; i2 = i2+1)
21167 // Data gets shifted into MSB first.
21168 for (x=deserialization_factor-1; x > 0; x=x-1)
21169 rx_shift_reg[x + (i2 * deserialization_factor)] <= rx_shift_reg [x-1 + (i2 * deserialization_factor)];
21171 rx_shift_reg[i2 * deserialization_factor] <= retime_data[i2];
21172 retime_data <= rx_in;
21174 fastclk_negedge_count[i2] <= (fastclk_negedge_count[i2] + 1) ;
21177 end // DPA_SERDES_NEGEDGE_FAST_CLOCK
21179 //phase compensation FIFO
21180 always @ (posedge fifo_write_clk)
21181 begin : DPA_FIFO_WRITE_CLOCK
21182 if ((enable_dpa_fifo == "ON") && (rx_locked == 1'b1))
21184 for (i3 = 0; i3 <= number_of_channels-1; i3 = i3+1)
21186 if(sync_reset[i3] == 1'b1)
21188 else if ((fifo_write_clk[i3] == 1'b1) && (fifo_write_clk_pre[i3] == 1'b0))
21192 for (j = i3*deserialization_factor; j <= (i3+1)*deserialization_factor -1; j=j+1)
21193 ram_array0[j] <= fifo_data_in[j];
21196 for (j = i3*deserialization_factor; j <= (i3+1)*deserialization_factor -1; j=j+1)
21197 ram_array1[j] <= fifo_data_in[j];
21199 for (j = i3*deserialization_factor; j <= (i3+1)*deserialization_factor -1; j=j+1)
21200 ram_array2[j] <= fifo_data_in[j];
21202 for (j = i3*deserialization_factor; j <= (i3+1)*deserialization_factor -1; j=j+1)
21203 ram_array3[j] <= fifo_data_in[j];
21205 $display ("Error! Invalid wrPtr value.");
21207 wrPtr[i3] <= (wrPtr[i3] + 1) % 4;
21211 end // DPA_FIFO_WRITE_CLOCK
21213 always @ (negedge fifo_write_clk)
21215 for (i6 = 0; i6 <= number_of_channels-1; i6 = i6+1)
21217 if (fifo_write_clk[i6] == 1'b0)
21218 fifo_write_clk_pre[i6] <= fifo_write_clk[i6];
21222 always @ (posedge dpagclk)
21223 begin : DPA_FIFO_SLOW_CLOCK
21225 if((enable_dpa_fifo == "ON") )
21227 for (i4 = 0; i4 <= number_of_channels-1; i4 = i4+1)
21229 if ((dpagclk[i4] == 1'b1) && (dpagclk_pre[i4] == 1'b0))
21231 if ((rx_reset[i4] == 1'b1) || (rx_dpll_reset[i4] == 1'b1) || (sync_reset[i4] == 1'b1))
21233 for (j1 = i4*deserialization_factor; j1 <= (i4+1)*deserialization_factor -1; j1=j1+1)
21235 fifo_data_out[j1] <= 1'b0;
21236 ram_array0[j1] <= 1'b0;
21237 ram_array1[j1] <= 1'b0;
21238 ram_array2[j1] <= 1'b0;
21239 ram_array3[j1] <= 1'b0;
21249 for (j1 = i4*deserialization_factor; j1 <= (i4+1)*deserialization_factor -1; j1=j1+1)
21250 fifo_data_out[j1] <= ram_array0[j1];
21252 for (j1 = i4*deserialization_factor; j1 <= (i4+1)*deserialization_factor -1; j1=j1+1)
21253 fifo_data_out[j1] <= ram_array1[j1];
21255 for (j1 = i4*deserialization_factor; j1 <= (i4+1)*deserialization_factor -1; j1=j1+1)
21256 fifo_data_out[j1] <= ram_array2[j1];
21258 for (j1 = i4*deserialization_factor; j1 <= (i4+1)*deserialization_factor -1; j1=j1+1)
21259 fifo_data_out[j1] <= ram_array3[j1];
21261 $display ("Error! Invalid rdPtr value.");
21264 rdPtr[i4] <= (rdPtr[i4] + 1) % 4;
21269 end // DPA_FIFO_SLOW_CLOCK
21272 //bit-slipping logic
21273 always @ (posedge dpagclk)
21274 begin : DPA_BIT_SLIP
21276 for (i5 = 0; i5 <= number_of_channels-1; i5 = i5 + 1)
21278 if ((dpagclk[i5] == 1'b1) && (dpagclk_pre[i5] == 1'b0))
21280 if ((sync_reset[i5] == 1'b1) || (rx_reset[i5] == 1'b1) ||
21281 (rx_dpll_reset[i5] == 1'b1))
21283 for(j2 = deserialization_factor*i5; j2 <= deserialization_factor*(i5+1) -1; j2=j2+1)
21285 rxpdat2[j2] <= 1'b0;
21286 rxpdat3[j2] <= 1'b0;
21287 rxpdatout[j2] <= 1'b0;
21289 bitslip_count[i5] <= 0;
21290 bitslip_count_reg[i5] <= 0;
21294 if ((rx_channel_data_align[i5] == 1'b1) && (rx_channel_data_align_pre[i5] == 1'b0))
21295 bitslip_count[i5] <= (bitslip_count[i5] + 1) % deserialization_factor;
21297 bitslip_count_reg[i5] <= bitslip_count[i5];
21299 rxpdat2 <= rxpdat1;
21300 rxpdat3 <= rxpdat2;
21302 for(j2 = deserialization_factor*i5 + bitslip_count_reg[i5]; j2 <= deserialization_factor*(i5+1) -1; j2=j2+1)
21303 rxpdatout[j2] <= rxpdat3[j2-bitslip_count_reg[i5]];
21305 for(j2 = deserialization_factor*i5 ; j2 <= deserialization_factor*i5 + bitslip_count_reg[i5] -1; j2=j2+1)
21306 rxpdatout[j2] <= rxpdat2[j2+ deserialization_factor -bitslip_count_reg[i5]];
21308 rx_channel_data_align_pre[i5] <= rx_channel_data_align[i5];
21311 end // DPA_BIT_SLIP
21313 // synchronization register
21314 always @ (posedge dpagclk)
21315 begin : SYNC_REGISTER
21316 for (i8 = 0; i8 < number_of_channels; i8 = i8+1)
21318 if ((dpagclk[i8] == 1'b1) && (dpagclk_pre[i8] == 1'b0))
21320 for (j3 = 0; j3 < deserialization_factor; j3 = j3+1)
21321 rx_out_reg[i8*deserialization_factor + j3] <= rxpdatout[i8*deserialization_factor + j3];
21324 end // SYNC_REGISTER
21326 // store previous value of the global clocks
21329 dpagclk_pre <= dpagclk;
21332 // CONTINOUS ASSIGNMENT
21333 assign dpagclk = (use_coreclock_input == "ON") ? rx_coreclk : {number_of_channels{rx_slowclk}};
21334 assign rxpdat1 = (enable_dpa_fifo == "ON") ? fifo_data_out : serdes_data_out;
21335 assign serdes_data_out = rx_parallel_load_reg;
21336 assign fifo_data_in = serdes_data_out;
21337 assign fifo_write_clk = clkout_tmp;
21338 assign rx_dpa_locked = {number_of_channels {1'b1}};
21339 assign rx_out = (registered_output == "ON") ? rx_out_reg : rxpdatout;
21342 endmodule // stratixgx_dpa_lvds_rx
21345 //START_MODULE_NAME-------------------------------------------------------------
21347 // Module Name : stratixii_lvds_rx
21349 // Description : Stratix II lvds receiver. Support both the dpa and non-dpa
21352 // Limitation : Only available to Stratix II.
21354 // Results expected: Deserialized output data, dpa lock signal and status bit
21355 // indicating whether maximum bitslip has been reached.
21357 //END_MODULE_NAME---------------------------------------------------------------
21359 // BEGINNING OF MODULE
21360 `timescale 1 ps / 1 ps
21362 // MODULE DECLARATION
21363 module stratixii_lvds_rx (
21373 rx_channel_data_align,
21380 // GLOBAL PARAMETER DECLARATION
21381 parameter number_of_channels = 1;
21382 parameter deserialization_factor = 4;
21383 parameter enable_dpa_mode = "OFF";
21384 parameter data_align_rollover = deserialization_factor;
21385 parameter lose_lock_on_one_change = "OFF";
21386 parameter reset_fifo_at_first_lock = "ON";
21388 // LOCAL PARAMETER DECLARATION
21389 parameter REGISTER_WIDTH = deserialization_factor*number_of_channels;
21390 parameter MUX_WIDTH = 12;
21391 parameter RAM_WIDTH = 6;
21393 // INPUT PORT DECLARATION
21394 input [number_of_channels -1 :0] rx_in;
21398 input [number_of_channels -1 :0] rx_reset;
21399 input [number_of_channels -1 :0] rx_dpll_reset;
21400 input [number_of_channels -1 :0] rx_dpll_hold;
21401 input [number_of_channels -1 :0] rx_dpll_enable;
21402 input [number_of_channels -1 :0] rx_fifo_reset;
21403 input [number_of_channels -1 :0] rx_channel_data_align;
21404 input [number_of_channels -1 :0] rx_cda_reset;
21406 // OUTPUT PORT DECLARATION
21407 output [REGISTER_WIDTH -1: 0] rx_out;
21408 output [number_of_channels -1: 0] rx_dpa_locked;
21409 output [number_of_channels -1: 0] rx_cda_max;
21412 // INTERNAL REGISTERS DECLARATION
21414 reg [REGISTER_WIDTH -1 : 0] rx_shift_reg;
21415 reg [REGISTER_WIDTH -1 : 0] rx_parallel_load_reg;
21416 reg [number_of_channels -1 : 0] rx_in_reg;
21417 reg [number_of_channels -1 : 0] fifo_in_sync_reg;
21418 reg [number_of_channels -1 : 0] fifo_out_sync_reg;
21419 reg [number_of_channels -1 : 0] bitslip_mux_out;
21420 reg [number_of_channels -1 : 0] dpa_in;
21421 reg [number_of_channels -1 : 0] retime_data;
21422 reg [number_of_channels -1 : 0] dpll_lock;
21423 reg [number_of_channels -1 : 0] dpll_first_lock;
21424 reg [number_of_channels -1 : 0] rx_channel_data_align_pre;
21425 reg [number_of_channels -1 : 0] write_side_sync_reset;
21426 reg [number_of_channels -1 : 0] read_side_sync_reset;
21428 reg ram_array [(RAM_WIDTH*number_of_channels) -1 : 0];
21429 reg [2 : 0] wrPtr [number_of_channels -1 : 0];
21430 reg [2 : 0] rdPtr [number_of_channels -1 : 0];
21431 reg [3 : 0] bitslip_count [number_of_channels -1 : 0];
21432 reg [number_of_channels -1 : 0] start_corrupt_bits;
21433 reg [1 : 0] num_corrupt_bits [number_of_channels -1 : 0];
21434 reg [number_of_channels -1 : 0] rx_cda_max;
21435 reg [(MUX_WIDTH*number_of_channels) -1 : 0] shift_reg_chain;
21438 // INTERNAL WIRE DECLARATION
21439 wire fifo_write_clk;
21440 wire fifo_read_clk;
21441 wire [number_of_channels -1 : 0] dpa_fifo_in;
21442 wire [number_of_channels -1 : 0] dpa_fifo_out;
21443 wire rx_in_reg_clk;
21446 // INTERNAL TRI DECLARATION
21447 tri0[number_of_channels -1 :0] rx_reset;
21448 tri0[number_of_channels -1 :0] rx_dpll_reset;
21449 tri0[number_of_channels -1 :0] rx_dpll_hold;
21450 tri1[number_of_channels -1 :0] rx_dpll_enable;
21451 tri0[number_of_channels -1 :0] rx_fifo_reset;
21452 tri0[number_of_channels -1 :0] rx_channel_data_align;
21453 tri0[number_of_channels -1 :0] rx_cda_reset;
21455 // LOCAL INTEGER DECLARATION
21471 integer dpll_clk_count[number_of_channels -1: 0];
21473 // INITIAL CONSTRUCT BLOCK
21475 begin : INITIALIZATION
21478 for (i = 0; i < number_of_channels; i = i + 1)
21480 rx_in_reg[i] = 1'b0;
21481 rx_cda_max[i] = 1'b0;
21482 fifo_in_sync_reg[i] = 1'b0;
21483 fifo_out_sync_reg[i] = 1'b0;
21484 bitslip_mux_out[i] = 1'b0;
21486 retime_data[i] = 1'b0;
21489 bitslip_count[i] = 0;
21490 dpll_clk_count[i] = 0;
21491 dpll_lock[i] = 1'b0;
21492 dpll_first_lock[i] = 1'b0;
21493 start_corrupt_bits[i] = 0;
21494 num_corrupt_bits[i] = 0;
21496 for (j = 0; j < RAM_WIDTH; j = j + 1)
21497 ram_array[(i*RAM_WIDTH) + j] = 1'b0;
21499 for (j = 0; j < MUX_WIDTH; j = j + 1)
21500 shift_reg_chain[(i*MUX_WIDTH) + j] = 1'b0;
21503 for (i = 0; i < REGISTER_WIDTH; i = i + 1)
21505 rx_shift_reg[i] = 0;
21506 rx_parallel_load_reg[i] = 0;
21510 end //INITIALIZATION
21512 // ALWAYS CONSTRUCT BLOCK
21514 // Fast clock (on rising edge)
21515 always @ (posedge rx_fastclk)
21516 begin : STRATIXII_DESER
21518 rx_parallel_load_reg <= rx_shift_reg;
21520 for (i1 = 0; i1 < number_of_channels; i1 = i1+1)
21522 for (x=deserialization_factor-1; x >0; x=x-1)
21523 rx_shift_reg[x + (i1 * deserialization_factor)] <= rx_shift_reg [x-1 + (i1 * deserialization_factor)];
21525 rx_shift_reg[i1 * deserialization_factor] <= bitslip_mux_out[i1];
21528 // Registering enable0 signal
21529 enable0_reg <= rx_enable;
21530 end // STRATIXII_DESER
21532 // input synchronization register
21533 always @ (posedge rx_in_reg_clk)
21534 begin : IN_SYNC_REGISTER
21535 rx_in_reg <= rx_in;
21536 end // IN_SYNC_REGISTER
21538 // Stratix II bitslip logic
21539 always @ (posedge rx_cda_reset)
21541 for (i2 = 0; i2 <= number_of_channels-1; i2 = i2 + 1)
21543 if (rx_cda_reset[i2] == 1'b1)
21545 // reset the bitslipping circuitry.
21546 bitslip_count[i2] <= 0;
21547 rx_cda_max[i2] <= 1'b0;
21552 always @ (posedge rx_fastclk)
21553 begin : STRATIXII_BITSLIP
21554 for (i3 = 0; i3 <= number_of_channels-1; i3 = i3 + 1)
21556 if (rx_cda_reset[i3] !== 1'b1)
21558 if ((rx_channel_data_align[i3] === 1'b1) &&
21559 (rx_channel_data_align_pre[i3] === 1'b0))
21561 // slipped data byte is corrupted.
21562 start_corrupt_bits[i3] <= 1;
21563 num_corrupt_bits[i3] <= 1;
21565 // Rollover has occurred. Serial data stream is reset back to 0 latency.
21566 if (bitslip_count[i3] == data_align_rollover)
21568 bitslip_count[i3] <= 0;
21569 rx_cda_max[i3] <= 1'b0;
21573 // increase the bit slip count.
21574 bitslip_count[i3] <= bitslip_count[i3] + 1;
21576 // if maximum of bitslip limit has been reach, set rx_cda_max to high.
21577 // Rollover will occur on the next bit slip.
21578 if (bitslip_count[i3] == data_align_rollover - 1)
21579 rx_cda_max[i3] <= 1'b1;
21582 else if ((rx_channel_data_align[i3] === 1'b0) &&
21583 (rx_channel_data_align_pre[i3] === 1'b1))
21585 start_corrupt_bits[i3] <= 0;
21586 num_corrupt_bits[i3] <= 0;
21590 if (start_corrupt_bits[i3] == 1'b1)
21592 if (num_corrupt_bits[i3]+1 == 3)
21593 start_corrupt_bits[i3] <= 0;
21595 num_corrupt_bits[i3] <= num_corrupt_bits[i3] + 1;
21598 // load serial data stream into the shift register chain.
21599 if ((enable_dpa_mode == "ON") && (rx_dpll_enable[i3] == 1'b1))
21600 shift_reg_chain[(i3*MUX_WIDTH) + 0] <= dpa_fifo_out[i3];
21602 shift_reg_chain[(i3*MUX_WIDTH) + 0] <= rx_in_reg[i3];
21604 // propagate the serial data stream through the bitslip register chain.
21605 for (j1 = 0; j1 < data_align_rollover; j1 = j1 + 1)
21606 shift_reg_chain[(i3*MUX_WIDTH) + j1 + 1] <= shift_reg_chain[(i3*MUX_WIDTH) + j1];
21608 // set the output to 'X' for 3 fast clock cycles after receiving the bitslip signal.
21609 if (((rx_channel_data_align[i3] === 1'b1) && (rx_channel_data_align_pre[i3] === 1'b0)) ||
21610 ((start_corrupt_bits[i3] == 1'b1) && (num_corrupt_bits[i3] < 3) &&
21611 (rx_channel_data_align[i3] === 1'b1)))
21612 bitslip_mux_out[i3] <= 1'bx;
21614 bitslip_mux_out[i3] <= shift_reg_chain[(i3*MUX_WIDTH) + bitslip_count[i3]];
21616 rx_channel_data_align_pre[i3] <= rx_channel_data_align[i3];
21618 end //STRATIXII_BITSLIP
21620 // Stratix II Phase Compensation FIFO
21621 always @ (posedge fifo_write_clk or posedge rx_reset or posedge rx_fifo_reset)
21622 begin : STRATIXII_DPA_FIFO_WRITE
21623 for (i4 = 0; i4 <= number_of_channels-1; i4 = i4 + 1)
21625 if ((rx_reset[i4] == 1'b1) || (rx_fifo_reset[i4] == 1'b1) ||
21626 ((reset_fifo_at_first_lock == "ON") &&
21627 (dpll_first_lock[i4] == 1'b0)))
21630 for (j2 = 0; j2 < RAM_WIDTH; j2 = j2 + 1)
21631 ram_array[(i4*RAM_WIDTH) + j2] <= 1'b0;
21632 fifo_in_sync_reg[i4] <= 1'b0;
21633 write_side_sync_reset[i4] <= 1'b1;
21637 if (write_side_sync_reset[i4] <= 1'b0)
21639 wrPtr[i4] <= wrPtr[i4] + 1;
21640 fifo_in_sync_reg[i4] <= dpa_fifo_in[i4];
21641 ram_array[(i4*RAM_WIDTH) + wrPtr[i4]] <= fifo_in_sync_reg[i4];
21642 if (wrPtr[i4] == 5)
21645 write_side_sync_reset[i4] <= 1'b0;
21648 end //STRATIXII_DPA_FIFO_WRITE
21650 // Stratix II Phase Compensation FIFO
21651 always @ (posedge fifo_read_clk or posedge rx_reset or posedge rx_fifo_reset)
21652 begin : STRATIXII_DPA_FIFO_READ
21653 for (i5 = 0; i5 <= number_of_channels-1; i5 = i5 + 1)
21655 if ((rx_reset[i5] == 1'b1) || (rx_fifo_reset[i5] == 1'b1) ||
21656 ((reset_fifo_at_first_lock == "ON") &&
21657 (dpll_first_lock[i5] == 1'b0)))
21660 fifo_out_sync_reg[i5] <= 1'b0;
21661 read_side_sync_reset[i5] <= 1'b1;
21665 if (read_side_sync_reset[i5] == 1'b0)
21667 rdPtr[i5] <= rdPtr[i5] + 1;
21668 fifo_out_sync_reg[i5] <= ram_array[(i5*RAM_WIDTH) + rdPtr[i5]];
21669 if (rdPtr[i5] == 5)
21672 read_side_sync_reset[i5] <= 1'b0;
21675 end //STRATIXII_DPA_FIFO_READ
21677 // Stratix II DPA Block
21678 always @ (posedge rx_fastclk or posedge rx_reset)
21679 begin : STRATIXII_DPA_BLOCK
21680 for (i6 = 0; i6 <= number_of_channels-1; i6 = i6 + 1)
21682 if (rx_reset[i6] == 1'b1)
21684 dpll_clk_count[i6] <= 0;
21685 dpll_lock[i6] <= 1'b0;
21689 dpll_clk_count[i6] <= dpll_clk_count[i6] + 1;
21691 if (dpll_clk_count[i6] == 2)
21693 dpll_lock[i6] <= 1'b1;
21694 dpll_first_lock[i6] <= 1'b1;
21698 end //STRATIXII_DPA_BLOCK
21700 always @ (posedge rx_fastclk)
21703 retime_data <= dpa_in;
21707 // CONTINOUS ASSIGNMENT
21708 assign rx_out = rx_parallel_load_reg;
21709 assign dpa_fifo_in = retime_data;
21710 assign dpa_fifo_out = fifo_out_sync_reg;
21711 assign fifo_write_clk = rx_fastclk;
21712 assign fifo_read_clk = rx_fastclk;
21713 assign rx_in_reg_clk = rx_fastclk;
21714 assign rx_dpa_locked = dpll_lock;
21715 assign rx_bload = enable0_reg;
21717 endmodule // stratixii_lvds_rx
21720 //START_MODULE_NAME----------------------------------------------------
21722 // Module Name : flexible_lvds_rx
21724 // Description : flexible lvds receiver
21726 // Limitation : Only available to Cyclone and Cyclone II
21729 // Results expected: Deserialized output data.
21731 //END_MODULE_NAME----------------------------------------------------
21733 // BEGINNING OF MODULE
21734 `timescale 1 ps / 1 ps
21736 // MODULE DECLARATION
21737 module flexible_lvds_rx (
21738 rx_in, // input serial data
21739 rx_fastclk, // fast clock from PLL
21740 rx_slowclk, // slow clock from PLL
21741 rx_syncclk, // sync clock from PLL
21742 rx_locked, // lock signal from PLL
21743 rx_out // deserialized output data
21746 // GLOBAL PARAMETER DECLARATION
21747 parameter number_of_channels = 1;
21748 parameter deserialization_factor = 4;
21749 parameter use_extra_ddio_register = "YES";
21750 parameter use_extra_pll_clk = "NO";
21752 // LOCAL PARAMETER DECLARATION
21753 parameter REGISTER_WIDTH = deserialization_factor*number_of_channels;
21755 // INPUT PORT DECLARATION
21756 input [number_of_channels -1 :0] rx_in;
21762 // OUTPUT PORT DECLARATION
21763 output [REGISTER_WIDTH -1: 0] rx_out;
21765 // INTERNAL REGISTERS DECLARATION
21766 reg [REGISTER_WIDTH -1 : 0] rx_shift_reg;
21767 reg [REGISTER_WIDTH -1 : 0] rx_shift_reg1;
21768 reg [REGISTER_WIDTH -1 : 0] rx_shift_reg2;
21769 reg [REGISTER_WIDTH -1 : 0] rx_sync_reg1;
21770 reg [REGISTER_WIDTH -1 : 0] rx_sync_reg2;
21771 reg [REGISTER_WIDTH -1 : 0] rx_sync_reg1_buf1;
21772 reg [REGISTER_WIDTH -1 : 0] rx_sync_reg1_buf1_pipe;
21773 reg [REGISTER_WIDTH -1 : 0] rx_sync_reg2_buf1;
21774 reg [REGISTER_WIDTH -1 : 0] rx_sync_reg1_buf2;
21775 reg [REGISTER_WIDTH -1 : 0] rx_sync_reg1_buf2_pipe;
21776 reg [REGISTER_WIDTH -1 : 0] rx_sync_reg2_buf2;
21777 reg [REGISTER_WIDTH -1 : 0] rx_out_odd;
21778 reg [REGISTER_WIDTH -1 : 0] rx_out_odd_mode;
21779 reg [number_of_channels -1 :0] ddio_h_reg;
21780 reg [number_of_channels -1 :0] ddio_l_reg;
21781 reg [number_of_channels -1 :0] datain_h_reg;
21782 reg [number_of_channels -1 :0] datain_l_reg;
21783 reg [number_of_channels -1 :0] datain_l_latch;
21787 // INTERNAL WIRE DECLARATION
21788 wire [REGISTER_WIDTH -1 : 0] rx_out;
21790 // LOCAL INTEGER DECLARATION
21794 // INITIAL CONSTRUCT BLOCK
21796 begin : INITIALIZATION
21798 rx_shift_reg = {REGISTER_WIDTH{1'b0}};
21799 rx_shift_reg1 = {REGISTER_WIDTH{1'b0}};
21800 rx_shift_reg2 = {REGISTER_WIDTH{1'b0}};
21801 rx_sync_reg1 = {REGISTER_WIDTH{1'b0}};
21802 rx_sync_reg2 = {REGISTER_WIDTH{1'b0}};
21803 rx_sync_reg1_buf1 = {REGISTER_WIDTH{1'b0}};
21804 rx_sync_reg1_buf1_pipe = {REGISTER_WIDTH{1'b0}};
21805 rx_sync_reg2_buf1 = {REGISTER_WIDTH{1'b0}};
21806 rx_sync_reg1_buf2 = {REGISTER_WIDTH{1'b0}};
21807 rx_sync_reg1_buf2_pipe = {REGISTER_WIDTH{1'b0}};
21808 rx_sync_reg2_buf2 = {REGISTER_WIDTH{1'b0}};
21809 rx_out_odd = {REGISTER_WIDTH{1'b0}};
21810 rx_out_odd_mode = {REGISTER_WIDTH{1'b0}};
21811 ddio_h_reg = {number_of_channels{1'b0}};
21812 ddio_l_reg = {number_of_channels{1'b0}};
21813 datain_h_reg = {number_of_channels{1'b0}};
21814 datain_l_reg = {number_of_channels{1'b0}};
21815 datain_l_latch = {number_of_channels{1'b0}};
21819 end //INITIALIZATION
21822 // ALWAYS CONSTRUCT BLOCK
21824 // This always block implements the altddio_in that takes in the input serial
21825 // data of each channel and deserialized it into two parallel data stream
21826 // (ddio_h_reg and ddio_l_reg). Each parallel data stream will be registered
21827 // before send to shift registers.
21828 always @(posedge rx_fastclk)
21830 if (use_extra_ddio_register == "YES")
21832 ddio_h_reg <= rx_in;
21833 datain_h_reg <= ddio_h_reg;
21836 datain_h_reg <= rx_in;
21838 datain_l_reg <= datain_l_latch;
21841 always @(negedge rx_fastclk)
21842 begin : DDIO_IN_LATCH
21843 if (use_extra_ddio_register == "YES")
21845 ddio_l_reg <= rx_in;
21846 datain_l_latch <= ddio_l_reg;
21849 datain_l_latch <= rx_in;
21850 end // DDIO_IN_LATCH
21852 // Loading input data to shift register
21853 always @ (posedge rx_fastclk)
21856 // Implementation for even deserialization factor.
21857 if ((deserialization_factor % 2) == 0)
21859 for (i= 0; i < number_of_channels; i = i+1)
21861 for (x=deserialization_factor-1; x >1; x=x-1)
21862 rx_shift_reg[x + (i * deserialization_factor)] <=
21863 rx_shift_reg [x-2 + (i * deserialization_factor)];
21865 rx_shift_reg[i * deserialization_factor] <= datain_h_reg[i];
21866 rx_shift_reg[(i * deserialization_factor)+1] <= datain_l_reg[i];
21869 else // Implementation for odd deserialization factor.
21871 for (i= 0; i < number_of_channels; i = i+1)
21873 for (x=deserialization_factor-1; x >1; x=x-1)
21875 rx_shift_reg1[x + (i * deserialization_factor)] <=
21876 rx_shift_reg1[x-2 + (i * deserialization_factor)];
21878 rx_shift_reg2[x + (i * deserialization_factor)] <=
21879 rx_shift_reg2[x-2 + (i * deserialization_factor)];
21881 rx_shift_reg1[i * deserialization_factor] <= datain_h_reg[i];
21882 rx_shift_reg1[(i * deserialization_factor)+1] <= datain_l_reg[i];
21883 rx_shift_reg2[i * deserialization_factor] <= rx_shift_reg1[((i+1)* deserialization_factor)-2];
21884 rx_shift_reg2[(i * deserialization_factor)+1] <= rx_shift_reg1[((i+1)* deserialization_factor)-1];
21889 always @ (posedge rx_slowclk)
21891 rx_sync_reg1 <= rx_shift_reg1;
21892 rx_sync_reg2 <= rx_shift_reg2;
21893 rx_sync_reg1_buf2_pipe <= rx_sync_reg1_buf2;
21895 if (rx_locked == 1'b1)
21897 sync_clock <= ~sync_clock;
21898 select_bit <= ~select_bit;
21901 if(use_extra_pll_clk == "NO")
21904 rx_out_odd_mode <= rx_sync_reg1_buf1_pipe;
21906 rx_out_odd_mode <= rx_sync_reg2_buf1;
21911 rx_out_odd_mode <= rx_sync_reg1_buf2_pipe;
21913 rx_out_odd_mode <= rx_sync_reg2_buf2;
21916 rx_out_odd <= rx_out_odd_mode;
21919 always @ (posedge sync_clock)
21921 rx_sync_reg1_buf1 <= rx_sync_reg1;
21922 rx_sync_reg2_buf1 <= rx_sync_reg2;
21923 rx_sync_reg1_buf1_pipe <= rx_sync_reg1_buf1;
21926 always @ (posedge rx_syncclk)
21928 rx_sync_reg1_buf2 <= rx_sync_reg1;
21929 rx_sync_reg2_buf2 <= rx_sync_reg2;
21932 // CONTINOUS ASSIGNMENT
21933 assign rx_out = ((deserialization_factor % 2) == 0) ? rx_shift_reg :
21935 endmodule // flexible_lvds_rx
21939 //START_MODULE_NAME--------------------------------------------------------------
21941 // Module Name : altlvds_tx
21943 // Description : Low Voltage Differential Signaling (LVDS) transmitter
21944 // megafunction. The altlvds_tx megafunction implements a
21945 // serialization transmitter. LVDS is a high speed IO
21946 // interface that uses inputs without a reference voltage.
21947 // LVDS uses two wires carrying differential values to
21948 // create a single channel. These wires are connected to two
21949 // pins on supported device to create a single LVDS channel
21951 // Limitation : Only available for APEX20KE, APEXII, MERCURY, STRATIX,
21952 // STRATIX GX, STRATIX II, CYCLONE and CYCLONEII families.
21954 // Results expected: Output clock, serialized output data and pll locked signal.
21956 //END_MODULE_NAME----------------------------------------------------------------
21958 // BEGINNING OF MODULE
21959 `timescale 1 ps / 1 ps
21961 module altlvds_tx (
21976 // GLOBAL PARAMETER DECLARATION
21978 // No. of LVDS channels (required)
21979 parameter number_of_channels = 1;
21981 // No. of bits per channel (required)
21982 parameter deserialization_factor = 4;
21984 // Indicates whether the tx_in[] and tx_outclock ports should be registered.
21985 parameter registered_input = "ON";
21987 // "ON" means that sync_inclock is also used
21988 // (not used for Stratix and Stratix GX devices.)
21989 parameter multi_clock = "OFF";
21991 // The period of the input clock in ps (Required)
21992 parameter inclock_period = 10000;
21994 // Specifies the period of the tx_outclock port as
21995 // [INCLOCK_PERIOD * OUTCLOCK_DIVIDE_BY]
21996 parameter outclock_divide_by = deserialization_factor;
21998 // The effective clock period to sample output data
21999 parameter inclock_boost = deserialization_factor;
22001 // Aligns the Most Significant Bit(MSB) to the falling edge of the clock
22002 // instead of the rising edge. (only for APEX II devices)
22003 parameter center_align_msb = "OFF";
22005 // The device family to be used.
22006 parameter intended_device_family = "APEX20KE";
22008 // Data rate out of the PLL. (required and only for Stratix and
22009 // Stratix GX devices)
22010 parameter output_data_rate = 0;
22012 // The alignment of the input data with respect to the tx_inclock port.
22013 // (required and only for Stratix and Stratix GX devices)
22014 parameter inclock_data_alignment = "EDGE_ALIGNED";
22016 // The alignment of the output data with respect to the tx_outclock port.
22017 // (required and only for Stratix and Stratix GX devices)
22018 parameter outclock_alignment = "EDGE_ALIGNED";
22020 // Specifies whether the compiler uses the same PLL for both the LVDS
22021 // receiver and the LVDS transmitter
22022 parameter common_rx_tx_pll = "ON";
22024 parameter outclock_resource = "AUTO";
22025 parameter use_external_pll = "OFF";
22026 parameter implement_in_les = "OFF";
22027 parameter preemphasis_setting = 0;
22028 parameter vod_setting = 0;
22029 parameter differential_drive = 0;
22031 parameter lpm_type = "altlvds_tx";
22032 parameter lpm_hint = "UNUSED";
22034 // Specifies whether the source of the input clock is from a PLL
22035 parameter clk_src_is_pll = "off";
22038 // LOCAL PARAMETER DECLARATION
22040 // A APEX20KE type of LVDS?
22041 parameter APEX20KE_TX_STYLE = (intended_device_family == "APEX20KE") ||
22042 (intended_device_family == "EXCALIBUR_ARM") ||
22043 (intended_device_family == "EXCALIBUR_MIPS") ||
22044 (intended_device_family == "APEX20KC")
22047 // A APEXII type of LVDS?
22048 parameter APEXII_TX_STYLE = (intended_device_family == "APEXII") ||
22049 (intended_device_family == "APEX II")
22052 // A MERCURY type of LVDS?
22053 parameter MERCURY_TX_STYLE = (intended_device_family == "MERCURY") ||
22054 (intended_device_family == "Mercury")
22057 // A STRATIX type of LVDS?
22058 parameter STRATIX_TX_STYLE = (intended_device_family == "Stratix") ||
22059 (intended_device_family == "STRATIX") ||
22060 (intended_device_family == "STRATIXGX") ||
22061 (intended_device_family == "STRATIX-GX") ||
22062 (intended_device_family == "Stratix GX") ||
22063 (intended_device_family == "HardCopy Stratix") ||
22064 (intended_device_family == "HARDCOPY STRATIX") ||
22065 (intended_device_family == "hardcopy stratix") ||
22066 (intended_device_family == "HardcopyStratix") ||
22067 (intended_device_family == "HARDCOPYSTRATIX") ||
22068 (intended_device_family == "hardcopystratix")
22071 // A STRATIXII type of LVDS?
22072 parameter STRATIXII_TX_STYLE = ((intended_device_family == "Stratix II") ||
22073 (intended_device_family == "StratixII") ||
22074 (intended_device_family == "HardCopy II") ||
22075 (intended_device_family == "HardCopyII") ||
22076 (intended_device_family == "HARDCOPY II") ||
22077 (intended_device_family == "HARDCOPYII") ||
22078 (intended_device_family == "hardcopy ii") ||
22079 (intended_device_family == "hardcopyii") ||
22080 (intended_device_family == "Stratix II GX") ||
22081 (intended_device_family == "STRATIX II GX") ||
22082 (intended_device_family == "stratix ii gx") ||
22083 (intended_device_family == "StratixIIGX") ||
22084 (intended_device_family == "STRATIXIIGX") ||
22085 (intended_device_family == "stratixiigx"))
22088 // A Cyclone type of LVDS?
22089 parameter CYCLONE_TX_STYLE = ((intended_device_family == "Cyclone") ||
22090 (intended_device_family == "CYCLONE") ||
22091 (intended_device_family == "cyclone"))
22094 // A Cyclone II type of LVDS?
22095 parameter CYCLONEII_TX_STYLE = ((intended_device_family == "Cyclone II") ||
22096 (intended_device_family == "CYCLONE II") ||
22097 (intended_device_family == "cyclone ii") ||
22098 (intended_device_family == "Cycloneii") ||
22099 (intended_device_family == "CYCLONEII") ||
22100 (intended_device_family == "cycloneii"))
22103 // Is the device family has flexible LVDS?
22104 parameter FAMILY_HAS_FLEXIBLE_LVDS = ((CYCLONE_TX_STYLE == 1) ||
22105 (CYCLONEII_TX_STYLE == 1) ||
22106 (((STRATIX_TX_STYLE == 1) || (STRATIXII_TX_STYLE == 1)) &&
22107 (implement_in_les == "ON")))
22110 // Is the family has Stratix style PLL
22111 parameter FAMILY_HAS_STRATIX_STYLE_PLL = ((STRATIX_TX_STYLE == 1) ||
22112 (CYCLONE_TX_STYLE == 1))
22115 // Is the family has Stratix style PLL
22116 parameter FAMILY_HAS_STRATIXII_STYLE_PLL = ((STRATIXII_TX_STYLE == 1) ||
22117 (CYCLONEII_TX_STYLE == 1))
22120 // Parameter to check whether the selected lvds trasmitter use
22121 // holding register or not.
22122 parameter TX_NEED_HOLD = (((APEX20KE_TX_STYLE == 1) &&
22123 (deserialization_factor >= 7)) ||
22124 ((APEXII_TX_STYLE == 1) &&
22125 (deserialization_factor >= 5)) ||
22126 ((MERCURY_TX_STYLE == 1) &&
22127 (deserialization_factor >= 7)))
22130 // calculate clock boost for device family other than STRATIX and STRATIX GX
22131 parameter INT_CLOCK_BOOST = (APEX20KE_TX_STYLE == 1)
22132 ? deserialization_factor :
22133 ((inclock_boost == 0)
22134 ? deserialization_factor
22137 // M value for Stratix/Stratix II/Cyclone/Cyclone II PLL
22138 parameter PLL_M_VALUE = (((output_data_rate * inclock_period)
22139 + (5 * 100000)) / 1000000);
22141 // D value for Stratix/Stratix II/Cyclone/Cyclone II PLL
22142 parameter PLL_D_VALUE = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
22143 ? ((output_data_rate !=0) && (inclock_period !=0)
22148 // calculate clock boost for STRATIX, STRATIX GX and STRATIX II
22149 parameter STRATIX_INCLOCK_BOOST =
22150 ((output_data_rate !=0) && (inclock_period !=0))
22152 ((inclock_boost == 0)
22153 ? deserialization_factor
22156 // parameter for inclock phase shift. Add 0.5 to the calculated result to
22157 // round up result to the nearest integer.
22158 // CENTER_ALIGNED means 180 degrees
22159 parameter PHASE_INCLOCK = (inclock_data_alignment == "EDGE_ALIGNED")?
22161 (inclock_data_alignment == "CENTER_ALIGNED") ?
22162 (0.5 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5:
22163 (inclock_data_alignment == "45_DEGREES") ?
22164 (0.125 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5:
22165 (inclock_data_alignment == "90_DEGREES") ?
22166 (0.25 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5:
22167 (inclock_data_alignment == "135_DEGREES") ?
22168 (0.375 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5:
22169 (inclock_data_alignment == "180_DEGREES") ?
22170 (0.5 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5:
22171 (inclock_data_alignment == "225_DEGREES") ?
22172 (0.625 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5:
22173 (inclock_data_alignment == "270_DEGREES") ?
22174 (0.75 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5:
22175 (inclock_data_alignment == "315_DEGREES") ?
22176 (0.875 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5: 0;
22178 // parameter for Stratix II inclock phase shift.
22179 parameter STXII_PHASE_INCLOCK = PHASE_INCLOCK - (0.5 * inclock_period / STRATIX_INCLOCK_BOOST);
22181 // parameter for outclock phase shift. Add 0.5 to the calculated result to
22182 // round up result to the nearest integer.
22183 parameter PHASE_OUTCLOCK = (outclock_alignment == "EDGE_ALIGNED") ?
22185 (outclock_alignment == "CENTER_ALIGNED") ?
22186 ((0.5 * inclock_period / STRATIX_INCLOCK_BOOST) +
22188 (outclock_alignment == "45_DEGREES") ?
22189 ((0.125 * inclock_period / STRATIX_INCLOCK_BOOST) +
22191 (outclock_alignment == "90_DEGREES") ?
22192 ((0.25 * inclock_period / STRATIX_INCLOCK_BOOST) +
22194 (outclock_alignment == "135_DEGREES") ?
22195 ((0.375 * inclock_period / STRATIX_INCLOCK_BOOST) +
22197 (outclock_alignment == "180_DEGREES") ?
22198 ((0.5 * inclock_period / STRATIX_INCLOCK_BOOST) +
22200 (outclock_alignment == "225_DEGREES") ?
22201 ((0.625 * inclock_period / STRATIX_INCLOCK_BOOST) +
22203 (outclock_alignment == "270_DEGREES") ?
22204 ((0.75 * inclock_period / STRATIX_INCLOCK_BOOST) +
22206 (outclock_alignment == "315_DEGREES") ?
22207 ((0.875 * inclock_period / STRATIX_INCLOCK_BOOST) +
22210 // parameter for Stratix and Stratix GX outclock phase shift.
22211 // Add 0.5 to the calculated result to round up result to the nearest integer.
22212 parameter STX_PHASE_OUTCLOCK = ((outclock_divide_by == 1) ||
22213 (outclock_alignment == "45_DEGREES") ||
22214 (outclock_alignment == "90_DEGREES") ||
22215 (outclock_alignment == "135_DEGREES")) ?
22216 PHASE_OUTCLOCK + PHASE_INCLOCK:
22217 ((outclock_alignment == "180_DEGREES") ||
22218 (outclock_alignment == "CENTER_ALIGNED")) ?
22220 (outclock_alignment == "225_DEGREES") ?
22221 ((0.125 * inclock_period / STRATIX_INCLOCK_BOOST) +
22222 0.5 + PHASE_INCLOCK):
22223 (outclock_alignment == "270_DEGREES") ?
22224 ((0.25 * inclock_period / STRATIX_INCLOCK_BOOST) +
22225 0.5 + PHASE_INCLOCK):
22226 (outclock_alignment == "315_DEGREES") ?
22227 ((0.375 * inclock_period / STRATIX_INCLOCK_BOOST) +
22228 0.5 + PHASE_INCLOCK): PHASE_INCLOCK;
22230 // parameter for Stratix II outclock phase shift.
22231 parameter STXII_PHASE_OUTCLOCK = STX_PHASE_OUTCLOCK - (0.5 * inclock_period / STRATIX_INCLOCK_BOOST);
22233 parameter REGISTER_WIDTH = deserialization_factor * number_of_channels;
22235 // input clock period for PLL.
22236 parameter CLOCK_PERIOD = (deserialization_factor > 2) ? inclock_period : 10000;
22239 // INPUT PORT DECLARATION
22241 // Input data (required)
22242 input [REGISTER_WIDTH -1 : 0] tx_in;
22244 // Input clock (required)
22249 // Optional clock for input registers (Required if "multi_clock" parameters
22251 input sync_inclock;
22253 // Enable control for the LVDS PLL
22254 input tx_pll_enable;
22256 // Asynchronously resets all counters to initial values (only for Stratix
22257 // and Stratix GX devices)
22262 // OUTPUT PORT DECLARATION
22264 // Serialized data signal(required)
22265 output [number_of_channels-1 :0] tx_out;
22267 // External reference clock
22268 output tx_outclock;
22270 // Output clock used to feed non-peripheral logic.
22271 // Only available for Mercury, Stratix, and Stratix GX devices only.
22272 output tx_coreclock;
22274 // Gives the status of the LVDS PLL
22275 // (when the PLL is locked, this signal is VCC. GND otherwise)
22279 // INTERNAL REGISTERS DECLARATION
22281 reg [REGISTER_WIDTH -1 : 0] tx_hold_reg;
22282 reg [REGISTER_WIDTH -1 : 0] tx_in_reg;
22283 reg [REGISTER_WIDTH -1 : 0] tx_shift_reg;
22284 reg [REGISTER_WIDTH -1 : 0] tx_parallel_load_reg;
22285 reg tx_mercury_core_clock;
22287 reg [number_of_channels-1 :0] tx_out_apex;
22288 reg [number_of_channels-1 :0] tx_out_stratix;
22289 reg [number_of_channels-1 :0] tx_ddio_out;
22290 reg [number_of_channels-1 :0] dataout_l;
22291 reg [number_of_channels-1 :0] dataout_h;
22295 reg tx_fastclk_pre;
22296 reg [9 : 0] stx_phase_shift_txdata;
22297 reg [9 : 0] phase_shift_txdata;
22300 // INTERNAL WIRE DECLARATION
22302 wire [REGISTER_WIDTH -1 : 0] tx_in_int;
22307 wire tx_coreclock_int;
22308 wire tx_locked_int;
22309 wire unused_clk_ext;
22310 wire [2:0] altclklock_clk;
22311 wire altclklock_locked;
22312 wire altclklock_inclock;
22313 wire altclklock_clkena;
22314 wire [1:0] stratix_pll_inclock;
22315 wire [1:0] stratixii_pll_inclock;
22316 wire [5:0] stratix_pll_outclock;
22317 wire [5:0] stratixii_pll_outclock;
22318 wire stratix_pll_enable;
22319 wire stratixii_pll_enable;
22320 wire stratix_pll_areset;
22321 wire stratixii_pll_areset;
22322 wire stratix_locked;
22323 wire stratixii_locked;
22324 wire stratix_enable0;
22325 wire stratixii_enable0;
22326 wire stratix_enable1;
22327 wire stratixii_enable1;
22328 wire stratix_outclock;
22329 wire stratixii_outclock;
22330 wire stratixii_sclkout0;
22331 wire stratixii_sclkout1;
22332 wire stratix_inclock;
22333 wire stratix_enable;
22334 wire stratixii_inclock;
22335 wire stratixii_enable;
22336 wire flvds_fastclk;
22337 wire flvds_slowclk;
22339 wire[number_of_channels-1 :0] flvds_dataout;
22341 // INTERNAL TRI DECLARATION
22345 tri1 tx_pll_enable;
22348 // LOCAL INTEGER DECLARATION
22354 integer posedge_count;
22355 integer negedge_count;
22356 integer shift_data;
22358 // LOCAL TIME DECLARATION
22362 // COMPONENT INSTANTIATIONS
22363 ALTERA_DEVICE_FAMILIES dev ();
22365 // INITIAL CONSTRUCT BLOCK
22368 begin : INITIALIZATION
22369 tx_in_reg = {REGISTER_WIDTH{1'b0}};
22370 tx_hold_reg = {REGISTER_WIDTH{1'b0}};
22371 tx_parallel_load_reg = {REGISTER_WIDTH{1'b0}};
22372 tx_shift_reg = {REGISTER_WIDTH{1'b0}};
22374 tx_out_apex = {number_of_channels{1'b0}};
22375 tx_out_stratix = {number_of_channels{1'b0}};
22376 tx_ddio_out = {number_of_channels{1'b0}};
22377 dataout_l = {number_of_channels{1'b0}};
22378 dataout_h = {number_of_channels{1'b0}};
22386 tx_out_delay = inclock_period/(deserialization_factor*2);
22388 // Input data needed by stratix_tx_outclk in order to generate the tx_outclock.
22389 stx_phase_shift_txdata = 0;
22390 if (outclock_divide_by > 1)
22392 if (deserialization_factor == 4)
22394 if ( outclock_divide_by == 2)
22395 stx_phase_shift_txdata[3:0] = 4'b1010;
22396 else if (outclock_divide_by == 4)
22397 stx_phase_shift_txdata[3:0] = 4'b0011;
22399 else if (deserialization_factor == 8)
22401 if (outclock_divide_by == 2)
22402 stx_phase_shift_txdata[7:0] = 8'b10101010;
22403 else if (outclock_divide_by == 4)
22404 stx_phase_shift_txdata[7:0] = 8'b00110011;
22405 else if (outclock_divide_by == 8)
22406 stx_phase_shift_txdata[7:0] = 8'b11000011;
22408 else if (deserialization_factor == 10)
22410 if (outclock_divide_by == 2)
22411 stx_phase_shift_txdata[9:0] = 10'b1010101010;
22412 else if (outclock_divide_by == 10)
22413 stx_phase_shift_txdata[9:0] = 10'b1110000011;
22415 else if (deserialization_factor == 7)
22416 if (outclock_divide_by == 7)
22417 stx_phase_shift_txdata[6:0] = 7'b1100011;
22420 // Input data needed by stratixii_tx_outclk in order to generate the tx_outclock.
22421 phase_shift_txdata = 0;
22422 if (outclock_divide_by > 1)
22424 if (deserialization_factor == 4)
22426 if ( outclock_divide_by == 2)
22427 phase_shift_txdata[3:0] = 4'b1010;
22428 else if (outclock_divide_by == 4)
22429 phase_shift_txdata[3:0] = 4'b1100;
22431 else if (deserialization_factor == 6)
22433 if (outclock_divide_by == 2)
22434 phase_shift_txdata[5:0] = 6'b101010;
22435 else if (outclock_divide_by == 6)
22436 phase_shift_txdata[5:0] = 6'b111000;
22438 else if (deserialization_factor == 8)
22440 if (outclock_divide_by == 2)
22441 phase_shift_txdata[7:0] = 8'b10101010;
22442 else if (outclock_divide_by == 4)
22443 phase_shift_txdata[7:0] = 8'b11001100;
22444 else if (outclock_divide_by == 8)
22445 phase_shift_txdata[7:0] = 8'b11110000;
22447 else if (deserialization_factor == 10)
22449 if (outclock_divide_by == 2)
22450 phase_shift_txdata[9:0] = 10'b1010101010;
22451 else if (outclock_divide_by == 10)
22452 phase_shift_txdata[9:0] = 10'b1111100000;
22454 else if (deserialization_factor == 7)
22455 if (outclock_divide_by == 7)
22456 phase_shift_txdata[6:0] = 7'b1111000;
22459 // Check for illegal mode settings
22460 if ((APEX20KE_TX_STYLE == 1) && (deserialization_factor != 1) &&
22461 (deserialization_factor != 4) && (deserialization_factor != 7) &&
22462 (deserialization_factor != 8))
22464 $display ($time, "ps Error: APEX20KE does not support the specified deserialization factor!");
22467 else if ((MERCURY_TX_STYLE == 1) &&
22468 (deserialization_factor != 1) && (deserialization_factor != 2) &&
22469 (((deserialization_factor > 12) &&
22470 (deserialization_factor != 14) &&
22471 (deserialization_factor != 16) &&
22472 (deserialization_factor != 18) &&
22473 (deserialization_factor != 20)) ||(deserialization_factor < 3)))
22475 $display ($time, "ps Error: MERCURY does not support the specified deserialization factor!");
22478 else if (((APEXII_TX_STYLE == 1)) &&
22479 ((deserialization_factor > 10) || (deserialization_factor < 4)) &&
22480 (deserialization_factor != 1) && (deserialization_factor != 2))
22482 $display ($time, "ps Error: APEXII does not support the specified deserialization factor!");
22485 else if ((STRATIX_TX_STYLE == 1) &&
22486 (deserialization_factor != 1) && (deserialization_factor != 2) &&
22487 ((deserialization_factor > 10) || (deserialization_factor < 4)))
22489 $display ($time, "ps Error: STRATIX does not support the specified deserialization factor!");
22492 else if ((STRATIXII_TX_STYLE == 1) &&
22493 (deserialization_factor > 10))
22495 $display ($time, "ps Error: STRATIX II does not support the specified deserialization factor!");
22499 if (CYCLONE_TX_STYLE == 1)
22501 if ((use_external_pll == "ON") &&
22502 (deserialization_factor != 1) && (deserialization_factor != 2) &&
22503 (deserialization_factor != 4) && (deserialization_factor != 6) &&
22504 (deserialization_factor != 8) && (deserialization_factor != 10))
22506 $display ($time, "ps Error: Cyclone does not support the specified deserialization factor when use_external_pll is 'ON'!");
22509 else if ((deserialization_factor > 10) || (deserialization_factor == 3))
22511 $display ($time, "ps Error: Cyclone does not support the specified deserialization factor when use_external_pll is 'OFF'!");
22516 if (CYCLONEII_TX_STYLE == 1)
22518 if ((use_external_pll == "ON") &&
22519 (deserialization_factor != 1) && (deserialization_factor != 2) &&
22520 (deserialization_factor != 4) && (deserialization_factor != 6) &&
22521 (deserialization_factor != 8) && (deserialization_factor != 10))
22523 $display ($time, "ps Error: Cyclone II does not support the specified deserialization factor when use_external_pll is 'ON'!");
22526 else if ((deserialization_factor > 10) || (deserialization_factor == 3))
22528 $display ($time, "ps Error: Cyclone II does not support the specified deserialization factor when use_external_pll is 'OFF'!");
22533 if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
22535 $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
22539 if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
22541 $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
22545 end // INITIALIZATION
22548 // COMPONENT INSTANTIATIONS
22550 // PLL for device family other than Stratix, Stratix GX and Stratix II
22552 .inclock(altclklock_inclock), // Required
22553 .inclocken(altclklock_clkena),
22555 .clock0(altclklock_clk[0]),
22556 .clock1(altclklock_clk[1]),
22557 .clock2(altclklock_clk[2]),
22558 .clock_ext(unused_clk_ext),
22559 .locked(altclklock_locked));
22562 u0.inclock_period = CLOCK_PERIOD,
22563 u0.clock0_boost = INT_CLOCK_BOOST,
22564 u0.clock1_boost = INT_CLOCK_BOOST,
22565 u0.clock1_divide = deserialization_factor,
22566 u0.clock2_boost = (MERCURY_TX_STYLE == 1) ?
22567 INT_CLOCK_BOOST : 1,
22568 u0.clock2_divide = (MERCURY_TX_STYLE == 1) ?
22569 outclock_divide_by : 1,
22570 u0.valid_lock_cycles = (APEXII_TX_STYLE == 1) ? 1 :
22571 (MERCURY_TX_STYLE == 1) ? 3 : 5,
22572 u0.intended_device_family = ((APEX20KE_TX_STYLE == 1 ) ||
22573 (APEXII_TX_STYLE == 1 ) ||
22574 (MERCURY_TX_STYLE == 1 ))
22575 ? intended_device_family
22579 // PLL for Stratix and Stratix GX
22580 MF_stratix_pll u1 (
22581 .inclk(stratix_pll_inclock), // Required
22582 .ena(stratix_pll_enable),
22583 .areset(stratix_pll_areset),
22584 .clkena(6'b111111),
22585 .clk (stratix_pll_outclock),
22586 .locked(stratix_locked),
22597 .enable0(stratix_enable0),
22598 .enable1(stratix_enable1),
22604 u1.primary_clock = "inclk0",
22605 u1.pll_type = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
22608 u1.inclk0_input_frequency = CLOCK_PERIOD,
22609 u1.valid_lock_multiplier = 1,
22610 u1.clk0_multiply_by = STRATIX_INCLOCK_BOOST,
22611 u1.clk0_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
22614 u1.clk0_phase_shift_num = PHASE_INCLOCK,
22615 u1.clk1_multiply_by = STRATIX_INCLOCK_BOOST,
22616 u1.clk1_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
22617 ? PLL_D_VALUE*outclock_divide_by
22619 u1.clk1_phase_shift_num = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
22621 : STX_PHASE_OUTCLOCK,
22622 u1.clk2_multiply_by = STRATIX_INCLOCK_BOOST,
22623 u1.clk2_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
22624 ? ((deserialization_factor%2 == 0)
22625 ? PLL_D_VALUE*deserialization_factor/2
22626 : PLL_D_VALUE*deserialization_factor)
22627 : deserialization_factor,
22628 u1.clk2_phase_shift_num = PHASE_INCLOCK,
22629 u1.simulation_type = "functional",
22632 // PLL for Stratix II
22633 MF_stratixii_pll u2 (
22634 .inclk(stratixii_pll_inclock), // Required
22635 .ena(stratixii_pll_enable),
22636 .areset(stratixii_pll_areset),
22637 .clk (stratixii_pll_outclock ),
22638 .locked(stratixii_locked),
22648 .enable0(stratixii_enable0),
22649 .enable1(stratixii_enable1),
22654 .sclkout({stratixii_sclkout1, stratixii_sclkout0}),
22659 u2.primary_clock = "inclk0",
22660 u2.pll_type = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
22663 u2.vco_multiply_by = STRATIX_INCLOCK_BOOST,
22664 u2.vco_divide_by = 1,
22665 u2.inclk0_input_frequency = CLOCK_PERIOD,
22666 u2.clk0_multiply_by = STRATIX_INCLOCK_BOOST,
22667 u2.clk0_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
22669 : deserialization_factor,
22670 u2.clk0_phase_shift_num = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
22672 : STXII_PHASE_INCLOCK,
22673 u2.clk1_multiply_by = STRATIX_INCLOCK_BOOST,
22674 u2.clk1_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
22675 ? PLL_D_VALUE*outclock_divide_by
22676 : deserialization_factor,
22677 u2.clk1_phase_shift_num = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
22679 : STXII_PHASE_OUTCLOCK,
22680 u2.clk2_multiply_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
22681 ? STRATIX_INCLOCK_BOOST
22683 u2.clk2_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
22684 ? ((deserialization_factor%2 == 0)
22685 ? PLL_D_VALUE*deserialization_factor/2
22686 : PLL_D_VALUE*deserialization_factor)
22688 u2.clk2_phase_shift_num = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
22691 u2.sclkout0_phase_shift = STXII_PHASE_INCLOCK,
22692 u2.sclkout1_phase_shift = STXII_PHASE_OUTCLOCK,
22693 u2.simulation_type = "functional",
22697 // This module produces output clock for Stratix and Stratix GX.
22698 stratix_tx_outclk u3 (
22699 .tx_in(stx_phase_shift_txdata),
22700 .tx_fastclk(stratix_inclock),
22701 .tx_enable(stratix_enable),
22702 .tx_out(stratix_outclock));
22704 u3.deserialization_factor = deserialization_factor,
22705 u3.bypass_serializer = (outclock_divide_by == 1) ?
22707 u3.use_falling_clock_edge = ((outclock_alignment == "180_DEGREES") ||
22708 (outclock_alignment == "CENTER_ALIGNED") ||
22709 (outclock_alignment == "225_DEGREES") ||
22710 (outclock_alignment == "270_DEGREES") ||
22711 (outclock_alignment == "315_DEGREES")) ?
22715 // This module produces output clock for StratixII.
22716 stratixii_tx_outclk u4 (
22717 .tx_in(phase_shift_txdata),
22718 .tx_fastclk(stratixii_inclock),
22719 .tx_enable(stratixii_enable),
22720 .tx_out(stratixii_outclock));
22723 u4.deserialization_factor = deserialization_factor,
22724 u4.bypass_serializer = (outclock_divide_by == 1) ?
22726 u4.use_falling_clock_edge = ((outclock_alignment == "180_DEGREES") ||
22727 (outclock_alignment == "CENTER_ALIGNED") ||
22728 (outclock_alignment == "225_DEGREES") ||
22729 (outclock_alignment == "270_DEGREES") ||
22730 (outclock_alignment == "315_DEGREES")) ?
22733 // This module produces output clock for StratixII.
22734 flexible_lvds_tx u5 (
22736 .tx_fastclk(flvds_fastclk),
22737 .tx_slowclk(flvds_slowclk),
22738 .tx_regclk(flvds_regclk),
22739 .tx_locked(tx_locked_int),
22740 .tx_out(flvds_dataout));
22743 u5.number_of_channels = number_of_channels,
22744 u5.deserialization_factor = deserialization_factor,
22745 u5.registered_input = registered_input;
22747 // ALWAYS CONSTRUCT BLOCK
22749 // For x2 mode. For each data channel, input data are separated into 2 data
22750 // stream which will be transmitted on different edge of input clock.
22751 always @ (posedge tx_inclock)
22752 begin : DDIO_OUT_RECEIVE
22753 if (deserialization_factor == 2)
22755 for (i1 = 0; i1 < number_of_channels; i1 = i1 +1)
22757 dataout_l[i1] <= tx_in_int[i1*2];
22758 dataout_h[i1] <= tx_in_int[i1*2+1];
22761 end // DDIO_OUT_RECEIVE
22764 always @ (posedge tx_fastclk)
22765 begin : FAST_CLOCK_POS
22766 if (deserialization_factor > 2)
22769 // registering load enable signal
22770 enable0_reg2 <= enable0_reg1;
22771 enable0_reg1 <= (use_external_pll == "ON") ? tx_enable :
22772 (STRATIX_TX_STYLE == 1) ? stratix_enable0 :
22775 if ((STRATIX_TX_STYLE == 0) && (STRATIXII_TX_STYLE == 0))
22777 posedge_count <= (posedge_count+1) % deserialization_factor;
22778 if (posedge_count == 2)
22780 // register incoming data on the third edge
22781 tx_shift_reg <= tx_parallel_load_reg;
22783 for (i = 0; i < number_of_channels; i = i +1)
22784 // Data in MSB gets shifted out first.
22785 // NB: This happens 1/2clk cycle later for APEXII (MSB
22786 // only) when center_align_msb is ON.
22788 if ((i == number_of_channels-1) &&
22789 ((APEXII_TX_STYLE == 1)) &&
22790 (center_align_msb == "ON"))
22792 tx_out_apex[i] <= #tx_out_delay
22793 tx_parallel_load_reg[(i+1)*deserialization_factor - 1];
22797 tx_out_apex[i] <= tx_parallel_load_reg[(i+1)*deserialization_factor - 1];
22804 count <= count + 1;
22805 for (i = 0; i < number_of_channels; i = i +1)
22806 // Data in MSB gets shifted out first.
22807 // NB: This happens 1/2clk cycle later for APEXII (MSB
22808 // only) when center_align_msb is ON.
22810 if ((i == number_of_channels-1) &&
22811 ((APEXII_TX_STYLE == 1)) &&
22812 (center_align_msb == "ON"))
22814 tx_out_apex[i] <= #tx_out_delay
22815 tx_shift_reg[(i+1)*deserialization_factor - count];
22819 tx_out_apex[i] <= tx_shift_reg[(i+1)*deserialization_factor - count];
22824 // Mercury core clock is assymmetrical for odd deserialization
22826 if (posedge_count == ((deserialization_factor+1)/2+1))
22828 tx_mercury_core_clock <= ~tx_mercury_core_clock;
22833 if(((STRATIX_TX_STYLE == 1) && (enable0_neg == 1)) ||
22834 ((STRATIXII_TX_STYLE == 1) && (enable0_reg1 == 1)))
22836 tx_shift_reg <= tx_parallel_load_reg;
22839 for (i = 0; i < number_of_channels; i = i +1)
22841 tx_out_stratix[i] <= tx_parallel_load_reg[(i+1)*deserialization_factor - 1];
22846 count <= (count % deserialization_factor) + 1;
22847 for (i = 0; i < number_of_channels; i = i +1)
22849 tx_out_stratix[i] <= tx_shift_reg[(i+1)*deserialization_factor - count];
22853 // Loading data to parallel load register for Stratix and
22855 if (((STRATIX_TX_STYLE == 1) && (stratix_enable0 == 1)) ||
22856 (STRATIXII_TX_STYLE == 1))
22858 tx_parallel_load_reg <= tx_in_int;
22862 end // FAST_CLOCK_POS
22864 always @ (negedge tx_fastclk)
22865 begin : FAST_CLOCK_NEG
22866 if (deserialization_factor > 2)
22868 // registering load enable signal
22869 enable0_neg <= enable0_reg2;
22871 negedge_count <= negedge_count + 1;
22873 // Loading data to parallel load register for non-STRATIX family
22874 if ((negedge_count == 2) && (STRATIX_TX_STYLE == 0) &&
22875 (STRATIXII_TX_STYLE == 0) &&
22876 (tx_locked_int == 1))
22878 if (TX_NEED_HOLD == 1)
22880 tx_parallel_load_reg <= tx_hold_reg;
22884 tx_parallel_load_reg <= tx_in_int;
22888 end // FAST_CLOCK_NEG
22891 always @ (posedge tx_slowclk)
22893 negedge_count <= 0;
22894 tx_mercury_core_clock <= tx_slowclk;
22897 // synchronization register
22898 always @ (posedge tx_reg_clk)
22899 begin : SYNC_REGISTER
22900 tx_in_reg <= #5 tx_in;
22901 end // SYNC_REGISTER
22904 always @ (negedge tx_hold_clk)
22905 begin : HOLD_REGISTER
22906 if (deserialization_factor > 1)
22908 tx_hold_reg <= tx_in_int;
22910 end // HOLD_REGISTER
22913 // CONTINOUS ASSIGNMENT
22914 assign tx_out = (deserialization_factor == 1)
22916 (deserialization_factor == 2)
22917 ? ((tx_inclock == 1) ? dataout_h : dataout_l) :
22918 (FAMILY_HAS_FLEXIBLE_LVDS == 1)
22920 ((STRATIX_TX_STYLE == 1) || (STRATIXII_TX_STYLE == 1))
22924 assign tx_in_int = (registered_input != "OFF")
22928 assign tx_reg_clk = ((STRATIX_TX_STYLE == 1) ||
22929 (((STRATIXII_TX_STYLE == 1) ||
22930 (CYCLONE_TX_STYLE == 1) ||
22931 (CYCLONEII_TX_STYLE == 1)) &&
22932 (use_external_pll == "OFF")))
22933 ? ((registered_input == "TX_CLKIN")
22935 : tx_coreclock_int) :
22936 (((registered_input == "ON") &&
22937 (multi_clock == "ON"))
22941 assign tx_hold_clk = (multi_clock == "ON")
22943 ((MERCURY_TX_STYLE == 1)
22947 assign tx_outclock = (deserialization_factor < 3)
22949 ((FAMILY_HAS_FLEXIBLE_LVDS == 1) &&
22950 (FAMILY_HAS_STRATIX_STYLE_PLL == 1))
22951 ? stratix_pll_outclock[1] :
22952 ((FAMILY_HAS_FLEXIBLE_LVDS == 1) &&
22953 (FAMILY_HAS_STRATIXII_STYLE_PLL == 1))
22954 ? stratixii_pll_outclock[1] :
22955 (STRATIX_TX_STYLE == 1)
22956 ? stratix_outclock :
22957 (STRATIXII_TX_STYLE == 1)
22958 ? stratixii_outclock :
22959 (MERCURY_TX_STYLE == 1)
22960 ? altclklock_clk[2] :
22961 (APEXII_TX_STYLE == 1)
22965 assign tx_coreclock = tx_coreclock_int;
22967 assign tx_coreclock_int = (deserialization_factor < 3)
22969 (FAMILY_HAS_FLEXIBLE_LVDS == 1)
22971 (((deserialization_factor % 2) != 0) &&
22972 (MERCURY_TX_STYLE == 1))
22973 ? tx_mercury_core_clock
22976 assign tx_locked = (deserialization_factor > 2)
22980 assign tx_locked_int = ((STRATIX_TX_STYLE == 1) ||
22981 (CYCLONE_TX_STYLE == 1))
22983 ((STRATIXII_TX_STYLE == 1) ||
22984 (CYCLONEII_TX_STYLE == 1))
22986 : altclklock_locked;
22988 assign tx_fastclk = ((deserialization_factor < 3) ||
22989 (FAMILY_HAS_FLEXIBLE_LVDS == 1))
22991 (use_external_pll == "ON")
22993 (STRATIX_TX_STYLE == 1)
22994 ? stratix_pll_outclock[0] :
22995 (STRATIXII_TX_STYLE == 1)
22996 ? stratixii_sclkout0
22997 : altclklock_clk[0];
22999 assign tx_slowclk = ((use_external_pll == "ON") ||
23000 (FAMILY_HAS_FLEXIBLE_LVDS == 1))
23002 (STRATIX_TX_STYLE == 1)
23003 ? stratix_pll_outclock[2] :
23004 (STRATIXII_TX_STYLE == 1)
23005 ? stratixii_pll_outclock[0]
23006 : altclklock_clk[1];
23008 assign altclklock_inclock = ((STRATIX_TX_STYLE == 1) ||
23009 (STRATIXII_TX_STYLE == 1) ||
23010 (FAMILY_HAS_FLEXIBLE_LVDS == 1))
23014 assign altclklock_clkena = ((FAMILY_HAS_STRATIX_STYLE_PLL == 1) ||
23015 (FAMILY_HAS_STRATIXII_STYLE_PLL == 1))
23019 assign stratix_pll_inclock[1:0] = (FAMILY_HAS_STRATIX_STYLE_PLL == 1)
23020 ? {1'b0, tx_inclock}
23023 assign stratixii_pll_inclock[1:0] = (FAMILY_HAS_STRATIXII_STYLE_PLL == 1)
23024 ? {1'b0, tx_inclock}
23027 assign stratix_pll_enable = (FAMILY_HAS_STRATIX_STYLE_PLL == 1)
23031 assign stratixii_pll_enable = (FAMILY_HAS_STRATIXII_STYLE_PLL == 1)
23035 assign stratix_pll_areset = (FAMILY_HAS_STRATIX_STYLE_PLL == 1)
23039 assign stratixii_pll_areset = (FAMILY_HAS_STRATIXII_STYLE_PLL == 1)
23043 assign stratix_inclock = ((STRATIX_TX_STYLE == 1) &&
23044 (implement_in_les == "OFF"))
23045 ? stratix_pll_outclock[1]
23048 assign stratix_enable = ((STRATIX_TX_STYLE == 1) &&
23049 (implement_in_les == "OFF"))
23053 assign stratixii_inclock = ((STRATIXII_TX_STYLE == 1) &&
23054 (implement_in_les == "OFF"))
23055 ? ((use_external_pll == "ON")
23057 : stratixii_sclkout1)
23060 assign stratixii_enable = ((STRATIXII_TX_STYLE == 1) &&
23061 (implement_in_les == "OFF"))
23062 ? ((use_external_pll == "ON")
23064 : stratixii_enable1)
23067 assign flvds_fastclk = ((FAMILY_HAS_FLEXIBLE_LVDS == 1) &&
23068 (FAMILY_HAS_STRATIX_STYLE_PLL == 1))
23069 ? ((use_external_pll == "ON")
23071 : stratix_pll_outclock[0]) :
23072 ((FAMILY_HAS_FLEXIBLE_LVDS == 1) &&
23073 (FAMILY_HAS_STRATIXII_STYLE_PLL == 1))
23074 ? ((use_external_pll == "ON")
23076 : stratixii_pll_outclock[0])
23079 assign flvds_slowclk = ((FAMILY_HAS_FLEXIBLE_LVDS == 1) &&
23080 (FAMILY_HAS_STRATIX_STYLE_PLL == 1))
23081 ? ((use_external_pll == "ON")
23083 : stratix_pll_outclock[2]) :
23084 ((FAMILY_HAS_FLEXIBLE_LVDS == 1) &&
23085 (FAMILY_HAS_STRATIXII_STYLE_PLL == 1))
23086 ? ((use_external_pll == "ON")
23088 : stratixii_pll_outclock[2])
23091 assign flvds_regclk = (FAMILY_HAS_FLEXIBLE_LVDS == 1)
23095 endmodule // altlvds_tx
23099 //START_MODULE_NAME--------------------------------------------------------------
23101 // Module Name : stratix_tx_outclk
23103 // Description : This module is used to generate the tx_outclock for Stratix
23106 // Limitation : Only available STRATIX family.
23108 // Results expected: Output clock.
23110 //END_MODULE_NAME----------------------------------------------------------------
23112 // BEGINNING OF MODULE
23113 `timescale 1 ps / 1 ps
23115 module stratix_tx_outclk (
23122 // GLOBAL PARAMETER DECLARATION
23123 // No. of bits per channel (required)
23124 parameter deserialization_factor = 4;
23125 parameter bypass_serializer = "FALSE";
23126 parameter use_falling_clock_edge = "FALSE";
23128 // INPUT PORT DECLARATION
23129 // Input data (required)
23130 input [9 : 0] tx_in;
23131 // Input clock (required)
23135 // OUTPUT PORT DECLARATION
23136 // Serialized data signal(required)
23139 // INTERNAL REGISTERS DECLARATION
23140 reg [deserialization_factor -1 : 0] tx_shift_reg;
23141 reg [deserialization_factor -1 : 0] tx_parallel_load_reg;
23147 // INTERNAL TRI DECLARATION
23150 // LOCAL INTEGER DECLARATION
23153 // INITIAL CONSTRUCT BLOCK
23156 begin : INITIALIZATION
23157 tx_parallel_load_reg = {deserialization_factor{1'b0}};
23158 tx_shift_reg = {deserialization_factor{1'b0}};
23159 end // INITIALIZATION
23161 // ALWAYS CONSTRUCT BLOCK
23163 // registering load enable signal
23164 always @ (posedge tx_fastclk)
23165 begin : LOAD_ENABLE_POS
23166 if (tx_fastclk === 1'b1)
23168 enable1_reg1 <= enable1_reg0;
23169 enable1_reg0 <= tx_enable;
23171 end // LOAD_ENABLE_POS
23173 always @ (negedge tx_fastclk)
23174 begin : LOAD_ENABLE_NEG
23175 enable1_reg2 <= enable1_reg1;
23176 end // LOAD_ENABLE_NEG
23179 always @ (posedge tx_fastclk)
23180 begin : POSEDGE_FAST_CLOCK
23181 if (enable1_reg2 == 1'b1)
23182 tx_shift_reg <= tx_parallel_load_reg;
23183 else// Shift data from shift register to tx_out
23185 for (x=deserialization_factor-1; x >0; x=x-1)
23186 tx_shift_reg[x] <= tx_shift_reg [x-1];
23189 tx_parallel_load_reg <= tx_in[deserialization_factor-1 : 0];
23190 end // POSEDGE_FAST_CLOCK
23192 always @ (negedge tx_fastclk)
23193 begin : NEGEDGE_FAST_CLOCK
23194 tx_out_neg <= tx_shift_reg[deserialization_factor-1];
23195 end // NEGEDGE_FAST_CLOCK
23197 // CONTINUOUS ASSIGNMENT
23198 assign tx_out = (bypass_serializer == "TRUE") ? tx_fastclk :
23199 (use_falling_clock_edge == "TRUE") ? tx_out_neg :
23200 tx_shift_reg[deserialization_factor-1];
23202 endmodule // stratix_tx_outclk
23205 //START_MODULE_NAME--------------------------------------------------------------
23207 // Module Name : stratixii_tx_outclk
23209 // Description : This module is used to generate the tx_outclock for StratixII
23212 // Limitation : Only available STRATIX II family.
23214 // Results expected: Output clock.
23216 //END_MODULE_NAME----------------------------------------------------------------
23218 // BEGINNING OF MODULE
23219 `timescale 1 ps / 1 ps
23221 module stratixii_tx_outclk (
23228 // GLOBAL PARAMETER DECLARATION
23229 // No. of bits per channel (required)
23230 parameter deserialization_factor = 4;
23231 parameter bypass_serializer = "FALSE";
23232 parameter use_falling_clock_edge = "FALSE";
23234 // INPUT PORT DECLARATION
23235 // Input data (required)
23236 input [9 : 0] tx_in;
23237 // Input clock (required)
23241 // OUTPUT PORT DECLARATION
23242 // Serialized data signal(required)
23245 // INTERNAL REGISTERS DECLARATION
23246 reg [deserialization_factor -1 : 0] tx_shift_reg;
23247 reg [deserialization_factor -1 : 0] tx_parallel_load_reg;
23252 // INTERNAL TRI DECLARATION
23255 // LOCAL INTEGER DECLARATION
23260 // INITIAL CONSTRUCT BLOCK
23263 begin : INITIALIZATION
23264 tx_parallel_load_reg = {deserialization_factor{1'b0}};
23265 tx_shift_reg = {deserialization_factor{1'b0}};
23269 end // INITIALIZATION
23271 // ALWAYS CONSTRUCT BLOCK
23274 always @ (posedge tx_fastclk)
23275 begin : POSEDGE_FAST_CLOCK
23276 // registering enable1 signal
23277 enable1_reg <= tx_enable;
23279 if (enable1_reg == 1'b1)
23280 tx_shift_reg <= tx_parallel_load_reg;
23281 else// Shift data from shift register to tx_out
23283 for (x=deserialization_factor-1; x >0; x=x-1)
23284 tx_shift_reg[x] <= tx_shift_reg [x-1];
23287 tx_parallel_load_reg <= tx_in[deserialization_factor-1 : 0];
23288 end // POSEDGE_FAST_CLOCK
23290 always @ (negedge tx_fastclk)
23291 begin : NEGEDGE_FAST_CLOCK
23292 tx_out_neg <= tx_shift_reg[deserialization_factor-1];
23293 end // NEGEDGE_FAST_CLOCK
23295 // CONTINUOUS ASSIGNMENT
23296 assign tx_out = (bypass_serializer == "TRUE") ? tx_fastclk :
23297 (use_falling_clock_edge == "TRUE") ? tx_out_neg :
23298 tx_shift_reg[deserialization_factor-1];
23300 endmodule // stratixii_tx_outclk
23304 //START_MODULE_NAME----------------------------------------------------
23306 // Module Name : flexible_lvds_tx
23308 // Description : flexible lvds transmitter
23310 // Limitation : Only available to Cyclone and Cyclone II
23313 // Results expected: Serialized output data.
23315 //END_MODULE_NAME----------------------------------------------------
23317 // BEGINNING OF MODULE
23318 `timescale 1 ps / 1 ps
23320 // MODULE DECLARATION
23321 module flexible_lvds_tx (
23322 tx_in, // input serial data
23323 tx_fastclk, // fast clock from pll
23324 tx_slowclk, // slow clock from pll
23325 tx_regclk, // clock for registering input data
23326 tx_locked, // locked signal from PLL
23327 tx_out // deserialized output data
23330 // GLOBAL PARAMETER DECLARATION
23331 parameter number_of_channels = 1;
23332 parameter deserialization_factor = 4;
23333 parameter registered_input = "ON";
23335 // LOCAL PARAMETER DECLARATION
23336 parameter REGISTER_WIDTH = deserialization_factor*number_of_channels;
23337 parameter DOUBLE_DESER = deserialization_factor*2;
23339 // INPUT PORT DECLARATION
23340 input [REGISTER_WIDTH -1: 0] tx_in;
23346 // OUTPUT PORT DECLARATION
23347 output [number_of_channels -1 :0] tx_out;
23349 // INTERNAL REGISTERS DECLARATION
23350 reg [REGISTER_WIDTH -1 : 0] tx_reg;
23351 reg [(REGISTER_WIDTH*2) -1 : 0] tx_reg2;
23352 reg [REGISTER_WIDTH -1 : 0] tx_shift_reg;
23353 reg [(REGISTER_WIDTH*2) -1 : 0] tx_shift_reg2;
23354 reg [REGISTER_WIDTH -1 :0] h_sync_a;
23355 reg [(REGISTER_WIDTH*2) -1 :0] sync_b_reg;
23356 reg [number_of_channels -1 :0] dataout_h;
23357 reg [number_of_channels -1 :0] dataout_l;
23358 reg [number_of_channels -1 :0] dataout_tmp;
23359 reg [number_of_channels -1 :0] tx_ddio_out;
23361 // INTERNAL WIRE DECLARATION
23362 wire [REGISTER_WIDTH -1 : 0] tx_in_int;
23363 wire [(REGISTER_WIDTH*2) -1 : 0] tx_in_int2;
23366 // LOCAL INTEGER DECLARATION
23374 // INITIAL CONSTRUCT BLOCK
23376 begin : INITIALIZATION
23377 tx_reg = {REGISTER_WIDTH{1'b0}};
23378 tx_reg2 = {(REGISTER_WIDTH*2){1'b0}};
23380 tx_shift_reg = {REGISTER_WIDTH{1'b0}};
23381 tx_shift_reg2 = {(REGISTER_WIDTH*2){1'b0}};
23383 dataout_h = {number_of_channels{1'b0}};
23384 dataout_l = {number_of_channels{1'b0}};
23385 dataout_tmp = {number_of_channels{1'b0}};
23386 tx_ddio_out = {number_of_channels{1'b0}};
23388 h_sync_a = {REGISTER_WIDTH{1'b0}};
23389 sync_b_reg = {(REGISTER_WIDTH*2){1'b0}};
23392 end //INITIALIZATION
23395 // ALWAYS CONSTRUCT BLOCK
23397 // For each data channel, input data are separated into 2 data
23398 // stream which will be transmitted on different edge of input clock.
23399 always @ (posedge tx_fastclk)
23400 begin : DDIO_OUT_POS
23401 if ((deserialization_factor % 2) == 0)
23403 for (i1 = 0; i1 < number_of_channels; i1 = i1 +1)
23405 dataout_h[i1] <= tx_shift_reg[(i1+1)*deserialization_factor-1];
23406 dataout_l[i1] <= tx_shift_reg[(i1+1)*deserialization_factor-2];
23407 dataout_tmp[i1] <= tx_shift_reg[(i1+1)*deserialization_factor-1];
23412 for (i1 = 0; i1 < number_of_channels; i1 = i1 +1)
23414 dataout_h[i1] <= tx_shift_reg2[(i1+1)*DOUBLE_DESER-1];
23415 dataout_l[i1] <= tx_shift_reg2[(i1+1)*DOUBLE_DESER-2];
23416 dataout_tmp[i1] <= tx_shift_reg2[(i1+1)*DOUBLE_DESER-1];
23419 end // DDIO_OUT_POS
23421 always @ (negedge tx_fastclk)
23422 begin : DDIO_OUT_NEG
23423 dataout_tmp <= dataout_l;
23424 end // DDIO_OUT_NEG
23426 // Loading input data to shift register
23427 always @ (posedge tx_fastclk)
23430 // if(tx_locked == 1'b1)
23432 // Implementation for even deserialization factor.
23433 if ((deserialization_factor % 2) == 0)
23435 loadcnt <= (loadcnt + 1) % (deserialization_factor/2);
23438 tx_shift_reg <= tx_in_int;
23441 for (i2= 0; i2 < number_of_channels; i2 = i2+1)
23443 for (x=deserialization_factor-1; x >1; x=x-1)
23444 tx_shift_reg[x + (i2 * deserialization_factor)] <=
23445 tx_shift_reg [x-2 + (i2 * deserialization_factor)];
23449 else // Implementation for odd deserialization factor.
23451 loadcnt <= (loadcnt + 1) % deserialization_factor;
23454 tx_shift_reg2 <= tx_in_int2;
23457 for (i2= 0; i2 < number_of_channels; i2 = i2+1)
23459 for (x=DOUBLE_DESER-1; x >1; x=x-1)
23460 tx_shift_reg2[x + (i2 * DOUBLE_DESER)] <=
23461 tx_shift_reg2 [x-2 + (i2 * DOUBLE_DESER)];
23468 // loading data to synchronization register
23469 always @ (posedge tx_slowclk)
23470 begin : SYNC_REG_POS
23472 end // SYNC_REG_POS
23474 always @ (negedge tx_slowclk)
23475 begin : SYNC_REG_NEG
23477 for (i3= 0; i3 < number_of_channels; i3 = i3+1)
23479 for (x2=0; x2 < deserialization_factor; x2=x2+1)
23481 sync_b_reg[x2 + (((i3 * 2) + 1) * deserialization_factor)] <=
23482 h_sync_a[x2 + (i3 * deserialization_factor)];
23483 sync_b_reg[x2 + (i3 * DOUBLE_DESER)] <=
23484 tx_in[x2 + (i3 * deserialization_factor)];
23487 end // SYNC_REG_NEG
23489 // loading data to input register
23490 always @ (posedge tx_regclk)
23492 if ((deserialization_factor % 2) == 0)
23495 tx_reg2 <= sync_b_reg;
23498 // CONTINOUS ASSIGNMENT
23499 assign tx_in_int = (registered_input == "OFF") ? tx_in : tx_reg;
23500 assign tx_in_int2 = (registered_input == "OFF") ? sync_b_reg : tx_reg2;
23501 assign tx_out = dataout_tmp;
23504 endmodule // flexible_lvds_tx
23508 //START_MODULE_NAME----------------------------------------------------
23510 // Module Name : altcam
23512 // Description : Content-addressable memory (CAM) Megafunction. The
23513 // data contained in a CAM is a set of patterns that can be searched in a
23514 // single-clock cycle. The altcam megafunction allows each stored pattern
23515 // bit to be specified as a binary "1" bit, binary "0" bit, or a don't care bit.
23516 // Comparing a stored pattern bit that is specified as don't care with its
23517 // corresponding input pattern bit will always result in a match.
23519 // Limitation : Input patterns cannot contain don't care bits.
23521 // Results expected: If the input pattern given to the CAM matches one
23522 // of the patterns stored in the CAM, the address of the matching stored
23523 // pattern is generated.
23525 //END_MODULE_NAME----------------------------------------------------
23527 `timescale 1 ps / 1 ps
23530 module altcam (pattern, wrx, wrxused, wrdelete, wraddress, wren,
23531 inclock, inclocken, inaclr, outclock,
23532 outclocken, outaclr, mstart, mnext, maddress, mbits, mfound, mcount,
23535 parameter width = 1;
23536 parameter widthad = 1;
23537 parameter numwords = 1;
23538 parameter lpm_file = "UNUSED";
23539 parameter lpm_filex = "UNUSED";
23540 parameter lpm_hint = "UNUSED";
23541 parameter match_mode = "MULTIPLE";
23542 parameter output_reg = "UNREGISTERED";
23543 parameter output_aclr = "ON";
23544 parameter pattern_reg = "INCLOCK";
23545 parameter pattern_aclr = "ON";
23546 parameter wraddress_aclr = "ON";
23547 parameter wrx_reg = "INCLOCK";
23548 parameter wrx_aclr = "ON";
23549 parameter wrcontrol_aclr = "ON";
23550 parameter use_eab = "ON";
23551 parameter lpm_type = "altcam";
23554 input [width-1 : 0] pattern; // Required port
23555 input [width-1 : 0] wrx;
23558 input [widthad-1 : 0] wraddress;
23560 input inclock; // Required port
23570 output [widthad-1 : 0] maddress;
23571 output [numwords-1 : 0] mbits;
23573 output [widthad-1 : 0] mcount;
23578 tri1 wrxused_pullup;
23579 tri1 inclocken_pullup;
23580 tri1 outclocken_pullup;
23581 tri0 wrdelete_pulldown;
23582 tri0 inaclr_pulldown;
23583 wire [width-1 : 0] pattern_int;
23584 wire [width-1 : 0] wrx_int;
23588 wire rdbusy_delayed;
23591 reg [width-1 : 0] pattern_rgd;
23592 reg [width-1 : 0] wrx_rgd;
23594 reg [widthad-1 : 0] wraddress_rgd;
23597 reg [widthad-1 : 0] maddress_rgd;
23598 reg [widthad-1 : 0] maddress_int;
23599 reg [numwords-1 : 0] mbits_rgd;
23600 reg [numwords-1 : 0] mbits_int;
23603 reg [widthad-1 : 0] mcount_rgd;
23604 reg [widthad-1 : 0] mcount_int;
23609 reg [width-1 : 0] cam_array [numwords-1 : 0];
23610 reg [width-1 : 0] x_array [numwords-1 : 0];
23612 // Read control registers
23613 reg first_read_clock;
23614 reg get_first_match;
23615 reg get_next_match;
23618 reg first_read_in_write;
23620 // Write control registers
23622 reg write_start_rgd;
23624 reg write_incomplete;
23633 reg [8*256:1] cam_initf;
23634 reg [8*256:1] cam_initx;
23635 reg [width-1 : 0] word_0;
23636 reg [width-1 : 0] word_1;
23637 reg [widthad-1 : 0] address_0;
23638 reg [widthad-1 : 0] address_1;
23639 reg [numwords-1 : 0] numwords_0;
23642 integer i, j, k, addr;
23643 integer next_search;
23647 reg [width-1:0] ipattern;
23648 reg [widthad-1:0] iwraddress;
23649 reg [width-1:0] iwrx;
23652 reg [numwords-1 : 0] mbits_tmp;
23654 function read_cam_array;
23655 input [widthad-1 : 0] i;
23656 input [width-1 : 0] j;
23658 reg [width-1 : 0] tmp;
23659 tmp = cam_array[i];
23660 read_cam_array = tmp[j];
23661 end // end READ_CAM
23662 endfunction // end of read_cam_array
23664 task write_cam_array;
23665 input [widthad-1 : 0] i;
23666 input [width-1 : 0] j;
23669 reg [width-1 : 0] tmp;
23670 tmp = cam_array[i];
23672 cam_array[i] = tmp;
23673 end // end of WRITE_CAM
23674 endtask // end of write_cam_array
23676 function read_x_array;
23677 input [widthad-1 : 0] i;
23678 input [width-1 : 0] j;
23680 reg [width-1 : 0] tmp;
23682 read_x_array = tmp[j];
23683 end // end of READ_X
23684 endfunction // end of read_x_array
23686 task write_x_array;
23687 input [widthad-1 : 0] i;
23688 input [width-1 : 0] j;
23691 reg [width-1 : 0] tmp;
23695 end // end of WRITE_X
23696 endtask // end of write_x_array
23698 ALTERA_MF_MEMORY_INITIALIZATION mem ();
23703 // Checking for invalid parameters
23706 $display("Error! Value of width parameter must be greater than 0.");
23712 $display("Error! Value of widthad parameter must be greater than 0.");
23716 if( (match_mode != "SINGLE") && (match_mode != "MULTIPLE") && (match_mode != "FAST_MULTIPLE") )
23718 $display("Error! Illegal value for match_mode parameter. The value must be SINGLE, MULTIPLE (the default), or FAST_MULTIPLE.");
23722 for (i=0; i<width; i=i+1)
23724 for (i=0; i<width; i=i+1)
23726 for (i=0; i<widthad; i=i+1)
23728 address_0[i] = 1'b0;
23729 address_1[i] = 1'b1;
23731 for (i=0; i<numwords; i=i+1)
23732 numwords_0[i] = 1'b0;
23734 mbits_int = numwords_0;
23735 mbits_rgd = numwords_0;
23738 mcount_int = address_0;
23739 mcount_rgd = address_0;
23740 maddress_rgd = address_0;
23741 wraddress_rgd = address_0;
23742 pattern_rgd = word_0;
23745 wrdelete_rgd = 1'b0;
23746 wrxused_rgd = 1'b0;
23747 first_read_clock = 1'b0;
23748 get_first_match = 1'b0;
23751 write_start = 1'b0;
23752 write_start_rgd = 1'b0;
23753 write_start_1 = 1'b0;
23754 mstart_rgd1 = 1'b0;
23755 mstart_rgd2 = 1'b0;
23756 write_incomplete = 1'b0;
23760 write0_done = 1'b0;
23761 write1_done = 1'b0;
23762 writex_done = 1'b0;
23764 restart_read = 1'b0;
23768 // word_1[] and word_0[] have to be initialized before
23769 // using it in the code below.
23771 if (lpm_file == "UNUSED")
23772 // no memory initialization file
23773 // Initialize cam to never match.
23774 for (i=0; i<numwords; i=i+1)
23776 cam_array[i] = word_1;
23777 x_array[i] = word_1;
23779 else if (lpm_filex == "UNUSED")
23781 // only lpm_file is used, lpm_filex is not used
23782 // read in the lpm_file and allow matching all bits
23784 $readmemh(lpm_file, cam_array);
23787 $readmemh(lpm_file, cam_array);
23789 mem.convert_hex2ver(lpm_file, width, cam_initf);
23790 $readmemh(cam_initf, cam_array);
23793 for (i = 0; i < numwords; i=i+1)
23794 x_array[i] = word_0;
23798 // both lpm_file and lpm_filex are used.
23799 // Initialize cam using both files.
23801 $readmemh(lpm_file, cam_array);
23804 $readmemh(lpm_file, cam_array);
23806 mem.convert_hex2ver(lpm_file, width, cam_initf);
23807 $readmemh(cam_initf, cam_array);
23811 $readmemh(lpm_filex, x_array);
23814 $readmemh(lpm_filex, x_array);
23816 mem.convert_hex2ver(lpm_filex, width, cam_initx);
23817 $readmemh(cam_initx, x_array);
23822 if (match_mode != "SINGLE")
23824 maddress_int = address_1;
23828 maddress_int = address_0;
23831 if ((match_mode == "FAST_MULTIPLE") && (mstart !== 1'b0) && (mstart !== 1'b1))
23833 // mstart and mnext are not used.
23834 mstart_used = 1'b0;
23835 get_next_match = 1'b1;
23839 mstart_used = 1'b1;
23840 get_next_match = 1'b0;
23844 always @ (wren_rgd)
23846 if ((wren_rgd == 1'b0) && (write_incomplete == 1'b1))
23847 $display ("Insufficient write cycle time, write maybe invalid! ");
23850 always @ (pattern_int)
23852 if (write_incomplete == 1'b1)
23853 $display( "Insufficient pattern hold time, write maybe invalid! ");
23856 always @ (wraddress_rgd)
23858 if (write_incomplete == 1'b1)
23859 $display( "Insufficient address hold time, write maybe invalid! ");
23862 always @ (wrdelete_rgd)
23864 if ((wrdelete_rgd == 1'b0) && (write_incomplete == 1'b1))
23865 $display( "Insufficient delete cycle time, delete failed! ");
23868 always @ (wrdelete_rgd)
23870 if ((wrdelete_rgd == 1'b1) && (write_incomplete == 1'b1))
23871 $display( "Insufficient write cycle time, write maybe invalid! ");
23874 always @ (wrxused_int)
23876 if ((write_incomplete == 1'b1) && (wrdelete_rgd == 1'b0))
23877 $display( "wrxused reg changed during write! ");
23880 always @ (mstart_rgd1)
23882 if ((write_incomplete == 1'b1) && (mstart_rgd1 == 1'b1))
23883 $display( "Incorrect read attempt during write! ");
23886 always @ (pattern_int)
23888 if (rdbusy_delayed == 1'b1)
23889 $display( "Insufficient read time, read failed! ");
23890 else if ((rdbusy_delayed == 1'b0) && (mnext == 1'b1))
23891 $display( "Illegal pattern change during read, read failed! ");
23896 if (mstart_used == 1'b0)
23898 // Implies fast multiple mode with mstart and mnext
23899 get_next_match = 1'b0;
23901 mstart_used = 1'b1;
23904 // Start: Async clear inclock registers
23905 always @ (posedge inaclr_pulldown)
23907 if (inaclr_pulldown == 1'b1)
23909 if (mstart_used == 1'b1)
23913 first_read_clock <= 1'b0;
23914 get_first_match <= 1'b0;
23915 if (pattern_aclr == "ON")
23917 pattern_rgd <= word_0;
23919 if (wrx_aclr == "ON")
23922 wrxused_rgd <= 1'b0;
23924 if (wraddress_aclr == "ON")
23926 wraddress_rgd <= word_0;
23928 if (wrcontrol_aclr == "ON")
23931 write0_done <= 1'b0;
23932 write1_done <= 1'b0;
23933 writex_done <= 1'b0;
23935 if (pattern_aclr == "ON")
23937 mbits_int <= numwords_0;
23938 mcount_int <= word_0;
23939 mfound_int <= 1'b0;
23940 if (match_mode == "SINGLE")
23942 maddress_int <= address_0;
23946 maddress_int <= address_1;
23949 if ((output_reg == "INCLOCK") && (output_aclr == "OFF"))
23951 maddress_rgd <= address_0;
23952 mbits_rgd <= numwords_0;
23953 mfound_rgd <= 1'b0;
23954 mcount_rgd <= address_0;
23958 // End: Async clear inclock registers
23960 /////////////////////////////////////////
23961 // Evaluate ALTCAM reading and writing
23962 /////////////////////////////////////////
23963 // Start: Read and Write to CAM
23964 always @ (inclock) // read_write
23966 ipattern = pattern;
23968 iwraddress = wraddress;
23970 if (wrx === {width{1'bz}})
23972 iwrxused = 1'b0; // must be unconnected
23976 iwrxused = wrxused_pullup;
23979 if (inaclr_pulldown == 1'b1)
23981 if (mstart_used == 1'b1)
23985 first_read_clock <= 1'b0;
23986 get_first_match <= 1'b0;
23987 if (pattern_aclr == "ON")
23991 if (wrx_aclr == "ON")
23996 if (wraddress_aclr == "ON")
23998 iwraddress = word_0;
24000 if (wrcontrol_aclr == "ON")
24004 if (pattern_aclr == "ON")
24006 mbits_int <= numwords_0;
24007 mcount_int <= word_0;
24008 mfound_int <= 1'b0;
24009 if (match_mode == "SINGLE")
24011 maddress_int <= address_0;
24015 maddress_int <= address_1;
24020 if (inclocken_pullup == 1'b1)
24022 if (inclock == 1'b1)
24023 begin // positive inclock edge
24024 pattern_rgd <= ipattern;
24026 wrxused_rgd <= iwrxused;
24027 wraddress_rgd <= iwraddress;
24030 write_start_rgd <= write_start;
24031 write_incomplete <= wrbusy_int;
24032 mstart_rgd1 <= mstart;
24033 mstart_rgd2 <= mstart_rgd1;
24034 wrdelete_rgd <= wrdelete_pulldown;
24038 write0_done <= 1'b0;
24039 write1_done <= 1'b0;
24040 writex_done <= 1'b0;
24041 ////////////////////
24042 // CAM READ MODES //
24043 ////////////////////
24044 // If pattern changed || mstart asserted again) begin restart
24046 if (((match_mode == "FAST_MULTIPLE") && (mstart_used == 1'b0) && (reset_read==1'b1)) ||
24047 ((mstart == 1'b1) && (mstart_rgd1 == 1'b0)) ||
24048 ((ipattern != pattern_rgd) && (reset_read==1'b0)))
24050 restart_read = 1'b1;
24052 get_first_match <= 1'b0;
24056 restart_read = 1'b0;
24058 /////////////////////////
24059 // FAST MULTIPLE: READ //
24060 /////////////////////////
24061 if (match_mode == "FAST_MULTIPLE")
24063 if ((get_first_match == 1'b1) && (restart_read == 1'b0))
24065 if (get_next_match == 1'b1)
24066 begin // start of next read cycle
24067 index = next_search;
24068 begin: MADDR_FM0 for (i=index; i<numwords; i=i+1)
24069 begin: MWORD_FM0 for (j=0; j<width; j=j+1)
24070 if (((read_x_array(i,j) == 1'b0) && (read_cam_array(i,j) == ipattern[j])) ||
24071 ((read_x_array(i,j) == 1'b1) && (read_cam_array(i,j) == 1'b0)))
24086 if (index == next_search)
24087 begin // no more matches
24088 mfound_int <= 1'b0;
24089 maddress_int <= address_1;
24093 maddress_int <= (next_search-1);
24098 begin // start of new read cycle
24100 mbits_tmp = numwords_0;
24101 begin: MADDR_FM1 for (i=0; i<numwords; i=i+1)
24102 begin: MWORD_FM1 for (j=0; j<width; j=j+1)
24103 if (((read_x_array(i,j) == 1'b0) && (read_cam_array(i,j) == ipattern[j])) || // match pattern bit or
24104 ((read_x_array(i,j) == 1'b1) && (read_cam_array(i,j) == 1'b0))) // don't care bit
24106 if (j == width-1) // last bit of word
24108 if ((count == 0) && (reset_read == 1'b0) && (restart_read == 1'b1))
24110 mfound_int <= 1'b1;
24112 get_first_match <= 1'b1;
24115 mbits_tmp[i] = 1'b1; // set the match word
24116 count = count + 1; // count the matched word
24119 else // Never match bit
24125 mcount_int <= count;
24126 mbits_int <= mbits_tmp;
24127 if ((count == 0) || (reset_read == 1'b1))
24128 begin // no matches
24129 mfound_int <= 1'b0;
24130 maddress_int <= address_1;
24132 end // end of initial read cycle
24133 end // end of FAST MULTIPLE
24135 ////////////////////
24136 // MULTIPLE: READ //
24137 ////////////////////
24138 if (match_mode == "MULTIPLE")
24140 if ((get_first_match == 1'b1) && (restart_read == 1'b0))
24142 if (get_next_match == 1'b1)
24143 begin // start of next read cycle
24144 index = next_search;
24145 begin: MADDR_MM0 for (i=index; i<numwords; i=i+1)
24146 begin: MWORD_MM0 for (j=0; j<width; j=j+1)
24147 if (((read_x_array(i,j) == 1'b0) && (read_cam_array(i,j) == ipattern[j])) ||
24148 ((read_x_array(i,j) == 1'b1) && (read_cam_array(i,j) == 1'b0)))
24163 if (index == next_search)
24165 mfound_int <= 1'b0;
24166 maddress_int <= address_1;
24170 maddress_int <= (next_search-1);
24175 begin // start of 1st match
24177 if (reset_read==1'b0)
24178 begin // Not in reset state
24179 if (first_read_clock == 1'b0)
24181 // 1st cycle: match with even && write to even
24182 first_read_clock <= 1'b1;
24183 maddress_int <= address_1;
24184 mfound_int <= 1'b0;
24185 mbits_tmp = mbits_int;
24186 begin: MADDR_MM1 for (i=0; i<numwords; i=i+1)
24189 if (mbits_int[i] == 1'b1)
24193 begin: MWORD_MM1 for (j=0; j<width; j=j+1)
24194 if (((read_x_array(i,j) == 1'b0) && (read_cam_array(i,j) == ipattern[j])) ||
24195 ((read_x_array(i,j) == 1'b1) && (read_cam_array(i,j) == 1'b0)))
24199 mbits_tmp[i+1] = 1'b1;
24205 mbits_tmp[i+1] = 1'b0;
24213 begin // 2nd read cycle
24214 // 2nd cycle: do match
24215 first_read_clock <= 1'b0;
24216 mbits_tmp = numwords_0;
24217 begin: MADDR_MM2 for (i=0; i<numwords; i=i+1)
24218 begin: MWORD_MM2 for (j=0; j<width; j=j+1)
24219 if (((read_x_array(i,j) == 1'b0) && (read_cam_array(i,j) == ipattern[j])) ||
24220 ((read_x_array(i,j) == 1'b1) && (read_cam_array(i,j) == 1'b0)))
24228 mbits_tmp[i] = 1'b1;
24239 begin // no matches
24240 maddress_int <= address_1;
24241 mfound_int <= 1'b0;
24245 get_first_match <= 1'b1;
24246 mfound_int <= 1'b1;
24247 maddress_int <= (next_search-1);
24252 begin // In reset state
24253 // Match with even but write to odd
24254 maddress_int <= address_1;
24255 mfound_int <= 1'b0;
24256 mbits_tmp = numwords_0;
24257 begin: MADDR_MM3 for (i=0; i<numwords; i=i+1)
24260 begin: MWORD_MM3 for (j=0; j<width; j=j+1)
24261 if (((read_x_array(i,j) == 1'b0) && (read_cam_array(i,j) == ipattern[j])) ||
24262 ((read_x_array(i,j) == 1'b1) && (read_cam_array(i,j) == 1'b0)))
24266 mbits_tmp[i+1] = 1'b1;
24277 end // end of reset state
24278 mcount_int <= count;
24279 mbits_int <= mbits_tmp;
24280 end // end of initial read cycle
24281 end // end of MULTIPLE
24286 if (match_mode == "SINGLE")
24288 mbits_tmp = numwords_0;
24291 begin: MADDR_SM0 for (i=0; i<numwords; i=i+1)
24292 begin: MWORD_SM0 for (j=0; j<width; j=j+1)
24293 if (((read_x_array(i,j) == 1'b0) && (read_cam_array(i,j) == ipattern[j])) ||
24294 ((read_x_array(i,j) == 1'b1) && (read_cam_array(i,j) == 1'b0)))
24298 mbits_tmp[i] = 1'b1;
24311 mcount_int <= count;
24312 mbits_int <= mbits_tmp;
24315 maddress_int <= address_0;
24316 mfound_int <= 1'b0;
24320 mfound_int <= 1'b1;
24321 maddress_int <= index;
24323 end // end of SINGLE
24326 begin // if wren == 1'b1
24327 //////////////////////
24328 // READ AFTER WRITE //
24329 //////////////////////
24330 // Writing to CAM so reset read cycle.
24331 get_first_match <= 1'b0;
24332 first_read_clock <= 1'b0;
24333 restart_read = 1'b0;
24334 if (mstart_used == 1'b1)
24338 /////////////////////////////////////
24339 // FAST MULTIPLE: READ AFTER WRITE //
24340 /////////////////////////////////////
24341 if (match_mode == "FAST_MULTIPLE")
24343 mfound_int <= 1'b0;
24344 maddress_int <= address_1;
24346 mbits_tmp = numwords_0;
24347 if ((writex == 1'b1) && (iwrxused == 1'b1))
24349 begin: WADDR_FM0 for (i=0; i<numwords; i=i+1)
24350 begin: WWORD_FM0 for (j=0; j<width; j=j+1)
24351 if (((read_x_array(i,j) == 1'b0) && (read_cam_array(i,j) == (ipattern[j] ^ iwrx[j]))) ||
24352 ((read_x_array(i,j) == 1'b1) && (read_cam_array(i,j) == 1'b0)))
24356 mbits_tmp[i] = 1'b1;
24369 begin: WADDR_FM1 for (i=0; i<numwords; i=i+1)
24370 begin: WWORD_FM1 for (j=0; j<width; j=j+1)
24371 if (((read_x_array(i,j) == 1'b0) && (read_cam_array(i,j) == ipattern[j])) ||
24372 ((read_x_array(i,j) == 1'b1) && (read_cam_array(i,j) == 1'b0)))
24376 mbits_tmp[i] = 1'b1;
24387 mcount_int <= count;
24388 mbits_int <= mbits_tmp;
24389 end // end of FAST MULTIPLE
24391 ////////////////////////////////
24392 // MULTIPLE: READ AFTER WRITE //
24393 ////////////////////////////////
24394 if ((match_mode == "MULTIPLE"))
24396 mfound_int <= 1'b0;
24397 maddress_int <= address_1;
24398 mbits_tmp = numwords_0;
24399 if ((writex == 1'b1) && (iwrxused == 1'b1))
24405 if (first_read_in_write == 1'b0)
24407 // Read even addresses but they appear on the odd locations
24410 begin: WADDR_MM0 for (i=0; i<numwords; i=i+1)
24413 if (mbits_int[i] == 1'b1)
24414 begin // counting previous even address matches
24417 begin: WWORD_MM0 for (j=0; j<width; j=j+1)
24418 if (((read_x_array(i,j) == 1'b0) && (read_cam_array(i,j) == ipattern[j])) ||
24419 ((read_x_array(i,j) == 1'b1) && (read_cam_array(i,j) == 1'b0)))
24423 mbits_tmp[i+1] = 1'b1;
24437 // Read odd addresses.
24439 begin: WADDR_MM1 for (i=numwords-1; i>=0; i=i-1)
24442 mbits_tmp[i-1] = mbits_tmp[i];
24446 begin: WWORD_MM1 for (j=0; j<width; j=j+1)
24447 if (((read_x_array(i,j) == 1'b0) && (read_cam_array(i,j) == ipattern[j])) ||
24448 ((read_x_array(i,j) == 1'b1) && (read_cam_array(i,j) == 1'b0)))
24452 mbits_tmp[i] = 1'b1;
24464 mcount_int <= count;
24465 mbits_int <= mbits_tmp;
24467 end // end of MULTIPLE
24469 //////////////////////////////
24470 // SINGLE: READ AFTER WRITE //
24471 //////////////////////////////
24472 if (match_mode == "SINGLE")
24474 mbits_tmp = numwords_0;
24477 if ((writex == 1'b1) && (iwrxused == 1'b1))
24479 begin: WADDR_SM0 for (i=0; i<numwords; i=i+1)
24480 begin: WWORD_SM0 for (j=0; j<width; j=j+1)
24481 if (((read_x_array(i,j) == 1'b0) && (read_cam_array(i,j) == (ipattern[j] ^ iwrx[j]))) ||
24482 ((read_x_array(i,j) == 1'b1) && (read_cam_array(i,j) == 1'b0)))
24486 mbits_tmp[i] = 1'b1;
24502 begin: WADDR_SM1 for (i=0; i<numwords; i=i+1)
24503 begin: WWORD_SM1 for (j=0; j<width; j=j+1)
24504 if (((read_x_array(i,j) == 1'b0) && (read_cam_array(i,j) == ipattern[j])) ||
24505 ((read_x_array(i,j) == 1'b1) && (read_cam_array(i,j) == 1'b0)))
24509 mbits_tmp[i] = 1'b1;
24523 mcount_int <= count;
24524 mbits_int <= mbits_tmp;
24527 mfound_int <= 1'b0;
24528 maddress_int <= address_0;
24532 mfound_int <= 1'b1;
24533 maddress_int <= index;
24535 end // end of SINGLE
24536 end // end of wren == 1'b1
24537 end // end of inclock == 1'b1
24539 begin // if (inclock negedge
24540 // We write to the CAM on the low cycle of inclock
24541 // when wren_rgd==1'b1.
24542 if (pattern_reg == "UNREGISTERED") ipattern = pattern;
24543 else ipattern = pattern_rgd;
24544 if ((wren_rgd==1'b1) && (inclock==1'b0))
24546 addr = wraddress_rgd;
24547 /////////////////////
24548 // CAM WRITE MODES //
24549 /////////////////////
24550 if (wrdelete_rgd == 1'b0)
24552 if ((wrxused_int == 1'b1) && (wrx !== {width{1'bz}}))
24554 ///////////////////
24555 // 3 CYCLE WRITE //
24556 ///////////////////
24560 if (write0 == 1'b1)
24562 for (i =0; i<width; i=i+1 )
24564 if (ipattern[i] == 1'b0)
24567 if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b0))
24569 write_cam_array(addr,i,1'b0);
24570 write_x_array(addr,i,1'b0);
24573 else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b0))
24575 write_cam_array(addr,i,1'b0);
24576 write_x_array(addr,i,1'b1);
24579 else if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b1))
24581 write_cam_array(addr,i,1'b0);
24582 write_x_array(addr,i,1'b1);
24585 else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b1))
24587 write_cam_array(addr,i,1'b0);
24588 write_x_array(addr,i,1'b0);
24590 end else if (ipattern[i] == 1'b1)
24593 if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b0))
24595 write_cam_array(addr,i,1'b0);
24596 write_x_array(addr,i,1'b1);
24599 else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b0))
24601 write_cam_array(addr,i,1'b1);
24602 write_x_array(addr,i,1'b0);
24605 else if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b1))
24607 write_cam_array(addr,i,1'b0);
24608 write_x_array(addr,i,1'b1);
24611 else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b1))
24613 write_cam_array(addr,i,1'b1);
24614 write_x_array(addr,i,1'b0);
24618 write0_done <= 1'b1;
24619 write1_done <= 1'b0;
24620 writex_done <= 1'b0;
24625 if (write1 == 1'b1)
24627 for (i =0; i<width; i=i+1)
24629 if (ipattern[i] == 1'b0)
24632 if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b0))
24634 write_cam_array(addr,i,1'b0);
24635 write_x_array(addr,i,1'b0);
24638 else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b0))
24640 write_cam_array(addr,i,1'b1);
24641 write_x_array(addr,i,1'b1);
24644 else if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b1))
24646 write_cam_array(addr,i,1'b0);
24647 write_x_array(addr,i,1'b0);
24650 else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b1))
24652 write_cam_array(addr,i,1'b1);
24653 write_x_array(addr,i,1'b1);
24656 else if (ipattern[i] == 1'b1)
24659 if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b0))
24661 write_cam_array(addr,i,1'b1);
24662 write_x_array(addr,i,1'b1);
24665 else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b0))
24667 write_cam_array(addr,i,1'b1);
24668 write_x_array(addr,i,1'b0);
24671 else if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b1))
24673 write_cam_array(addr,i,1'b1);
24674 write_x_array(addr,i,1'b0);
24677 else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b1))
24679 write_cam_array(addr,i,1'b1);
24680 write_x_array(addr,i,1'b1);
24684 write0_done <= 1'b0;
24685 write1_done <= 1'b1;
24686 writex_done <= 1'b0;
24691 if (writex == 1'b1)
24693 for (i =0; i<width; i=i+1)
24695 if ((ipattern[i] ^ wrx_int[i]) == 1'b0)
24698 if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b0))
24700 write_cam_array(addr,i,1'b0);
24701 write_x_array(addr,i,1'b0);
24704 else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b0))
24706 write_cam_array(addr,i,1'b0);
24707 write_x_array(addr,i,1'b1);
24710 else if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b1))
24712 write_cam_array(addr,i,1'b0);
24713 write_x_array(addr,i,1'b1);
24716 else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b1))
24718 write_cam_array(addr,i,1'b0);
24719 write_x_array(addr,i,1'b0);
24722 else if ((ipattern[i] ^ wrx_int[i]) == 1'b1)
24725 if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b0))
24727 write_cam_array(addr,i,1'b0);
24728 write_x_array(addr,i,1'b1);
24731 else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b0))
24733 write_cam_array(addr,i,1'b1);
24734 write_x_array(addr,i,1'b0);
24737 else if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b1))
24739 write_cam_array(addr,i,1'b0);
24740 write_x_array(addr,i,1'b1);
24743 else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b1))
24745 write_cam_array(addr,i,1'b1);
24746 write_x_array(addr,i,1'b0);
24750 writex_done <= 1'b1;
24751 write0_done <= 1'b0;
24752 write1_done <= 1'b0;
24754 if (wrbusy_int == 1'b1)
24756 write_start_1 <= 1'b1;
24757 write_start <= write_start_1;
24761 write_start_1 <= 1'b0;
24762 write_start <= 1'b0;
24766 begin // 2 Cycle write
24767 ///////////////////
24768 // 2 CYCLE WRITE //
24769 ///////////////////
24773 if (write0 == 1'b1)
24775 for (i =0; i<width; i=i+1)
24777 if (ipattern[i] == 1'b0)
24780 if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b0))
24782 write_cam_array(addr,i,1'b0);
24783 write_x_array(addr,i,1'b0);
24786 else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b0))
24788 write_cam_array(addr,i,1'b0);
24789 write_x_array(addr,i,1'b1);
24792 else if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b1))
24794 write_cam_array(addr,i,1'b0);
24795 write_x_array(addr,i,1'b1);
24798 else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b1))
24800 write_cam_array(addr,i,1'b0);
24801 write_x_array(addr,i,1'b0);
24804 else if (ipattern[i] == 1'b1)
24807 if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b0))
24809 write_cam_array(addr,i,1'b0);
24810 write_x_array(addr,i,1'b1);
24813 else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b0))
24815 write_cam_array(addr,i,1'b1);
24816 write_x_array(addr,i,1'b0);
24819 else if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b1))
24821 write_cam_array(addr,i,1'b0);
24822 write_x_array(addr,i,1'b1);
24825 else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b1))
24827 write_cam_array(addr,i,1'b1);
24828 write_x_array(addr,i,1'b0);
24832 write0_done <= 1'b1;
24833 write1_done <= 1'b0;
24834 writex_done <= 1'b0;
24839 if (write1 == 1'b1)
24841 for (i =0; i<width; i=i+1)
24843 if (ipattern[i] == 1'b0)
24846 if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b0))
24848 write_cam_array(addr,i,1'b0);
24849 write_x_array(addr,i,1'b0);
24852 else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b0))
24854 write_cam_array(addr,i,1'b1);
24855 write_x_array(addr,i,1'b1);
24858 else if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b1))
24860 write_cam_array(addr,i,1'b0);
24861 write_x_array(addr,i,1'b0);
24864 else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b1))
24866 write_cam_array(addr,i,1'b1);
24867 write_x_array(addr,i,1'b1);
24870 else if (ipattern[i] == 1'b1)
24873 if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b0))
24875 write_cam_array(addr,i,1'b1);
24876 write_x_array(addr,i,1'b1);
24879 else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b0))
24881 write_cam_array(addr,i,1'b1);
24882 write_x_array(addr,i,1'b0);
24885 else if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b1))
24887 write_cam_array(addr,i,1'b1);
24888 write_x_array(addr,i,1'b0);
24891 else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b1))
24893 write_cam_array(addr,i,1'b1);
24894 write_x_array(addr,i,1'b1);
24898 write0_done <= 1'b0;
24899 write1_done <= 1'b1;
24900 writex_done <= 1'b0;
24903 if (wrbusy_int == 1'b1)
24905 write_start <= 1'b1;
24909 write_start <= 1'b0;
24914 begin // if (wrdelete == 1'b1) begin
24915 ////////////////////
24916 // 2 CYCLE DELETE //
24917 ////////////////////
24918 // Delete is a 2-cycle write
24922 if (write0 == 1'b1)
24924 for (i =0; i<width; i=i+1)
24926 write_cam_array(addr,i,1'b1);
24928 write0_done <= 1'b1;
24929 write1_done <= 1'b0;
24930 writex_done <= 1'b0;
24935 if (write1 == 1'b1)
24937 for (i =0; i<width; i=i+1)
24939 write_x_array(addr,i,1'b1);
24941 write1_done <= 1'b1;
24942 write0_done <= 1'b0;
24943 writex_done <= 1'b0;
24945 if (wrbusy_int == 1'b1)
24947 write_start <= 1'b1;
24951 write_start <= 1'b0;
24955 //////////////////////////////////////
24956 // FAST MULTIPLE: READ DURING WRITE //
24957 //////////////////////////////////////
24958 // Now we need to update mbits, mcount during the write.
24959 if (match_mode == "FAST_MULTIPLE")
24961 mfound_int <= 1'b0;
24962 maddress_int <= address_1;
24964 mbits_tmp = numwords_0;
24965 if ((writex == 1'b1) && (wrxused_int == 1'b1))
24967 begin: WADDR_FM2 for (i=0; i<numwords; i=i+1)
24968 begin: WWORD_FM2 for (j=0; j<width; j=j+1)
24969 if (((read_x_array(i,j) == 1'b0) && (read_cam_array(i,j) == (ipattern[j] ^ wrx_int[j]))) ||
24970 ((read_x_array(i,j) == 1'b1) && (read_cam_array(i,j) == 1'b0)))
24974 if ((count == 0) && (mstart_used == 1'b0))
24976 mfound_int <= 1'b1;
24979 mbits_tmp[i] = 1'b1;
24992 begin: WADDR_FM3 for (i=0; i<numwords; i=i+1)
24993 begin: WWORD_FM3 for (j=0; j<width; j=j+1)
24994 if (((read_x_array(i,j) == 1'b0) && (read_cam_array(i,j) == ipattern[j])) ||
24995 ((read_x_array(i,j) == 1'b1) && (read_cam_array(i,j) == 1'b0)))
24999 if ((count == 0) && (mstart_used == 1'b0))
25001 mfound_int <= 1'b1;
25004 mbits_tmp[i] = 1'b1;
25015 mcount_int <= count;
25016 mbits_int <= mbits_tmp;
25017 end // end of FAST MULTIPLE
25019 /////////////////////////////////
25020 // MULTIPLE: READ DURING WRITE //
25021 /////////////////////////////////
25022 if ((match_mode == "MULTIPLE"))
25024 mfound_int <= 1'b0;
25025 maddress_int <= address_1;
25026 mbits_tmp = numwords_0;
25027 if ((writex == 1'b1) && (iwrxused == 1'b1))
25030 first_read_in_write <= 1'b0;
25034 if (first_read_in_write == 1'b0)
25036 first_read_in_write <= 1'b1;
25037 // Read even addresses but they appear on the odd locations
25040 begin: WADDR_MM2 for (i=0; i<numwords; i=i+1)
25043 if (mbits_int[i] == 1'b1)
25044 begin // counting previous even address matches
25048 begin: WWORD_MM2 for (j=0; j<width; j=j+1)
25049 if (((read_x_array(i,j) == 1'b0) && (read_cam_array(i,j) == ipattern[j])) ||
25050 ((read_x_array(i,j) == 1'b1) && (read_cam_array(i,j) == 1'b0)))
25054 mbits_tmp[i+1] = 1'b1;
25068 first_read_in_write <= 1'b0;
25069 // Read odd addresses.
25071 begin: WADDR_MM3 for (i=numwords-1; i>=0; i=i-1)
25074 mbits_tmp[i-1] = mbits_tmp[i];
25078 begin: WWORD_MM3 for (j=0; j<width; j=j+1)
25079 if (((read_x_array(i,j) == 1'b0) && (read_cam_array(i,j) == ipattern[j])) ||
25080 ((read_x_array(i,j) == 1'b1) && (read_cam_array(i,j) == 1'b0)))
25084 mbits_tmp[i] = 1'b1;
25096 mcount_int <= count;
25097 mbits_int <= mbits_tmp;
25099 end // end of MULTIPLE
25101 ///////////////////////////////
25102 // SINGLE: READ DURING WRITE //
25103 ///////////////////////////////
25104 if (match_mode == "SINGLE")
25106 mbits_tmp = numwords_0;
25109 if ((writex == 1'b1) && (wrxused_int == 1'b1))
25111 begin: WADDR_SM2 for (i=0; i<numwords; i=i+1)
25112 begin: WWORD_SM2 for (j=0; j<width; j=j+1)
25113 if (((read_x_array(i,j) == 1'b0) && (read_cam_array(i,j) == (ipattern[j] ^ wrx_int[j]))) ||
25114 ((read_x_array(i,j) == 1'b1) && (read_cam_array(i,j) == 1'b0)))
25118 mbits_tmp[i] = 1'b1;
25134 begin: WADDR_SM3 for (i=0; i<numwords; i=i+1)
25135 begin: WWORD_SM3 for (j=0; j<width; j=j+1)
25136 if (((read_x_array(i,j) == 1'b0) && (read_cam_array(i,j) == ipattern[j])) ||
25137 ((read_x_array(i,j) == 1'b1) && (read_cam_array(i,j) == 1'b0)))
25141 mbits_tmp[i] = 1'b1;
25155 mcount_int <= count;
25156 mbits_int <= mbits_tmp;
25159 mfound_int <= 1'b0;
25160 maddress_int <= address_0;
25164 mfound_int <= 1'b1;
25165 maddress_int <= index;
25167 end // end of SINGLE
25170 begin // End of Write
25171 if (write_start == 1'b1)
25173 // this should be a second write cycle but due to write violation,
25174 // we have to reset write_start
25175 write_start <= 1'b0;
25177 end // End of Write
25178 end // end of inclock edges
25179 end // end of inclock event
25181 // End: Read and Write to CAM
25183 // Start: Change in pattern
25186 // Only updating mbits, mcount, mfound && maddress if
25187 // the pattern input in unregistered, wren_rgd==1'b0 && the pattern
25188 // pattern changes.
25189 if (pattern_reg=="UNREGISTERED")
25191 if (wren_rgd==1'b0)
25193 ////////////////////////////////////////
25194 // FAST MULTIPLE: READ ON NEW PATTERN //
25195 ////////////////////////////////////////
25196 if (match_mode == "FAST_MULTIPLE")
25199 mbits_tmp = numwords_0;
25200 begin: MADDR_FM2 for (k=0; k<numwords; k=k+1)
25201 begin: MWORD_FM2 for (j=0; j<width; j=j+1)
25202 if (((read_x_array(k,j) == 1'b0) && (read_cam_array(k,j) == pattern[j])) ||
25203 ((read_x_array(k,j) == 1'b1) && (read_cam_array(k,j) == 1'b0)))
25207 if ((count == 0) && (reset_read == 1'b0))
25209 mfound_int <= 1'b1;
25212 mbits_tmp[k] = 1'b1;
25222 mcount_int <= count;
25223 mbits_int <= mbits_tmp;
25224 if ((count == 0) || (reset_read == 1'b1))
25226 mfound_int <= 1'b0;
25227 maddress_int <= address_1;
25229 end // end of FAST MULTIPLE
25231 ///////////////////////////////////
25232 // MULTIPLE: READ ON NEW PATTERN //
25233 ///////////////////////////////////
25234 if (match_mode == "MULTIPLE")
25237 mbits_tmp = mbits_int;
25238 if (reset_read == 1'b1)
25240 begin: MADDR_MM4 for (k=0; k<numwords; k=k+1)
25243 begin: MWORD_MM4 for (j=0; j<width; j=j+1)
25244 if ((((read_x_array(k,j) == 1'b0) && (read_cam_array(k,j) == pattern[j])) ||
25245 ((read_x_array(k,j) == 1'b1) && (read_cam_array(k,j) == 1'b0))))
25249 mbits_tmp[k+1] = 1'b1;
25255 mbits_tmp[k+1] = 1'b0;
25264 // Match odd addresses && write to odd
25265 begin: MADDR_MM5 for (k=0; k<numwords; k=k+1)
25268 begin: MWORD_MM5 for (j=0; j<width; j=j+1)
25269 if ((((read_x_array(k,j) == 1'b0) && (read_cam_array(k,j) == pattern[j])) ||
25270 ((read_x_array(k,j) == 1'b1) && (read_cam_array(k,j) == 1'b0))))
25274 mbits_tmp[k] = 1'b1;
25284 mbits_tmp[k] = 1'b0;
25291 if (mbits_tmp[k] == 1'b1)
25303 mfound_int <= 1'b1;
25307 mfound_int <= 1'b0;
25308 maddress_int <= word_1;
25311 mcount_int <= count;
25312 mbits_int <= mbits_tmp;
25315 /////////////////////////////////
25316 // SINGLE: READ ON NEW PATTERN //
25317 /////////////////////////////////
25318 if (match_mode == "SINGLE")
25320 mbits_tmp = numwords_0;
25323 begin: MADDR_SM1 for (k=0; k<numwords; k=k+1)
25324 begin: MWORD_SM1 for (j=0; j<width; j=j+1)
25325 if ((((read_x_array(k,j) == 1'b0) && (read_cam_array(k,j) == pattern[j])) ||
25326 ((read_x_array(k,j) == 1'b1) && (read_cam_array(k,j) == 1'b0))))
25330 mbits_tmp[k] = 1'b1;
25343 mcount_int <= count;
25344 mbits_int <= mbits_tmp;
25347 maddress_int <= address_0;
25348 mfound_int <= 1'b0;
25352 mfound_int <= 1'b1;
25353 maddress_int <= index;
25355 end // end of SINGLE
25356 end // end of read on pattern change
25358 begin // write on pattern change
25359 // We write to the CAM on the low cycle of inclock
25360 // when wren_rgd==1'b1 and pattern changes.
25361 if ((wren_rgd==1'b1) && (inclock==1'b0))
25363 addr = wraddress_rgd;
25364 /////////////////////
25365 // CAM WRITE MODES //
25366 /////////////////////
25367 if (wrdelete_rgd == 1'b0)
25369 if ((wrxused_int == 1'b1) && (wrx !== {width{1'bz}}))
25371 ///////////////////
25372 // 3 CYCLE WRITE //
25373 ///////////////////
25377 if (write0_done == 1'b1)
25379 for (k =0; k<width; k=k+1 )
25381 if (pattern[k] == 1'b0)
25384 if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b0))
25386 write_cam_array(addr,k,1'b0);
25387 write_x_array(addr,k,1'b0);
25390 else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b0))
25392 write_cam_array(addr,k,1'b0);
25393 write_x_array(addr,k,1'b1);
25396 else if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b1))
25398 write_cam_array(addr,k,1'b0);
25399 write_x_array(addr,k,1'b1);
25402 else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b1))
25404 write_cam_array(addr,k,1'b0);
25405 write_x_array(addr,k,1'b0);
25408 else if (pattern[k] == 1'b1)
25411 if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b0))
25413 write_cam_array(addr,k,1'b0);
25414 write_x_array(addr,k,1'b1);
25417 else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b0))
25419 write_cam_array(addr,k,1'b1);
25420 write_x_array(addr,k,1'b0);
25423 else if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b1))
25425 write_cam_array(addr,k,1'b0);
25426 write_x_array(addr,k,1'b1);
25429 else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b1))
25431 write_cam_array(addr,k,1'b1);
25432 write_x_array(addr,k,1'b0);
25440 if (write1_done == 1'b1)
25442 for (k =0; k<width; k=k+1)
25444 if (pattern[k] == 1'b0)
25447 if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b0))
25449 write_cam_array(addr,k,1'b0);
25450 write_x_array(addr,k,1'b0);
25453 else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b0))
25455 write_cam_array(addr,k,1'b1);
25456 write_x_array(addr,k,1'b1);
25459 else if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b1))
25461 write_cam_array(addr,k,1'b0);
25462 write_x_array(addr,k,1'b0);
25465 else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b1))
25467 write_cam_array(addr,k,1'b1);
25468 write_x_array(addr,k,1'b1);
25471 else if (pattern[k] == 1'b1)
25474 if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b0))
25476 write_cam_array(addr,k,1'b1);
25477 write_x_array(addr,k,1'b1);
25480 else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b0))
25482 write_cam_array(addr,k,1'b1);
25483 write_x_array(addr,k,1'b0);
25486 else if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b1))
25488 write_cam_array(addr,k,1'b1);
25489 write_x_array(addr,k,1'b0);
25492 else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b1))
25494 write_cam_array(addr,k,1'b1);
25495 write_x_array(addr,k,1'b1);
25503 if (writex_done == 1'b1)
25505 for (k =0; k<width; k=k+1)
25507 if ((pattern[k] ^ wrx_int[k]) == 1'b0)
25510 if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b0))
25512 write_cam_array(addr,k,1'b0);
25513 write_x_array(addr,k,1'b0);
25516 else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b0))
25518 write_cam_array(addr,k,1'b0);
25519 write_x_array(addr,k,1'b1);
25522 else if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b1))
25524 write_cam_array(addr,k,1'b0);
25525 write_x_array(addr,k,1'b1);
25528 else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b1))
25530 write_cam_array(addr,k,1'b0);
25531 write_x_array(addr,k,1'b0);
25534 else if ((pattern[k] ^ wrx_int[k]) == 1'b1)
25537 if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b0))
25539 write_cam_array(addr,k,1'b0);
25540 write_x_array(addr,k,1'b1);
25543 else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b0))
25545 write_cam_array(addr,k,1'b1);
25546 write_x_array(addr,k,1'b0);
25549 else if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b1))
25551 write_cam_array(addr,k,1'b0);
25552 write_x_array(addr,k,1'b1);
25555 else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b1))
25557 write_cam_array(addr,k,1'b1);
25558 write_x_array(addr,k,1'b0);
25565 begin // 2 Cycle write
25566 ///////////////////
25567 // 2 CYCLE WRITE //
25568 ///////////////////
25572 if (write0_done == 1'b1)
25574 for (k =0; k<width; k=k+1)
25576 if (pattern[k] == 1'b0)
25579 if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b0))
25581 write_cam_array(addr,k,1'b0);
25582 write_x_array(addr,k,1'b0);
25585 else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b0))
25587 write_cam_array(addr,k,1'b0);
25588 write_x_array(addr,k,1'b1);
25591 else if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b1))
25593 write_cam_array(addr,k,1'b0);
25594 write_x_array(addr,k,1'b1);
25597 else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b1))
25599 write_cam_array(addr,k,1'b0);
25600 write_x_array(addr,k,1'b0);
25603 else if (pattern[k] == 1'b1)
25606 if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b0))
25608 write_cam_array(addr,k,1'b0);
25609 write_x_array(addr,k,1'b1);
25612 else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b0))
25614 write_cam_array(addr,k,1'b1);
25615 write_x_array(addr,k,1'b0);
25618 else if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b1))
25620 write_cam_array(addr,k,1'b0);
25621 write_x_array(addr,k,1'b1);
25624 else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b1))
25626 write_cam_array(addr,k,1'b1);
25627 write_x_array(addr,k,1'b0);
25635 if (write1_done == 1'b1)
25637 for (k =0; k<width; k=k+1)
25639 if (pattern[k] == 1'b0)
25642 if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b0))
25644 write_cam_array(addr,k,1'b0);
25645 write_x_array(addr,k,1'b0);
25648 else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b0))
25650 write_cam_array(addr,k,1'b1);
25651 write_x_array(addr,k,1'b1);
25654 else if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b1))
25656 write_cam_array(addr,k,1'b0);
25657 write_x_array(addr,k,1'b0);
25660 else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b1))
25662 write_cam_array(addr,k,1'b1);
25663 write_x_array(addr,k,1'b1);
25666 else if (pattern[k] == 1'b1)
25669 if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b0))
25671 write_cam_array(addr,k,1'b1);
25672 write_x_array(addr,k,1'b1);
25675 else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b0))
25677 write_cam_array(addr,k,1'b1);
25678 write_x_array(addr,k,1'b0);
25681 else if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b1))
25683 write_cam_array(addr,k,1'b1);
25684 write_x_array(addr,k,1'b0);
25687 else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b1))
25689 write_cam_array(addr,k,1'b1);
25690 write_x_array(addr,k,1'b1);
25698 begin // if (wrdelete == 1'b1) begin
25699 ////////////////////
25700 // 2 CYCLE DELETE //
25701 ////////////////////
25702 // Delete is a 2-cycle write
25706 if (write0_done == 1'b1)
25708 for (k =0; k<width; k=k+1)
25710 write_cam_array(addr,k,1'b1);
25716 if (write1_done == 1'b1)
25718 for (k =0; k<width; k=k+1)
25720 write_x_array(addr,k,1'b1);
25725 //////////////////////////////////////
25726 // FAST MULTIPLE: READ DURING WRITE //
25727 //////////////////////////////////////
25728 // Now we need to update mbits, mcount during the write.
25729 if (match_mode == "FAST_MULTIPLE")
25731 mfound_int <= 1'b0;
25732 maddress_int <= address_1;
25734 mbits_tmp = numwords_0;
25735 if ((writex_done == 1'b1) && (wrxused_int == 1'b1))
25737 begin: WADDR_FM_2 for (k=0; k<numwords; k=k+1)
25738 begin: WWORD_FM_2 for (j=0; j<width; j=j+1)
25739 if (((read_x_array(k,j) == 1'b0) && (read_cam_array(k,j) == (pattern[j] ^ wrx_int[j]))) ||
25740 ((read_x_array(k,j) == 1'b1) && (read_cam_array(k,j) == 1'b0)))
25744 if ((count == 0) && (mstart_used == 1'b0))
25746 mfound_int <= 1'b1;
25749 mbits_tmp[k] = 1'b1;
25762 begin: WADDR_FM_3 for (k=0; k<numwords; k=k+1)
25763 begin: WWORD_FM_3 for (j=0; j<width; j=j+1)
25764 if (((read_x_array(k,j) == 1'b0) && (read_cam_array(k,j) == pattern[j])) ||
25765 ((read_x_array(k,j) == 1'b1) && (read_cam_array(k,j) == 1'b0)))
25769 if ((count == 0) && (mstart_used == 1'b0))
25771 mfound_int <= 1'b1;
25774 mbits_tmp[k] = 1'b1;
25785 mcount_int <= count;
25786 mbits_int <= mbits_tmp;
25787 end // end of FAST MULTIPLE
25789 /////////////////////////////////
25790 // MULTIPLE: READ DURING WRITE //
25791 /////////////////////////////////
25792 if ((match_mode == "MULTIPLE"))
25794 mfound_int <= 1'b0;
25795 maddress_int <= address_1;
25796 mbits_tmp = numwords_0;
25797 if ((writex_done == 1'b1) && (iwrxused == 1'b1))
25800 first_read_in_write <= 1'b0;
25804 if (first_read_in_write == 1'b0)
25806 first_read_in_write <= 1'b1;
25807 // Read even addresses but they appear on the odd locations
25810 begin: WADDR_MM_2 for (k=0; k<numwords; k=k+1)
25813 if (mbits_int[k] == 1'b1)
25814 begin // counting previous even address matches
25817 begin: WWORD_MM_2 for (j=0; j<width; j=j+1)
25818 if (((read_x_array(k,j) == 1'b0) && (read_cam_array(k,j) == pattern[j])) ||
25819 ((read_x_array(k,j) == 1'b1) && (read_cam_array(k,j) == 1'b0)))
25823 mbits_tmp[k+1] = 1'b1;
25837 first_read_in_write <= 1'b0;
25838 // Read odd addresses.
25840 begin: WADDR_MM_3 for (k=numwords-1; k>=0; k=k-1)
25843 mbits_tmp[k-1] = mbits_tmp[k];
25847 begin: WWORD_MM_3 for (j=0; j<width; j=j+1)
25848 if (((read_x_array(k,j) == 1'b0) && (read_cam_array(k,j) == pattern[j])) ||
25849 ((read_x_array(k,j) == 1'b1) && (read_cam_array(k,j) == 1'b0)))
25853 mbits_tmp[k] = 1'b1;
25865 mcount_int <= count;
25866 mbits_int <= mbits_tmp;
25868 end // end of MULTIPLE
25870 ///////////////////////////////
25871 // SINGLE: READ DURING WRITE //
25872 ///////////////////////////////
25873 if (match_mode == "SINGLE")
25875 mbits_tmp = numwords_0;
25878 if ((writex_done == 1'b1) && (wrxused_int == 1'b1))
25880 begin: WADDR_SM_2 for (k=0; k<numwords; k=k+1)
25881 begin: WWORD_SM_2 for (j=0; j<width; j=j+1)
25882 if (((read_x_array(k,j) == 1'b0) && (read_cam_array(k,j) == (pattern[j] ^ wrx_int[j]))) ||
25883 ((read_x_array(k,j) == 1'b1) && (read_cam_array(k,j) == 1'b0)))
25887 mbits_tmp[k] = 1'b1;
25903 begin: WADDR_SM_3 for (k=0; k<numwords; k=k+1)
25904 begin: WWORD_SM_3 for (j=0; j<width; j=j+1)
25905 if (((read_x_array(k,j) == 1'b0) && (read_cam_array(k,j) == pattern[j])) ||
25906 ((read_x_array(k,j) == 1'b1) && (read_cam_array(k,j) == 1'b0)))
25910 mbits_tmp[k] = 1'b1;
25924 mcount_int <= count;
25925 mbits_int <= mbits_tmp;
25928 mfound_int <= 1'b0;
25929 maddress_int <= address_0;
25933 mfound_int <= 1'b1;
25934 maddress_int <= index;
25936 end // end of SINGLE
25937 end // End of wren_rgd==1
25938 end // end of Write on pattern change
25939 end // end of pattern change
25941 // End: Change in pattern
25943 // Begin: Write Busy Control
25944 always @ (posedge wren_rgd)
25946 wrbusy_int <= 1'b1;
25949 always @ (negedge wren_rgd)
25951 wrbusy_int <= 1'b0;
25954 always @ (wraddress_rgd)
25956 if (wren_rgd == 1'b1)
25957 wrbusy_int <= 1'b1;
25960 always @ (posedge write_start_rgd)
25962 wrbusy_int <= 1'b0;
25965 always @ (negedge write_start_rgd)
25967 if (wren_rgd == 1'b1)
25968 wrbusy_int <= 1'b1;
25970 // End: Write Busy Control
25972 // Begin: Registered Outputs
25973 always @ (posedge outclock or posedge outaclr)
25975 if (output_reg == "OUTCLOCK")
25977 if ((outaclr == 1'b1) && (output_aclr == "ON" ))
25979 maddress_rgd <= address_0;
25980 mbits_rgd <= numwords_0;
25981 mfound_rgd <= 1'b0;
25982 mcount_rgd <= address_0;
25984 else if (outclocken_pullup == 1'b1)
25986 maddress_rgd <= maddress_int;
25987 mbits_rgd <= mbits_int;
25988 mfound_rgd <= mfound_int;
25989 mcount_rgd <= mcount_int;
25994 always @ (posedge outaclr or posedge inclock)
25996 if (output_reg == "INCLOCK")
25998 if (output_aclr == "ON" )
26000 if (outaclr == 1'b1)
26002 maddress_rgd <= address_0;
26003 mbits_rgd <= numwords_0;
26004 mfound_rgd <= 1'b0;
26005 mcount_rgd <= address_0;
26007 else if (inclocken_pullup == 1'b1)
26009 maddress_rgd <= maddress_int;
26010 mbits_rgd <= mbits_int;
26011 mfound_rgd <= mfound_int;
26012 mcount_rgd <= mcount_int;
26015 else if ((inclocken_pullup == 1'b1) && (inaclr_pulldown != 1'b1))
26017 maddress_rgd <= maddress_int;
26018 mbits_rgd <= mbits_int;
26019 mfound_rgd <= mfound_int;
26020 mcount_rgd <= mcount_int;
26024 // End: Registered Outputs
26026 // Begin: Write Control
26027 always @ (posedge wrbusy_int)
26034 always @ (negedge wrbusy_int)
26039 always @ (posedge write0_done)
26042 if ((wrxused_int == 1'b1) && (wrx !== {width{1'bz}})) write0 <= 1'b0;
26045 always @ (posedge write1_done)
26047 if ((wrxused_int == 1'b1) && (wrx !== {width{1'bz}} )) writex <= 1'b1;
26048 else writex <= 1'b0;
26052 always @ (posedge writex_done)
26059 // Begin: Read Control
26060 always @ (posedge mstart_rgd1)
26062 if ((match_mode == "SINGLE") || (match_mode == "FAST_MULTIPLE")) rdbusy_int <= 1'b0;
26063 else rdbusy_int <= 1'b1;
26066 always @ (posedge mstart_rgd2)
26068 rdbusy_int <= 1'b0;
26071 always @ (posedge mnext)
26073 if (get_first_match == 1'b1) get_next_match <= 1'b1;
26076 always @ (negedge mnext)
26078 get_next_match <= 1'b0;
26080 // End: Read Control
26082 // Evaluate parameters
26083 assign pattern_int = (pattern_reg == "UNREGISTERED") ? pattern : pattern_rgd;
26084 assign wrx_int = (wrx_reg == "UNREGISTERED" ) ? wrx : wrx_rgd;
26085 assign wrxused_int = (wrx_reg == "UNREGISTERED") ? wrxused_pullup : wrxused_rgd;
26086 assign maddress = (output_reg == "UNREGISTERED") ? maddress_int : maddress_rgd;
26087 assign mbits = (output_reg == "UNREGISTERED") ? mbits_int : mbits_rgd;
26088 assign mfound = (output_reg == "UNREGISTERED") ? mfound_int : mfound_rgd;
26089 assign mcount = (output_reg == "UNREGISTERED") ? mcount_int : mcount_rgd;
26090 assign wrbusy = wrbusy_int;
26091 assign rdbusy = rdbusy_int;
26092 assign outclock_int = (output_reg == "OUTCLOCK") ? outclock : inclock;
26093 assign outaclr_int = (output_reg == "OUTCLOCK") ? outaclr : inaclr_pulldown;
26094 assign wrxused_pullup = wrxused;
26095 assign inclocken_pullup = inclocken;
26096 assign outclocken_pullup = outclocken;
26097 assign wrdelete_pulldown = wrdelete;
26098 assign inaclr_pulldown = inaclr;
26100 assign # 2 rdbusy_delayed = rdbusy_int;
26102 endmodule // end of altcam
26104 //--------------------------------------------------------------------------
26105 // Module Name : altdpram
26107 // Description : Parameterized Dual Port RAM megafunction
26109 // Limitation : This megafunction is provided only for backward
26110 // compatibility in Cyclone, Stratix, and Stratix GX
26113 // Results expected : RAM having dual ports (separate Read and Write)
26116 //--------------------------------------------------------------------------
26117 `timescale 1 ps / 1 ps
26119 // MODULE DECLARATION
26120 module altdpram (wren, data, wraddress, inclock, inclocken, rden, rdaddress,
26121 outclock, outclocken, aclr, q);
26123 // PARAMETER DECLARATION
26124 parameter width = 1;
26125 parameter widthad = 1;
26126 parameter numwords = 0;
26127 parameter lpm_file = "UNUSED";
26128 parameter lpm_hint = "USE_EAB=ON";
26129 parameter use_eab = "ON";
26130 parameter lpm_type = "altdpram";
26131 parameter indata_reg = "INCLOCK";
26132 parameter indata_aclr = "ON";
26133 parameter wraddress_reg = "INCLOCK";
26134 parameter wraddress_aclr = "ON";
26135 parameter wrcontrol_reg = "INCLOCK";
26136 parameter wrcontrol_aclr = "ON";
26137 parameter rdaddress_reg = "OUTCLOCK";
26138 parameter rdaddress_aclr = "ON";
26139 parameter rdcontrol_reg = "OUTCLOCK";
26140 parameter rdcontrol_aclr = "ON";
26141 parameter outdata_reg = "UNREGISTERED";
26142 parameter outdata_aclr = "ON";
26143 parameter maximum_depth = 2048;
26144 parameter intended_device_family = "APEX20KE";
26145 parameter write_at_low_clock = ((wrcontrol_reg == "INCLOCK") &&
26146 (((lpm_hint == "USE_EAB=ON") || (lpm_hint == "UNUSED")) &&
26147 (use_eab == "ON"))) ?
26149 parameter rden_low_output_0 = ((intended_device_family == "APEX20K") &&
26150 (((lpm_hint == "USE_EAB=ON") || (lpm_hint == "UNUSED")) &&
26151 (use_eab == "ON"))) ?
26154 // INPUT PORT DECLARATION
26155 input wren; // Write enable input
26156 input [width-1:0] data; // Data input to the memory
26157 input [widthad-1:0] wraddress; // Write address input to the memory
26158 input inclock; // Input or write clock
26159 input inclocken; // Clock enable for inclock
26160 input rden; // Read enable input. Disable reading when low
26161 input [widthad-1:0] rdaddress; // Write address input to the memory
26162 input outclock; // Output or read clock
26163 input outclocken; // Clock enable for outclock
26164 input aclr; // Asynchronous clear input
26166 // OUTPUT PORT DECLARATION
26167 output [width-1:0] q; // Data output from the memory
26169 // INTERNAL SIGNAL/REGISTER DECLARATION
26170 reg [width-1:0] mem_data [0:(1<<widthad)-1];
26171 reg [8*256:1] ram_initf;
26172 reg [width-1:0] data_write_at_high;
26173 reg [width-1:0] data_write_at_low;
26174 reg [widthad-1:0] wraddress_at_high;
26175 reg [widthad-1:0] wraddress_at_low;
26176 reg [width-1:0] mem_output;
26177 reg [width-1:0] mem_output_at_outclock;
26178 reg [widthad-1:0] rdaddress_at_inclock;
26179 reg [widthad-1:0] rdaddress_at_outclock;
26182 reg rden_at_inclock;
26183 reg rden_at_outclock;
26185 // INTERNAL WIRE DECLARATION
26186 wire aclr_on_wraddress;
26187 wire aclr_on_wrcontrol;
26188 wire aclr_on_rdaddress;
26189 wire aclr_on_rdcontrol;
26190 wire aclr_on_indata;
26191 wire aclr_on_outdata;
26192 wire [width-1:0] data_tmp;
26193 wire [width-1:0] previous_read_data;
26194 wire [width-1:0] new_read_data;
26195 wire [widthad-1:0] wraddress_tmp;
26196 wire [widthad-1:0] rdaddress_tmp;
26200 // INTERNAL TRI DECLARATION
26208 // LOCAL INTEGER DECLARATION
26210 integer i_numwords;
26212 // COMPONENT INSTANTIATIONS
26213 ALTERA_MF_MEMORY_INITIALIZATION mem ();
26215 // INITIAL CONSTRUCT BLOCK
26218 // Check for invalid parameters
26221 $display("Error! width parameter must be greater than 0.");
26226 $display("Error! widthad parameter must be greater than 0.");
26230 // Initialize mem_data
26231 i_numwords = (numwords) ? numwords : 1<<widthad;
26232 if (lpm_file == "UNUSED")
26233 for (i=0; i<i_numwords; i=i+1)
26238 $readmemh(lpm_file, mem_data);
26241 $readmemh(lpm_file, mem_data);
26243 mem.convert_hex2ver(lpm_file, width, ram_initf);
26244 $readmemh(ram_initf, mem_data);
26249 // Power-up conditions
26251 mem_output_at_outclock = 0;
26252 data_write_at_high = 0;
26253 data_write_at_low = 0;
26254 rdaddress_at_inclock = 0;
26255 rdaddress_at_outclock = 0;
26256 rden_at_outclock = 1;
26257 rden_at_inclock = 1;
26261 // ALWAYS CONSTRUCT BLOCKS
26263 // Set up logics that respond to the postive edge of inclock
26264 // some logics may be affected by Asynchronous Clear
26265 always @(posedge inclock)
26267 if ((aclr == 1) && (indata_aclr == "ON") && (indata_reg != "UNREGISTERED") )
26268 data_write_at_high <= 0;
26269 else if (inclocken == 1)
26270 data_write_at_high <= data;
26272 if ((aclr == 1) && (wraddress_aclr == "ON") && (wraddress_reg != "UNREGISTERED") )
26273 wraddress_at_high <= 0;
26274 else if (inclocken == 1)
26275 wraddress_at_high <= wraddress;
26277 if ((aclr == 1) && (wrcontrol_aclr == "ON") && (wrcontrol_reg != "UNREGISTERED") )
26279 else if (inclocken == 1)
26280 wren_at_high <= wren;
26282 if ((aclr == 1) && (rdaddress_aclr == "ON") && (rdaddress_reg != "UNREGISTERED") )
26283 rdaddress_at_inclock <= 0;
26284 else if (inclocken == 1)
26285 rdaddress_at_inclock <= rdaddress;
26287 if ((aclr == 1) && (rdcontrol_aclr == "ON") && (rdcontrol_reg != "UNREGISTERED") )
26288 rden_at_inclock <= 0;
26289 else if (inclocken == 1)
26290 rden_at_inclock <= rden;
26293 // Set up logics that respond to the negative edge of inclock
26294 // some logics may be affected by Asynchronous Clear
26295 always @(negedge inclock)
26297 if ((aclr == 1) && (indata_aclr == "ON") && (indata_reg != "UNREGISTERED") )
26298 data_write_at_low <= 0;
26299 else if (inclocken == 1)
26300 data_write_at_low <= data_write_at_high;
26302 if ((aclr == 1) && (wraddress_aclr == "ON") && (wraddress_reg != "UNREGISTERED") )
26303 wraddress_at_low <= 0;
26304 else if (inclocken == 1)
26305 wraddress_at_low <= wraddress_at_high;
26307 if ((aclr == 1) && (wrcontrol_aclr == "ON") && (wrcontrol_reg != "UNREGISTERED") )
26309 else if (inclocken == 1)
26310 wren_at_low <= wren_at_high;
26313 // Set up logics that respond to the positive edge of outclock
26314 // some logics may be affected by Asynchronous Clear
26315 always @(posedge outclock)
26317 if ((aclr == 1) && (rdaddress_aclr == "ON") && (rdaddress_reg != "UNREGISTERED") )
26318 rdaddress_at_outclock <= 0;
26319 else if (outclocken == 1)
26320 rdaddress_at_outclock <= rdaddress;
26322 if ((aclr == 1) && (rdcontrol_aclr == "ON") && (rdcontrol_reg != "UNREGISTERED") )
26323 rden_at_outclock <= 0;
26324 else if (outclocken == 1)
26325 rden_at_outclock <= rden;
26327 if ((aclr == 1) && (outdata_aclr == "ON") && (outdata_reg != "UNREGISTERED") )
26328 mem_output_at_outclock <= 0;
26329 else if (outclocken == 1)
26330 mem_output_at_outclock <= mem_output;
26333 // Asynchronous Logic
26334 // Update memory with the latest data
26335 always @(data_tmp or wraddress_tmp or wren_tmp)
26338 mem_data[wraddress_tmp] <= data_tmp;
26341 always @(new_read_data)
26343 mem_output <= new_read_data;
26346 // CONTINUOUS ASSIGNMENT
26348 // The following circuits will select for appropriate connections based on
26349 // the given parameter values
26351 assign aclr_on_wraddress = ((wraddress_aclr == "ON") ?
26355 assign aclr_on_wrcontrol = ((wrcontrol_aclr == "ON") ?
26359 assign aclr_on_rdaddress = ((rdaddress_aclr == "ON") ?
26363 assign aclr_on_rdcontrol = ((rdcontrol_aclr == "ON") ?
26367 assign aclr_on_indata = ((indata_aclr == "ON") ?
26371 assign aclr_on_outdata = ((outdata_aclr == "ON") ?
26375 assign data_tmp = ((indata_reg == "INCLOCK") ?
26376 (write_at_low_clock ?
26377 ((aclr_on_indata == 1) ?
26379 : data_write_at_low)
26380 : ((aclr_on_indata == 1) ?
26382 : data_write_at_high))
26385 assign wraddress_tmp = ((wraddress_reg == "INCLOCK") ?
26386 (write_at_low_clock ?
26387 ((aclr_on_wraddress == 1) ?
26389 : wraddress_at_low)
26390 : ((aclr_on_wraddress == 1) ?
26392 : wraddress_at_high))
26395 assign wren_tmp = ((wrcontrol_reg == "INCLOCK") ?
26396 (write_at_low_clock ?
26397 ((aclr_on_wrcontrol == 1) ?
26400 : ((aclr_on_wrcontrol == 1) ?
26405 assign rdaddress_tmp = ((rdaddress_reg == "INCLOCK") ?
26406 ((aclr_on_rdaddress == 1) ?
26408 : rdaddress_at_inclock)
26409 : ((rdaddress_reg == "OUTCLOCK") ?
26410 ((aclr_on_rdaddress == 1) ?
26412 : rdaddress_at_outclock)
26415 assign rden_tmp = ((rdcontrol_reg == "INCLOCK") ?
26416 ((aclr_on_rdcontrol == 1) ?
26419 : ((rdcontrol_reg == "OUTCLOCK") ?
26420 ((aclr_on_rdcontrol == 1) ?
26422 : rden_at_outclock)
26425 assign previous_read_data = mem_output;
26427 assign new_read_data = ((rden_tmp == 1) ?
26428 mem_data[rdaddress_tmp]
26429 : ((rden_low_output_0) ?
26431 : previous_read_data));
26433 assign q = ((outdata_reg == "OUTCLOCK")?
26434 ((aclr_on_outdata == 1) ?
26436 :mem_output_at_outclock)
26439 endmodule // altdpram
26441 // START_MODULE_NAME------------------------------------------------------------
26443 // Module Name : ALTSYNCRAM
26445 // Description : Synchronous ram model for Stratix series family
26449 // END_MODULE_NAME--------------------------------------------------------------
26451 `timescale 1 ps / 1 ps
26453 // BEGINNING OF MODULE
26455 // MODULE DECLARATION
26457 module altsyncram (
26479 // GLOBAL PARAMETER DECLARATION
26481 // PORT A PARAMETERS
26482 parameter width_a = 1;
26483 parameter widthad_a = 1;
26484 parameter numwords_a = 0;
26485 parameter outdata_reg_a = "UNREGISTERED";
26486 parameter address_aclr_a = "NONE";
26487 parameter outdata_aclr_a = "NONE";
26488 parameter indata_aclr_a = "NONE";
26489 parameter wrcontrol_aclr_a = "NONE";
26490 parameter byteena_aclr_a = "NONE";
26491 parameter width_byteena_a = 1;
26493 // PORT B PARAMETERS
26494 parameter width_b = 1;
26495 parameter widthad_b = 1;
26496 parameter numwords_b = 0;
26497 parameter rdcontrol_reg_b = "CLOCK1";
26498 parameter address_reg_b = "CLOCK1";
26499 parameter outdata_reg_b = "UNREGISTERED";
26500 parameter outdata_aclr_b = "NONE";
26501 parameter rdcontrol_aclr_b = "NONE";
26502 parameter indata_reg_b = "CLOCK1";
26503 parameter wrcontrol_wraddress_reg_b = "CLOCK1";
26504 parameter byteena_reg_b = "CLOCK1";
26505 parameter indata_aclr_b = "NONE";
26506 parameter wrcontrol_aclr_b = "NONE";
26507 parameter address_aclr_b = "NONE";
26508 parameter byteena_aclr_b = "NONE";
26509 parameter width_byteena_b = 1;
26511 // STRATIX II RELATED PARAMETERS
26512 parameter clock_enable_input_a = "NORMAL";
26513 parameter clock_enable_output_a = "NORMAL";
26514 parameter clock_enable_input_b = "NORMAL";
26515 parameter clock_enable_output_b = "NORMAL";
26517 // GLOBAL PARAMETERS
26518 parameter operation_mode = "BIDIR_DUAL_PORT";
26519 parameter byte_size = 8;
26520 parameter read_during_write_mode_mixed_ports = "DONT_CARE";
26521 parameter ram_block_type = "AUTO";
26522 parameter init_file = "UNUSED";
26523 parameter init_file_layout = "UNUSED";
26524 parameter maximum_depth = 0;
26525 parameter intended_device_family = "Stratix";
26527 parameter lpm_hint = "UNUSED";
26528 parameter lpm_type = "altsyncram";
26530 parameter cread_during_write_mode_mixed_ports =
26531 ((read_during_write_mode_mixed_ports == "DONT_CARE") ||
26532 (read_during_write_mode_mixed_ports == "UNUSED"))? "DONT_CARE":
26533 read_during_write_mode_mixed_ports;
26535 parameter implement_in_les = "OFF";
26537 parameter power_up_uninitialized = "FALSE";
26539 // Internal parameters
26540 parameter is_bidir_and_wrcontrol_addb_clk0 = (((operation_mode == "BIDIR_DUAL_PORT") && (wrcontrol_wraddress_reg_b == "CLOCK0"))?
26542 parameter is_bidir_and_wrcontrol_addb_clk1 = (((operation_mode == "BIDIR_DUAL_PORT") && (wrcontrol_wraddress_reg_b == "CLOCK1"))?
26545 parameter megaram_or_mram = (((ram_block_type == "M-RAM") || (ram_block_type == "MEGARAM"))? 1: 0);
26547 parameter check_simultaneous_read_write = ((megaram_or_mram ||
26548 ((cread_during_write_mode_mixed_ports == "DONT_CARE") &&
26549 (ram_block_type == "AUTO")))? 1 : 0);
26550 parameter dual_port_addreg_b_clk0 = (((operation_mode == "DUAL_PORT") && (address_reg_b == "CLOCK0"))? 1: 0);
26552 parameter dual_port_addreg_b_clk1 = (((operation_mode == "DUAL_PORT") && (address_reg_b == "CLOCK1"))? 1: 0);
26555 // INPUT PORT DECLARATION
26557 input wren_a; // Port A write/read enable input
26558 input wren_b; // Port B write enable input
26559 input rden_b; // Port B read enable input
26560 input [width_a-1:0] data_a; // Port A data input
26561 input [width_b-1:0] data_b; // Port B data input
26562 input [widthad_a-1:0] address_a; // Port A address input
26563 input [widthad_b-1:0] address_b; // Port B address input
26565 // clock inputs on both ports and here are their usage
26566 // Port A -- 1. all input registers must be clocked by clock0.
26567 // 2. output register can be clocked by either clock0, clock1 or none.
26568 // Port B -- 1. all input registered must be clocked by either clock0 or clock1.
26569 // 2. output register can be clocked by either clock0, clock1 or none.
26573 // clock enable inputs and here are their usage
26574 // clocken0 -- can only be used for enabling clock0.
26575 // clocken1 -- can only be used for enabling clock1.
26579 // clear inputs on both ports and here are their usage
26580 // Port A -- 1. all input registers can only be cleared by clear0 or none.
26581 // 2. output register can be cleared by either clear0, clear1 or none.
26582 // Port B -- 1. all input registers can be cleared by clear0, clear1 or none.
26583 // 2. output register can be cleared by either clear0, clear1 or none.
26587 input [width_byteena_a-1:0] byteena_a; // Port A byte enable input
26588 input [width_byteena_b-1:0] byteena_b; // Port B byte enable input
26590 // Stratix II related ports
26591 input addressstall_a;
26592 input addressstall_b;
26596 // OUTPUT PORT DECLARATION
26598 output [width_a-1:0] q_a; // Port A output
26599 output [width_b-1:0] q_b; // Port B output
26601 // INTERNAL REGISTERS DECLARATION
26603 reg [width_a-1:0] mem_data [0:(1<<widthad_a)-1];
26604 reg [width_b-1:0] mem_data_b [0:(1<<widthad_b)-1];
26605 reg [width_a-1:0] i_data_reg_a;
26606 reg [width_a-1:0] temp_wa;
26607 reg [width_a-1:0] temp_wa2;
26608 reg [width_a-1:0] temp_wa2b;
26609 reg [width_b-1:0] i_data_reg_b;
26610 reg [width_b-1:0] temp_wb;
26611 reg [width_b-1:0] temp_wb2;
26613 reg [width_a-1:0] i_q_reg_a;
26614 reg [width_a-1:0] i_q_tmp_a;
26615 reg [width_a-1:0] i_q_tmp2_a;
26616 reg [width_b-1:0] i_q_reg_b;
26617 reg [width_b-1:0] i_q_tmp_b;
26618 reg [width_b-1:0] i_q_tmp2_b;
26619 reg [width_a-1:0] i_byteena_mask_reg_a;
26620 reg [width_b-1:0] i_byteena_mask_reg_b;
26621 reg [widthad_a-1:0] i_address_reg_a;
26622 reg [widthad_b-1:0] i_address_reg_b;
26625 reg [width_a-1:0] i_byteena_mask_reg_a_tmp;
26626 reg [width_b-1:0] i_byteena_mask_reg_b_tmp;
26627 reg [width_a-1:0] i_byteena_mask_reg_a_out;
26628 reg [width_b-1:0] i_byteena_mask_reg_b_out;
26629 reg [width_a-1:0] i_byteena_mask_reg_a_x;
26630 reg [width_b-1:0] i_byteena_mask_reg_b_x;
26632 reg [8*256:1] ram_initf;
26638 reg i_write_flag_a;
26639 reg i_write_flag_b;
26642 reg [31:0] file_desc;
26643 reg init_file_b_port;
26644 reg i_nmram_write_a;
26645 reg i_nmram_write_b;
26647 reg [width_a - 1: 0] wa_mult_x;
26648 reg [width_a - 1: 0] wa_mult_x_ii;
26649 reg [width_a - 1: 0] wa_mult_x_iii;
26650 reg [widthad_a + width_a - 1:0] add_reg_a_mult_wa;
26651 reg [widthad_b + width_b -1:0] add_reg_b_mult_wb;
26652 reg [widthad_a + width_a - 1:0] add_reg_a_mult_wa_pl_wa;
26653 reg [widthad_b + width_b -1:0] add_reg_b_mult_wb_pl_wb;
26656 // INTERNAL WIRE DECLARATIONS
26658 wire i_indata_aclr_a;
26659 wire i_address_aclr_a;
26660 wire i_wrcontrol_aclr_a;
26661 wire i_indata_aclr_b;
26662 wire i_address_aclr_b;
26663 wire i_wrcontrol_aclr_b;
26664 wire i_outdata_aclr_a;
26665 wire i_outdata_aclr_b;
26666 wire i_rdcontrol_aclr_b;
26667 wire i_byteena_aclr_a;
26668 wire i_byteena_aclr_b;
26669 wire i_outdata_clk_a;
26670 wire i_outdata_clken_a;
26671 wire i_outdata_clk_b;
26672 wire i_outdata_clken_b;
26677 // INTERNAL TRI DECLARATION
26688 tri0 addressstall_a;
26689 tri0 addressstall_b;
26690 tri1 [width_byteena_a-1:0] i_byteena_a;
26691 tri1 [width_byteena_b-1:0] i_byteena_b;
26694 // LOCAL INTEGER DECLARATION
26696 integer i_numwords_a;
26697 integer i_numwords_b;
26698 integer i_aclr_flag_a;
26699 integer i_aclr_flag_b;
26700 integer i_q_tmp2_a_idx;
26702 // for loop iterators
26715 // For temporary calculation
26718 integer j2_plus_i5;
26719 integer j_plus_i2_div_a;
26720 integer j2_plus_i5_div_a;
26722 // ------------------------
26723 // COMPONENT INSTANTIATIONS
26724 // ------------------------
26725 ALTERA_DEVICE_FAMILIES dev ();
26726 ALTERA_MF_MEMORY_INITIALIZATION mem ();
26729 // INITIAL CONSTRUCT BLOCK
26734 i_numwords_a = (numwords_a != 0) ? numwords_a : (1 << widthad_a);
26735 i_numwords_b = (numwords_b != 0) ? numwords_b : (1 << widthad_b);
26737 // Parameter Checking
26738 if ((operation_mode != "BIDIR_DUAL_PORT") && (operation_mode != "SINGLE_PORT") &&
26739 (operation_mode != "DUAL_PORT") && (operation_mode != "ROM"))
26741 $display("Error: Not a valid operation mode.");
26745 if ((ram_block_type != "M4K") && (ram_block_type != "M512") &&
26746 (ram_block_type != "M-RAM") && (ram_block_type != "MEGARAM") &&
26747 (ram_block_type != "AUTO"))
26749 $display("Error: RAM_BLOCK_TYPE HAS AN INVALID VALUE. IT CAN ONLY BE M512, M4K, M-RAM OR AUTO");
26753 if ((cread_during_write_mode_mixed_ports != "DONT_CARE") &&
26754 (cread_during_write_mode_mixed_ports != "OLD_DATA"))
26756 $display("Error: INVALID VALUE FOR READ_DURING_WRITE_MODE_MIXED_PORTS PARAMETER. IT HAS TO BE OLD_DATA OR DONT_CARE");
26760 if (ram_block_type == "LARGE" && init_file != "UNUSED")
26762 $display("Error: M-RAM block type doesn't support the use of an initialization file");
26766 if ((byte_size != 8) && (byte_size != 9) && (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0))
26768 $display("Error: BYTE SIZE HAS TO BE EITHER 8 or 9");
26772 if ((byte_size != 8) && (byte_size != 9) && (byte_size != 1) &&
26773 (byte_size != 2) && (byte_size != 4) && (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 1))
26775 $display("Error: BYTE SIZE has to be either 1, 2, 4, 8 or 9");
26781 $display("Error: Invalid value for WIDTH_A parameter");
26785 if ((width_b <= 0) &&
26786 ((operation_mode != "SINGLE_PORT") || (operation_mode != "ROM")))
26788 $display("Error: Invalid value for WIDTH_B parameter");
26792 if (widthad_a <= 0)
26794 $display("Error: Invalid value for WIDTHAD_A parameter");
26798 if ((width_b <= 0) &&
26799 ((operation_mode != "SINGLE_PORT") || (operation_mode != "ROM")))
26801 $display("Error: Invalid value for WIDTHAD_B parameter");
26805 if ((operation_mode == "ROM") &&
26806 ((ram_block_type == "M-RAM") || (ram_block_type == "MEGARAM")))
26808 $display("Error: ROM mode does not support ram_block_type = M-RAM");
26812 if (((wrcontrol_aclr_a != "NONE") && (wrcontrol_aclr_a != "UNUSED")) && (ram_block_type == "M512") && (operation_mode == "SINGLE_PORT"))
26814 $display("Error: Wren_a cannot have clear in single port mode for M512 block");
26818 if ((operation_mode == "DUAL_PORT") && (i_numwords_a * width_a != i_numwords_b * width_b))
26820 $display("Error: Total number of bits of port A and port B should be the same for dual port mode");
26824 if (((rdcontrol_aclr_b != "NONE") && (rdcontrol_aclr_b != "UNUSED")) && (ram_block_type == "M512") && (operation_mode == "DUAL_PORT"))
26826 $display("Error: rden_b cannot have clear in simple dual port mode for M512 block");
26830 if ((operation_mode == "BIDIR_DUAL_PORT") && (i_numwords_a * width_a != i_numwords_b * width_b))
26832 $display("Error: Total number of bits of port A and port B should be the same for bidir dual port mode");
26836 if ((operation_mode == "BIDIR_DUAL_PORT") && (ram_block_type == "M512"))
26838 $display("Error: M512 block type doesn't support bidir dual mode");
26842 if (((ram_block_type == "M-RAM") || (ram_block_type == "MEGARAM")) &&
26843 (cread_during_write_mode_mixed_ports == "OLD_DATA"))
26845 $display("Error: M-RAM doesn't support OLD_DATA value for READ_DURING_WRITE_MODE_MIXED_PORTS parameter");
26849 if ((dev.FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family) == 0) && (clock_enable_input_a == "BYPASS"))
26851 $display("Error: BYPASS value for CLOCK_ENABLE_INPUT_A is not supported in %s device family", intended_device_family);
26855 if ((dev.FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family) == 0) && (clock_enable_output_a == "BYPASS"))
26857 $display("Error: BYPASS value for CLOCK_ENABLE_OUTPUT_A is not supported in %s device family", intended_device_family);
26861 if ((dev.FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family) == 0) && (clock_enable_input_b == "BYPASS"))
26863 $display("Error: BYPASS value for CLOCK_ENABLE_INPUT_B is not supported in %s device family", intended_device_family);
26867 if ((dev.FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family) == 0) && (clock_enable_output_b == "BYPASS"))
26869 $display("Error: BYPASS value for CLOCK_ENABLE_OUTPUT_B is not supported in %s device family", intended_device_family);
26873 if ((implement_in_les != "OFF") && (implement_in_les != "ON"))
26875 $display("Error: Illegal value for implement_in_les parameter");
26879 if (((dev.FEATURE_FAMILY_HAS_M512(intended_device_family)) == 0) && (ram_block_type == "M512"))
26881 $display("Error: M512 value for ram_block_type parameter is not supported in %s device family", intended_device_family);
26885 if (((dev.FEATURE_FAMILY_HAS_MEGARAM(intended_device_family)) == 0) && (ram_block_type == "MEGARAM"))
26887 $display("Error: MEGARAM value for ram_block_type parameter is not supported in %s device family", intended_device_family);
26891 // *****************************************
26892 // legal operations for all operation modes:
26893 // | PORT A | PORT B |
26894 // | RD WR | RD WR |
26895 // BDP | x x | x x |
26899 // *****************************************
26902 // Initialize mem_data
26904 if ((init_file == "UNUSED") || (init_file == ""))
26906 if (operation_mode == "ROM")
26907 $display("Error! altsyncram needs data file for memory initialization.\n");
26910 if ((check_simultaneous_read_write ||
26911 (dev.IS_FAMILY_HARDCOPYSTRATIX(intended_device_family) == 1) ||
26912 (dev.IS_FAMILY_HARDCOPYII(intended_device_family) == 1) ||
26913 (power_up_uninitialized == "TRUE") ) && (implement_in_les == "OFF") )
26915 wa_mult_x = {width_a{1'bx}};
26916 for (i = 0; i < (1 << widthad_a); i = i + 1)
26917 mem_data[i] = wa_mult_x;
26920 for (i = 0; i < (1 << widthad_a); i = i + 1)
26925 else // Memory initialization file is used
26927 if (check_simultaneous_read_write ||
26928 (((dev.IS_FAMILY_HARDCOPYSTRATIX(intended_device_family) == 1) ||
26929 (dev.IS_FAMILY_HARDCOPYII(intended_device_family) == 1) || (power_up_uninitialized == "TRUE")) &&
26930 (operation_mode != "ROM")))
26932 wa_mult_x = {width_a{1'bx}};
26933 for (i = 0; i < (1 << widthad_a); i = i + 1)
26934 mem_data[i] = wa_mult_x;
26938 wa_mult_x = {width_a{1'b0}};
26939 for (i = 0; i < (1 << widthad_a); i = i + 1)
26940 mem_data[i] = wa_mult_x;
26943 init_file_b_port = 0;
26945 if ((init_file_layout != "PORT_A") &&
26946 (init_file_layout != "PORT_B"))
26948 if (operation_mode == "DUAL_PORT")
26949 init_file_b_port = 1;
26951 init_file_b_port = 0;
26955 if (init_file_layout == "PORT_A")
26956 init_file_b_port = 0;
26957 else if (init_file_layout == "PORT_B")
26958 init_file_b_port = 1;
26961 if (init_file_b_port)
26964 $readmemh(init_file, mem_data_b);
26967 $readmemh(init_file, mem_data_b);
26969 mem.convert_hex2ver(init_file, width_b, ram_initf);
26970 $readmemh(ram_initf, mem_data_b);
26974 for (i = 0; i < (i_numwords_b * width_b); i = i + 1)
26976 temp_wb = mem_data_b[i / width_b];
26977 i_div_wa = i / width_a;
26978 temp_wa = mem_data[i_div_wa];
26979 temp_wa[i % width_a] = temp_wb[i % width_b];
26980 mem_data[i_div_wa] = temp_wa;
26986 $readmemh(init_file, mem_data);
26989 $readmemh(init_file, mem_data);
26991 mem.convert_hex2ver(init_file, width_a, ram_initf);
26992 $readmemh(ram_initf, mem_data);
26997 i_nmram_write_a = 0;
26998 i_nmram_write_b = 0;
27003 // Initialize internal registers/signals
27006 i_address_reg_a = 0;
27007 i_address_reg_b = 0;
27013 i_write_flag_a = 0;
27014 i_write_flag_b = 0;
27015 i_byteena_mask_reg_a = ~0;
27016 i_byteena_mask_reg_b = ~0;
27017 i_byteena_mask_reg_a_x = 0;
27018 i_byteena_mask_reg_b_x = 0;
27020 if (check_simultaneous_read_write)
27022 i_q_tmp_a = {width_a{1'bx}};
27023 i_q_tmp_b = {width_b{1'bx}};
27024 i_q_tmp2_a = {width_a{1'bx}};
27025 i_q_tmp2_b = {width_b{1'bx}};
27026 i_q_reg_a = {width_a{1'bx}};
27027 i_q_reg_b = {width_b{1'bx}};
27044 // SIGNAL ASSIGNMENT
27046 // Clock signal assignment
27048 // port a clock assignments:
27049 assign i_outdata_clk_a = (outdata_reg_a == "CLOCK1") ?
27050 clock1 : ((outdata_reg_a == "CLOCK0") ?
27052 // port b clock assignments:
27053 assign i_outdata_clk_b = (outdata_reg_b == "CLOCK1") ?
27054 clock1 : ((outdata_reg_b == "CLOCK0") ?
27057 // Clock enable signal assignment
27059 // port a clock enable assignments:
27060 assign i_outdata_clken_a = (clock_enable_output_a == "BYPASS") ?
27061 1'b1 : (outdata_reg_a == "CLOCK1") ?
27062 clocken1 : ((outdata_reg_a == "CLOCK0") ?
27064 // port b clock enable assignments:
27065 assign i_outdata_clken_b = (clock_enable_output_b == "BYPASS") ?
27066 1'b1 : (outdata_reg_b == "CLOCK0") ?
27067 clocken0 : ((outdata_reg_b == "CLOCK1") ?
27072 assign i_clocken0 = (clock_enable_input_a == "BYPASS") ?
27075 assign i_clocken0_b = (clock_enable_input_b == "BYPASS") ?
27078 assign i_clocken1 = (clock_enable_input_b == "BYPASS") ?
27083 // Async clear signal assignment
27085 // port a clear assigments:
27086 assign i_indata_aclr_a = (indata_aclr_a == "CLEAR0") ? aclr0 : 1'b0;
27087 assign i_address_aclr_a = (address_aclr_a == "CLEAR0") ? aclr0 : 1'b0;
27088 assign i_wrcontrol_aclr_a = (wrcontrol_aclr_a == "CLEAR0") ? aclr0 : 1'b0;
27089 assign i_byteena_aclr_a = (byteena_aclr_a == "CLEAR0") ?
27090 aclr0 : ((byteena_aclr_a == "CLEAR1") ?
27092 assign i_outdata_aclr_a = (outdata_aclr_a == "CLEAR0") ?
27093 aclr0 : ((outdata_aclr_a == "CLEAR1") ?
27095 // port b clear assignments:
27096 assign i_indata_aclr_b = (indata_aclr_b == "CLEAR0") ?
27097 aclr0 : ((indata_aclr_b == "CLEAR1") ?
27099 assign i_address_aclr_b = (address_aclr_b == "CLEAR0") ?
27100 aclr0 : ((address_aclr_b == "CLEAR1") ?
27102 assign i_wrcontrol_aclr_b = (wrcontrol_aclr_b == "CLEAR0") ?
27103 aclr0 : ((wrcontrol_aclr_b == "CLEAR1") ?
27105 assign i_rdcontrol_aclr_b = (rdcontrol_aclr_b == "CLEAR0") ?
27106 aclr0 : ((rdcontrol_aclr_b == "CLEAR1") ?
27108 assign i_byteena_aclr_b = (byteena_aclr_b == "CLEAR0") ?
27109 aclr0 : ((byteena_aclr_b == "CLEAR1") ?
27111 assign i_outdata_aclr_b = (outdata_aclr_b == "CLEAR0") ?
27112 aclr0 : ((outdata_aclr_b == "CLEAR1") ?
27115 assign i_byteena_a = byteena_a;
27116 assign i_byteena_b = byteena_b;
27121 // Port A inputs registered : indata, address, byeteena, wren
27122 // Aclr status flags get updated here for M-RAM ram_block_type
27124 always @(posedge clock0)
27126 if ((!i_clocken0) && (operation_mode != "ROM"))
27127 i_nmram_write_a <= 1'b0;
27129 if ((!i_clocken0) && (is_bidir_and_wrcontrol_addb_clk0))
27130 i_nmram_write_b <= 1'b0;
27137 if (i_indata_aclr_a)
27140 i_data_reg_a <= data_a;
27142 if (i_address_aclr_a)
27143 i_address_reg_a <= 0;
27144 else if (!addressstall_a)
27145 i_address_reg_a <= address_a;
27147 if (i_byteena_aclr_a)
27149 i_byteena_mask_reg_a <= ~0;
27150 i_byteena_mask_reg_a_out <= 0;
27151 i_byteena_mask_reg_a_x <= 0;
27156 if (width_byteena_a == 1)
27158 i_byteena_mask_reg_a <= {width_a{i_byteena_a[0]}};
27159 i_byteena_mask_reg_a_out <= (i_byteena_a[0])? {width_a{1'b0}} : {width_a{1'bx}};
27160 i_byteena_mask_reg_a_x <= ((i_byteena_a[0]) || (i_byteena_a[0] == 1'b0))? {width_a{1'b0}} : {width_a{1'bx}};
27163 for (k = 0; k < width_a; k = k+1)
27165 i_byteena_mask_reg_a[k] <= i_byteena_a[k/byte_size];
27166 i_byteena_mask_reg_a_out[k] <= (i_byteena_a[k/byte_size])? 1'b0: 1'bx;
27167 i_byteena_mask_reg_a_x[k] <= ((i_byteena_a[k/byte_size]) || (i_byteena_a[k/byte_size] == 1'b0))? 1'b0: 1'bx;
27172 if (i_wrcontrol_aclr_a)
27176 i_wren_reg_a <= wren_a;
27177 if (operation_mode != "ROM")
27178 i_nmram_write_a <= 1'b1;
27182 if (megaram_or_mram)
27185 i_write_flag_a <= ~ i_write_flag_a;
27190 i_read_flag_a <= ~ i_read_flag_a;
27199 if (indata_reg_b == "CLOCK0")
27201 if (i_indata_aclr_b)
27204 i_data_reg_b <= data_b;
27208 if (is_bidir_and_wrcontrol_addb_clk0)
27211 if (i_wrcontrol_aclr_b)
27215 i_wren_reg_b <= wren_b;
27216 i_nmram_write_b <= 1'b1;
27219 if (i_address_aclr_b)
27220 i_address_reg_b <= 0;
27221 else if (!addressstall_b)
27222 i_address_reg_b <= address_b;
27224 if (i_byteena_aclr_b)
27226 i_byteena_mask_reg_b <= ~0;
27227 i_byteena_mask_reg_b_out <= 0;
27228 i_byteena_mask_reg_b_x <= 0;
27233 if (width_byteena_b == 1)
27235 i_byteena_mask_reg_b <= {width_b{i_byteena_b[0]}};
27236 i_byteena_mask_reg_b_out <= (i_byteena_b[0])? {width_b{1'b0}} : {width_b{1'bx}};
27237 i_byteena_mask_reg_b_x <= ((i_byteena_b[0]) || (i_byteena_b[0] == 1'b0))? {width_b{1'b0}} : {width_b{1'bx}};
27240 for (k2 = 0; k2 < width_b; k2 = k2 + 1)
27242 i_byteena_mask_reg_b[k2] <= i_byteena_b[k2/byte_size];
27243 i_byteena_mask_reg_b_out[k2] <= (i_byteena_b[k2/byte_size])? 1'b0 : 1'bx;
27244 i_byteena_mask_reg_b_x[k2] <= ((i_byteena_b[k2/byte_size]) || (i_byteena_b[k2/byte_size] == 1'b0))? 1'b0 : 1'bx;
27250 if (megaram_or_mram)
27253 i_write_flag_b <= ~ i_write_flag_b;
27255 i_read_flag_b <= ~i_read_flag_b;
27259 else if (dual_port_addreg_b_clk0)
27261 if (i_rdcontrol_aclr_b)
27262 i_rden_reg_b <= ~0;
27264 i_rden_reg_b <= rden_b;
27266 if (i_address_aclr_b)
27267 i_address_reg_b <= 0;
27268 else if (!addressstall_b)
27269 i_address_reg_b <= address_b;
27272 i_read_flag_b <= ~i_read_flag_b;
27281 always @(negedge clock0)
27284 if (!megaram_or_mram)
27286 if (i_nmram_write_a == 1'b1)
27288 i_write_flag_a <= ~ i_write_flag_a;
27292 if (is_bidir_and_wrcontrol_addb_clk0)
27294 if (i_nmram_write_b == 1'b1)
27295 i_write_flag_b <= ~ i_write_flag_b;
27302 always @(posedge clock1)
27306 if ((!i_clocken1) && (is_bidir_and_wrcontrol_addb_clk1))
27307 i_nmram_write_b <= 1'b0;
27314 if (indata_reg_b == "CLOCK1")
27316 if (i_indata_aclr_b)
27319 i_data_reg_b <= data_b;
27323 if (is_bidir_and_wrcontrol_addb_clk1)
27325 if (i_wrcontrol_aclr_b)
27329 i_wren_reg_b <= wren_b;
27330 i_nmram_write_b <= 1'b1;
27333 if (i_address_aclr_b)
27334 i_address_reg_b <= 0;
27335 else if (!addressstall_b)
27336 i_address_reg_b <= address_b;
27338 if (i_byteena_aclr_b)
27340 i_byteena_mask_reg_b <= ~0;
27341 i_byteena_mask_reg_b_out <= 0;
27342 i_byteena_mask_reg_b_x <= 0;
27346 if (width_byteena_b == 1)
27348 i_byteena_mask_reg_b <= {width_b{i_byteena_b[0]}};
27349 i_byteena_mask_reg_b_out <= (i_byteena_b[0])? {width_b{1'b0}} : {width_b{1'bx}};
27350 i_byteena_mask_reg_b_x <= ((i_byteena_b[0]) || (i_byteena_b[0] == 1'b0))? {width_b{1'b0}} : {width_b{1'bx}};
27353 for (k2 = 0; k2 < width_b; k2 = k2 + 1)
27355 i_byteena_mask_reg_b[k2] <= i_byteena_b[k2/byte_size];
27356 i_byteena_mask_reg_b_out[k2] <= (i_byteena_b[k2/byte_size])? 1'b0 : 1'bx;
27357 i_byteena_mask_reg_b_x[k2] <= ((i_byteena_b[k2/byte_size]) || (i_byteena_b[k2/byte_size] == 1'b0))? 1'b0 : 1'bx;
27363 if (megaram_or_mram)
27366 i_write_flag_b <= ~ i_write_flag_b;
27369 i_read_flag_b <= ~i_read_flag_b;
27373 else if (dual_port_addreg_b_clk1)
27376 if (i_rdcontrol_aclr_b)
27378 i_rden_reg_b <= ~0;
27382 i_rden_reg_b <= rden_b;
27385 if (i_address_aclr_b)
27386 i_address_reg_b <= 0;
27387 else if (!addressstall_b)
27388 i_address_reg_b <= address_b;
27390 i_read_flag_b <= ~i_read_flag_b;
27397 always @(negedge clock1)
27400 if (!megaram_or_mram)
27403 if (is_bidir_and_wrcontrol_addb_clk1)
27405 if (i_nmram_write_b == 1'b1)
27406 i_write_flag_b <= ~ i_write_flag_b;
27412 // Port A writting -------------------------------------------------------------
27414 always @(posedge i_write_flag_a or negedge i_write_flag_a)
27416 if ((operation_mode == "BIDIR_DUAL_PORT") ||
27417 (operation_mode == "DUAL_PORT") ||
27418 (operation_mode == "SINGLE_PORT"))
27423 if (i_indata_aclr_a)
27425 if (i_data_reg_a != 0)
27427 mem_data[i_address_reg_a] = {width_a{1'bx}};
27431 else if (i_byteena_aclr_a)
27433 if (i_byteena_mask_reg_a != {width_a{1'b1}})
27435 mem_data[i_address_reg_a] = {width_a{1'bx}};
27439 else if (i_address_aclr_a)
27441 if (i_address_reg_a != 0)
27443 wa_mult_x_ii = {width_a{1'bx}};
27444 for (i4 = 0; i4 < i_numwords_a; i4 = i4 + 1)
27445 mem_data[i4] = wa_mult_x_ii;
27450 if (i_aclr_flag_a == 0)
27452 mem_data[i_address_reg_a] = ((i_data_reg_a & i_byteena_mask_reg_a) |
27453 (mem_data[i_address_reg_a] & ~i_byteena_mask_reg_a)) ^ i_byteena_mask_reg_a_x;
27461 end // Port A writting ----------------------------------------------------
27464 // Port B writting -----------------------------------------------------------
27466 always @(posedge i_write_flag_b or negedge i_write_flag_b)
27468 if (operation_mode == "BIDIR_DUAL_PORT")
27473 // RAM content is following width_a
27474 // if Port B is of different width, need to make some adjustments
27476 if (i_indata_aclr_b)
27478 if (i_data_reg_b != 0)
27481 if (width_a == width_b)
27482 mem_data[i_address_reg_b] = {width_b{1'bx}};
27485 j = i_address_reg_b * width_b;
27486 for (i2 = 0; i2 < width_b; i2 = i2+1)
27488 j_plus_i2 = j + i2;
27489 temp_wa = mem_data[j_plus_i2 / width_a];
27490 temp_wa[j_plus_i2 % width_a] = {1'bx};
27491 mem_data[j_plus_i2 / width_a] = temp_wa;
27497 else if (i_byteena_aclr_b)
27499 if (i_byteena_mask_reg_b != {width_b{1'b1}})
27502 if (width_a == width_b)
27503 mem_data[i_address_reg_b] = {width_b{1'bx}};
27506 j = i_address_reg_b * width_b;
27507 for (i2 = 0; i2 < width_b; i2 = i2+1)
27509 j_plus_i2 = j + i2;
27510 j_plus_i2_div_a = j_plus_i2 / width_a;
27511 temp_wa = mem_data[j_plus_i2_div_a];
27512 temp_wa[j_plus_i2 % width_a] = {1'bx};
27513 mem_data[j_plus_i2_div_a] = temp_wa;
27519 else if (i_address_aclr_b)
27521 if (i_address_reg_b != 0)
27524 wa_mult_x_iii = {width_a{1'bx}};
27525 for (i2 = 0; i2 < i_numwords_a; i2 = i2 + 1)
27527 mem_data[i2] = wa_mult_x_iii;
27533 if (i_aclr_flag_b == 0)
27536 if (width_a == width_b)
27537 mem_data[i_address_reg_b] = ((i_data_reg_b & i_byteena_mask_reg_b) |
27538 (mem_data[i_address_reg_b] & ~i_byteena_mask_reg_b)) ^ i_byteena_mask_reg_b_x;
27541 j = i_address_reg_b * width_b;
27542 for (i2 = 0; i2 < width_b; i2 = i2+1)
27544 j_plus_i2 = j + i2;
27545 j_plus_i2_div_a = j_plus_i2 / width_a;
27546 temp_wa = mem_data[j_plus_i2_div_a];
27548 temp_wa[j_plus_i2 % width_a] = ((i_data_reg_b[i2] &
27549 i_byteena_mask_reg_b[i2]) |
27550 (temp_wa[j_plus_i2 % width_a] &
27551 ~i_byteena_mask_reg_b[i2])) ^ i_byteena_mask_reg_b_x[i2];
27552 mem_data[j_plus_i2_div_a] = temp_wa;
27567 always @(posedge i_read_flag_a or negedge i_read_flag_a)
27569 if ((operation_mode == "BIDIR_DUAL_PORT") ||
27570 (operation_mode == "SINGLE_PORT") ||
27571 (operation_mode == "ROM"))
27576 if ((check_simultaneous_read_write) && (operation_mode != "ROM"))
27577 i_q_tmp2_a = {width_a{1'bx}};
27583 // read from RAM content
27584 i_q_tmp2_a = mem_data[i_address_reg_a];
27586 if (is_bidir_and_wrcontrol_addb_clk0)
27589 if (check_simultaneous_read_write)
27592 if (i_wren_reg_b & ~i_wren_reg_a)
27594 add_reg_a_mult_wa = i_address_reg_a * width_a;
27595 add_reg_b_mult_wb = i_address_reg_b * width_b;
27596 add_reg_a_mult_wa_pl_wa = add_reg_a_mult_wa + width_a;
27597 add_reg_b_mult_wb_pl_wb = add_reg_b_mult_wb + width_b;
27600 ((add_reg_a_mult_wa >=
27601 add_reg_b_mult_wb) &&
27602 (add_reg_a_mult_wa <=
27603 (add_reg_b_mult_wb_pl_wb - 1)))
27607 (((add_reg_a_mult_wa_pl_wa - 1) >=
27608 add_reg_b_mult_wb) &&
27609 ((add_reg_a_mult_wa_pl_wa - 1) <=
27610 (add_reg_b_mult_wb_pl_wb - 1)))
27612 for (i3 = add_reg_a_mult_wa;
27613 i3 < add_reg_a_mult_wa_pl_wa;
27616 if ((i3 >= add_reg_b_mult_wb) &&
27617 (i3 <= (add_reg_b_mult_wb_pl_wb - 1)))
27619 i_q_tmp2_a_idx = (i3 - add_reg_a_mult_wa);
27620 i_q_tmp2_a[i_q_tmp2_a_idx] = 1'bx;
27631 // assigning the correct output values for i_q_tmp_a (non-registered output)
27632 always @(i_q_tmp2_a or i_wren_reg_a or i_data_reg_a or
27633 i_address_reg_a or i_byteena_mask_reg_a_out)
27638 i_q_tmp_a <= i_data_reg_a ^ i_byteena_mask_reg_a_out;
27642 i_q_tmp_a <= i_q_tmp2_a;
27647 // Port A outdata output registered
27648 always @(posedge i_outdata_clk_a or posedge i_outdata_aclr_a)
27650 if (i_outdata_aclr_a)
27652 else if (i_outdata_clken_a)
27653 i_q_reg_a <= i_q_tmp_a;
27657 // Port A : assigning the correct output values for q_a
27658 assign q_a = (operation_mode == "DUAL_PORT") ?
27659 {width_a{1'b0}} : (((outdata_reg_a == "CLOCK0") ||
27660 (outdata_reg_a == "CLOCK1")) ?
27661 i_q_reg_a : i_q_tmp_a);
27665 always @(posedge i_read_flag_b or negedge i_read_flag_b)
27667 if ((operation_mode == "BIDIR_DUAL_PORT") ||
27668 (operation_mode == "DUAL_PORT"))
27673 if (check_simultaneous_read_write)
27674 i_q_tmp2_b = {width_b{1'bx}};
27682 //If width_a is equal to b, no address calculation is needed
27683 if (width_a == width_b)
27685 if (check_simultaneous_read_write)
27687 if ((rdcontrol_reg_b == "CLOCK0") ||
27688 (wrcontrol_wraddress_reg_b == "CLOCK0"))
27691 if (i_wren_reg_a & ~i_wren_reg_b)
27693 // if A write to the same Ram address B is reading from
27694 if (i_address_reg_b == i_address_reg_a)
27695 temp_wb = {width_b{1'bx}};
27697 temp_wb = mem_data[i_address_reg_b];
27701 temp_wb = mem_data[i_address_reg_b];
27704 temp_wb = mem_data[i_address_reg_b];
27707 temp_wb = mem_data[i_address_reg_b];
27712 j2 = i_address_reg_b * width_b;
27714 if (check_simultaneous_read_write)
27716 if ((rdcontrol_reg_b == "CLOCK0") ||
27717 (wrcontrol_wraddress_reg_b == "CLOCK0"))
27720 if (i_wren_reg_a & ~i_wren_reg_b)
27723 for (i5=0; i5<width_b; i5=i5+1)
27725 j2_plus_i5 = j2 + i5;
27726 j2_plus_i5_div_a = j2_plus_i5 / width_a;
27727 temp_wa2b = mem_data[j2_plus_i5_div_a];
27728 // if A write to the same Ram address B is reading from
27729 if (j2_plus_i5_div_a == i_address_reg_a)
27730 temp_wa2b = {width_a{1'bx}};
27732 temp_wb[i5] = temp_wa2b[j2_plus_i5 % width_a];
27736 for (i5=0; i5<width_b; i5=i5+1)
27738 j2_plus_i5 = j2 + i5;
27739 temp_wa2b = mem_data[j2_plus_i5 / width_a];
27740 temp_wb[i5] = temp_wa2b[j2_plus_i5 % width_a];
27744 for (i5=0; i5<width_b; i5=i5+1)
27746 j2_plus_i5 = j2 + i5;
27747 temp_wa2b = mem_data[j2_plus_i5 / width_a];
27748 temp_wb[i5] = temp_wa2b[j2_plus_i5 % width_a];
27753 for (i5=0; i5<width_b; i5=i5+1)
27755 j2_plus_i5 = j2 + i5;
27756 temp_wa2b = mem_data[j2_plus_i5 / width_a];
27757 temp_wb[i5] = temp_wa2b[j2_plus_i5 % width_a];
27762 //end of width_a != width_b
27764 i_q_tmp2_b = temp_wb;
27772 // assigning the correct output values for i_q_tmp_b (non-registered output)
27773 always @(i_q_tmp2_b or i_wren_reg_b or i_data_reg_b or
27774 i_address_reg_b or i_byteena_mask_reg_b_out or i_rden_reg_b)
27777 if (operation_mode == "BIDIR_DUAL_PORT")
27781 i_q_tmp_b <= i_data_reg_b ^ i_byteena_mask_reg_b_out;
27785 i_q_tmp_b <= i_q_tmp2_b;
27787 else if (operation_mode == "DUAL_PORT")
27790 i_q_tmp_b <= i_q_tmp2_b;
27795 // Port B outdata output registered
27796 always @(posedge i_outdata_clk_b or posedge i_outdata_aclr_b)
27798 if (i_outdata_aclr_b)
27800 else if (i_outdata_clken_b)
27801 i_q_reg_b <= i_q_tmp_b;
27805 // Port B : assigning the correct output values for q_b
27806 assign q_b = ((operation_mode == "SINGLE_PORT") ||
27807 (operation_mode == "ROM")) ?
27808 {width_b{1'b0}} : (((outdata_reg_b == "CLOCK0") ||
27809 (outdata_reg_b == "CLOCK1")) ?
27810 i_q_reg_b : i_q_tmp_b);
27812 endmodule // ALTSYNCRAM
27816 //-----------------------------------------------------------------------------+
27817 // Module Name : alt3pram
27819 // Description : Triple-Port RAM megafunction. This megafunction implements
27820 // RAM with 1 write port and 2 read ports.
27822 // Limitation : This megafunction is provided only for backward
27823 // compatibility in Stratix designs; instead, Altera®
27824 // recommends using the altsyncram megafunction.
27826 // For Apex Families,
27827 // Uses one embedded cell per data output bit for
27828 // Embedded System Block (ESB): APEX 20K, APEX II,
27829 // ARM-based Excalibur and Mercury devices or
27830 // Embedded Array Block (EAB): ACEX 1K and FLEX 10KE family;
27832 // However, in FLEX 6000, MAX 3000, and MAX 7000 devices,
27833 // or if the USE_EAB paramter is set to "OFF", uses one
27834 // logic cell (LCs) per memory bit.
27837 // Results expected : The alt3pram function represents asynchronous memory
27838 // or memory with synchronous inputs and/or outputs.
27839 // (note: ^ below indicates posedge)
27841 // [ Synchronous Write to Memory (all inputs registered) ]
27842 // inclock inclocken wren Function
27843 // X L L No change.
27844 // not ^ H H No change.
27845 // ^ L X No change.
27846 // ^ H H The memory location
27847 // pointed to by wraddress[]
27848 // is loaded with data[].
27850 // [ Synchronous Read from Memory ]
27851 // inclock inclocken rden_a/rden_b Function
27852 // X L L No change.
27853 // not ^ H H No change.
27854 // ^ L X No change.
27855 // ^ H H The q_a[]/q_b[]port
27856 // outputs the contents of
27857 // the memory location.
27859 // [ Asynchronous Memory Operations ]
27862 // H The memory location pointed to by wraddress[] is
27863 // loaded with data[] and controlled by wren.
27864 // The output q_a[] is asynchronous and reflects
27865 // the memory location pointed to by rdaddress_a[].
27867 //-----------------------------------------------------------------------------+
27869 `timescale 1 ps / 1 ps
27870 `define DEV_APEX20KE "APEX20KE"
27871 `define DEV_APEX20K "APEX20K"
27873 module alt3pram (wren, data, wraddress, inclock, inclocken,
27874 rden_a, rden_b, rdaddress_a, rdaddress_b,
27875 outclock, outclocken, aclr, qa, qb);
27877 // ---------------------
27878 // PARAMETER DECLARATION
27879 // ---------------------
27881 parameter width = 1; // data[], qa[] and qb[]
27882 parameter widthad = 1; // rdaddress_a,rdaddress_b,wraddress
27883 parameter numwords = 0; // words stored in memory
27884 parameter lpm_file = "UNUSED"; // name of hex file
27885 parameter lpm_hint = "USE_EAB=ON"; // non-LPM parameters (Altera)
27886 parameter indata_reg = "UNREGISTERED";// clock used by data[] port
27887 parameter indata_aclr = "ON"; // aclr affects data[]?
27888 parameter write_reg = "UNREGISTERED";// clock used by wraddress & wren
27889 parameter write_aclr = "ON"; // aclr affects wraddress?
27890 parameter rdaddress_reg_a = "UNREGISTERED";// clock used by readdress_a
27891 parameter rdaddress_aclr_a = "ON"; // aclr affects rdaddress_a?
27892 parameter rdcontrol_reg_a = "UNREGISTERED";// clock used by rden_a
27893 parameter rdcontrol_aclr_a = "ON"; // aclr affects rden_a?
27894 parameter rdaddress_reg_b = "UNREGISTERED";// clock used by readdress_b
27895 parameter rdaddress_aclr_b = "ON"; // aclr affects rdaddress_b?
27896 parameter rdcontrol_reg_b = "UNREGISTERED";// clock used by rden_b
27897 parameter rdcontrol_aclr_b = "ON"; // aclr affects rden_b?
27898 parameter outdata_reg_a = "UNREGISTERED";// clock used by qa[]
27899 parameter outdata_aclr_a = "ON"; // aclr affects qa[]?
27900 parameter outdata_reg_b = "UNREGISTERED";// clock used by qb[]
27901 parameter outdata_aclr_b = "ON"; // aclr affects qb[]?
27902 parameter intended_device_family = `DEV_APEX20KE;
27903 parameter ram_block_type = "AUTO"; // ram block type to be used
27904 parameter maximum_depth = 0; // maximum segmented value of the RAM
27905 parameter lpm_type = "alt3pram";
27908 // the following behaviour come in effect when RAM is implemented in EAB/ESB
27910 // This is the flag to indicate if the memory is constructed using EAB/ESB:
27911 // A write request requires both rising and falling edge of the clock
27912 // to complete. First the data will be clocked in (registered) at the
27913 // rising edge and will not be written into the ESB/EAB memory until
27914 // the falling edge appears on the the write clock.
27915 // No such restriction if the memory is constructed using LCs.
27916 parameter write_at_low_clock = ((write_reg == "INCLOCK") &&
27917 (lpm_hint == "USE_EAB=ON")) ? 1 : 0;
27919 // The read ports will not hold any value (zero) if rden is low. This
27920 // behavior only apply to memory constructed using EAB/ESB, but not LCs.
27921 parameter rden_low_output_0 = ((intended_device_family == `DEV_APEX20K) &&
27922 (lpm_hint == "USE_EAB=ON")) ? 1 : 0;
27924 // Local Parameter declaration to cater for Stratix II family specific for disabling aclr involved parameter
27925 // to be coincide with megawizard option
27926 parameter indata_aclr_int = (intended_device_family == "Stratix II") ? "OFF" : indata_aclr;
27927 parameter write_aclr_int = (intended_device_family == "Stratix II") ? "OFF" : write_aclr;
27928 parameter rdaddress_aclr_a_int = (intended_device_family == "Stratix II") ? "OFF" : rdaddress_aclr_a;
27929 parameter rdcontrol_aclr_a_int = (intended_device_family == "Stratix II") ? "OFF" : rdcontrol_aclr_a;
27930 parameter rdaddress_aclr_b_int = (intended_device_family == "Stratix II") ? "OFF" : rdaddress_aclr_b;
27931 parameter rdcontrol_aclr_b_int = (intended_device_family == "Stratix II") ? "OFF" : rdcontrol_aclr_b;
27933 // ----------------
27934 // PORT DECLARATION
27935 // ----------------
27937 // data input ports
27938 input [width-1:0] data;
27941 input [widthad-1:0] wraddress;
27942 input [widthad-1:0] rdaddress_a;
27943 input [widthad-1:0] rdaddress_b;
27953 // clock enable ports
27961 output [width-1:0] qa;
27962 output [width-1:0] qb;
27967 reg [width-1:0] mem_data [(1<<widthad)-1:0];
27968 wire [width-1:0] i_data_reg;
27969 wire [width-1:0] i_data_tmp;
27970 reg [width-1:0] i_qa_reg;
27971 reg [width-1:0] i_qa_tmp;
27972 reg [width-1:0] i_qb_reg;
27973 reg [width-1:0] i_qb_tmp;
27975 wire [width-1:0] i_qa_stratix; // qa signal for Stratix families
27976 wire [width-1:0] i_qb_stratix; // qa signal for Stratix families
27978 reg [width-1:0] i_data_hi;
27979 reg [width-1:0] i_data_lo;
27981 wire [widthad-1:0] i_wraddress_reg;
27982 wire [widthad-1:0] i_wraddress_tmp;
27984 reg [widthad-1:0] i_wraddress_hi;
27985 reg [widthad-1:0] i_wraddress_lo;
27987 reg [widthad-1:0] i_rdaddress_reg_a;
27988 reg [widthad-1:0] i_rdaddress_reg_a_dly;
27989 wire [widthad-1:0] i_rdaddress_tmp_a;
27991 reg [widthad-1:0] i_rdaddress_reg_b;
27992 reg [widthad-1:0] i_rdaddress_reg_b_dly;
27993 wire [widthad-1:0] i_rdaddress_tmp_b;
28005 reg [8*256:1] ram_initf; // max RAM size (Apex20KE) 8*256=2048
28007 wire i_stratix_inclock; // inclock signal for Stratix families
28008 wire i_stratix_outclock; // inclock signal for Stratix families
28010 wire i_apex_inclock; // inclock signal for non-Stratix families
28011 wire i_apex_outclock; // inclock signal for non-Stratix families
28013 // -------------------
28014 // INTEGER DECLARATION
28015 // -------------------
28017 integer i_numwords;
28019 integer tmp_new_data;
28022 // --------------------------------
28023 // Tri-State and Buffer DECLARATION
28024 // --------------------------------
28034 // ------------------------
28035 // COMPONENT INSTANTIATIONS
28036 // ------------------------
28037 ALTERA_DEVICE_FAMILIES dev ();
28038 ALTERA_MF_MEMORY_INITIALIZATION mem ();
28040 // The alt3pram for Stratix/Stratix II/ Stratix GX and Cyclone device families
28041 // are basically consists of 2 instances of altsyncram with write port of each
28042 // instance been tied together.
28050 .address_a(wraddress),
28051 .address_b(rdaddress_a),
28052 .clock0(i_stratix_inclock),
28053 .clock1(i_stratix_outclock),
28054 .clocken0(inclocken),
28055 .clocken1(outclocken),
28063 .q_b(i_qa_stratix));
28066 u0.width_a = width,
28067 u0.widthad_a = widthad,
28068 u0.numwords_a = (numwords == 0) ? (1<<widthad) : numwords,
28069 u0.address_aclr_a = (write_aclr_int == "ON") ? "CLEAR0" : "NONE",
28070 u0.indata_aclr_a = (indata_aclr_int == "ON") ? "CLEAR0" : "NONE",
28071 u0.wrcontrol_aclr_a = (write_aclr_int == "ON") ? "CLEAR0" : "NONE",
28073 u0.width_b = width,
28074 u0.widthad_b = widthad,
28075 u0.numwords_b = (numwords == 0) ? (1<<widthad) : numwords,
28076 u0.rdcontrol_reg_b = (rdcontrol_reg_a == "INCLOCK") ? "CLOCK0" :
28077 (rdcontrol_reg_a == "OUTCLOCK") ? "CLOCK1" :
28079 u0.address_reg_b = (rdaddress_reg_a == "INCLOCK") ? "CLOCK0" :
28080 (rdaddress_reg_a == "OUTCLOCK") ? "CLOCK1" :
28082 u0.outdata_reg_b = (outdata_reg_a == "INCLOCK") ? "CLOCK0" :
28083 (outdata_reg_a == "OUTCLOCK") ? "CLOCK1" :
28085 u0.outdata_aclr_b = (outdata_aclr_a == "ON") ? "CLEAR0" : "NONE",
28086 u0.rdcontrol_aclr_b = (rdcontrol_aclr_a_int == "ON") ? "CLEAR0" : "NONE",
28087 u0.address_aclr_b = (rdaddress_aclr_a_int == "ON") ? "CLEAR0" : "NONE",
28089 u0.operation_mode = "DUAL_PORT",
28090 u0.read_during_write_mode_mixed_ports = (ram_block_type == "AUTO") ? "OLD_DATA" :
28092 u0.ram_block_type = ram_block_type,
28093 u0.init_file = lpm_file,
28094 u0.init_file_layout = "PORT_B",
28095 u0.maximum_depth = maximum_depth,
28096 u0.intended_device_family = intended_device_family;
28104 .address_a(wraddress),
28105 .address_b(rdaddress_b),
28106 .clock0(i_stratix_inclock),
28107 .clock1(i_stratix_outclock),
28108 .clocken0(inclocken),
28109 .clocken1(outclocken),
28117 .q_b(i_qb_stratix));
28120 u1.width_a = width,
28121 u1.widthad_a = widthad,
28122 u1.numwords_a = numwords,
28123 u1.address_aclr_a = (write_aclr_int == "ON") ? "CLEAR0" : "NONE",
28124 u1.indata_aclr_a = (indata_aclr_int == "ON") ? "CLEAR0" : "NONE",
28125 u1.wrcontrol_aclr_a = (write_aclr_int == "ON") ? "CLEAR0" : "NONE",
28127 u1.width_b = width,
28128 u1.widthad_b = widthad,
28129 u1.numwords_b = numwords,
28130 u1.rdcontrol_reg_b = (rdcontrol_reg_b == "INCLOCK") ? "CLOCK0" :
28131 (rdcontrol_reg_b == "OUTCLOCK") ? "CLOCK1" :
28133 u1.address_reg_b = (rdaddress_reg_b == "INCLOCK") ? "CLOCK0" :
28134 (rdaddress_reg_b == "OUTCLOCK") ? "CLOCK1" :
28136 u1.outdata_reg_b = (outdata_reg_b == "INCLOCK") ? "CLOCK0" :
28137 (outdata_reg_b == "OUTCLOCK") ? "CLOCK1" :
28139 u1.outdata_aclr_b = (outdata_aclr_b == "ON") ? "CLEAR0" : "NONE",
28140 u1.rdcontrol_aclr_b = (rdcontrol_aclr_b_int == "ON") ? "CLEAR0" : "NONE",
28141 u1.address_aclr_b = (rdaddress_aclr_b_int == "ON") ? "CLEAR0" : "NONE",
28143 u1.operation_mode = "DUAL_PORT",
28144 u1.read_during_write_mode_mixed_ports = (ram_block_type == "AUTO") ? "OLD_DATA" :
28146 u1.ram_block_type = ram_block_type,
28147 u1.init_file = lpm_file,
28148 u1.init_file_layout = "PORT_B",
28149 u1.maximum_depth = maximum_depth,
28150 u1.intended_device_family = intended_device_family;
28152 // -----------------------------------------------------------
28153 // Initialization block for all internal signals and registers
28154 // -----------------------------------------------------------
28157 // Check for invalid parameters
28160 $display("Error: width parameter must be greater than 0.");
28166 $display("Error: widthad parameter must be greater than 0.");
28170 // Initialize mem_data to '0' if no RAM init file is specified
28171 i_numwords = (numwords) ? numwords : 1<<widthad;
28172 if (lpm_file == "UNUSED")
28173 if (write_reg == "UNREGISTERED")
28174 for (i=0; i<i_numwords; i=i+1)
28175 mem_data[i] = {width{1'bx}};
28177 for (i=0; i<i_numwords; i=i+1)
28182 $readmemh(lpm_file, mem_data);
28185 $readmemh(lpm_file, mem_data);
28187 mem.convert_hex2ver(lpm_file, width, ram_initf);
28188 $readmemh(ram_initf, mem_data);
28193 // Initialize registers
28196 i_rdaddress_reg_a = 0;
28197 i_rdaddress_reg_b = 0;
28198 i_rdaddress_reg_a_dly = 0;
28199 i_rdaddress_reg_b_dly = 0;
28203 // Initialize integer
28208 // ------------------------
28209 // ALWAYS CONSTRUCT BLOCK
28210 // ------------------------
28212 // The following always blocks are used to implement the alt3pram behavior for
28213 // device families other than Stratix/Stratix II/Stratix GX and Cyclone.
28219 // At posedge of the write clock:
28220 // All input ports values (data, address and control) are
28221 // clocked in from physical ports to internal variables
28222 // Write Cycle: i_*_hi
28223 // Read Cycle: i_*_reg
28224 always @(posedge i_apex_inclock)
28226 if (indata_reg == "INCLOCK")
28228 if ((aclr == 1) && (indata_aclr_int == "ON"))
28230 else if (inclocken == 1)
28234 if (write_reg == "INCLOCK")
28236 if ((aclr == 1) && (write_aclr_int == "ON"))
28238 i_wraddress_hi <= 0;
28241 else if (inclocken == 1)
28243 i_wraddress_hi <= wraddress;
28248 if (rdaddress_reg_a == "INCLOCK")
28250 if ((aclr == 1) && (rdaddress_aclr_a_int == "ON"))
28251 i_rdaddress_reg_a <= 0;
28252 else if (inclocken == 1)
28253 i_rdaddress_reg_a <= rdaddress_a;
28256 if (rdcontrol_reg_a == "INCLOCK")
28258 if ((aclr == 1) && (rdcontrol_aclr_a_int == "ON"))
28260 else if (inclocken == 1)
28261 i_rden_reg_a <= rden_a;
28264 if (rdaddress_reg_b == "INCLOCK")
28266 if ((aclr == 1) && (rdaddress_aclr_b_int == "ON"))
28267 i_rdaddress_reg_b <= 0;
28268 else if (inclocken == 1)
28269 i_rdaddress_reg_b <= rdaddress_b;
28272 if (rdcontrol_reg_b == "INCLOCK")
28274 if ((aclr == 1) && (rdcontrol_aclr_b_int == "ON"))
28276 else if (inclocken == 1)
28277 i_rden_reg_b <= rden_b;
28279 end // End of always block: @(posedge inclock)
28282 // At negedge of the write clock:
28283 // Write Cycle: since internally data only completed written on memory
28284 // at the falling edge of write clock, the "write" related
28285 // data, address and controls need to be shift to another
28286 // varibles (i_*_hi -> i_*_lo) during falling edge.
28287 always @(negedge i_apex_inclock)
28289 if (indata_reg == "INCLOCK")
28291 if ((aclr == 1) && (indata_aclr_int == "ON"))
28294 i_data_lo <= i_data_hi;
28297 if (write_reg == "INCLOCK")
28299 if ((aclr == 1) && (write_aclr_int == "ON"))
28301 i_wraddress_lo <= 0;
28306 i_wraddress_lo <= i_wraddress_hi;
28307 i_wren_lo <= i_wren_hi;
28310 end // End of always block: @(negedge inclock)
28313 // At posedge of read clock:
28314 // Read Cycle: This block is valid only if the operating mode is
28315 // in "Seperate Clock Mode". All read data, address
28316 // and control are clocked out from internal vars
28317 // (i_*_reg) to output port.
28318 always @(posedge i_apex_outclock)
28320 if (outdata_reg_a == "OUTCLOCK")
28322 if ((aclr == 1) && (outdata_aclr_a == "ON"))
28324 else if (outclocken == 1)
28325 i_qa_reg <= i_qa_tmp;
28328 if (outdata_reg_b == "OUTCLOCK")
28330 if ((aclr == 1) && (outdata_aclr_b == "ON"))
28332 else if (outclocken == 1)
28333 i_qb_reg <= i_qb_tmp;
28336 if (rdaddress_reg_a == "OUTCLOCK")
28338 if ((aclr == 1) && (rdaddress_aclr_a_int == "ON"))
28339 i_rdaddress_reg_a <= 0;
28340 else if (outclocken == 1)
28341 i_rdaddress_reg_a <= rdaddress_a;
28344 if (rdcontrol_reg_a == "OUTCLOCK")
28346 if ((aclr == 1) && (rdcontrol_aclr_a_int == "ON"))
28348 else if (outclocken == 1)
28349 i_rden_reg_a <= rden_a;
28352 if (rdaddress_reg_b == "OUTCLOCK")
28354 if ((aclr == 1) && (rdaddress_aclr_b_int == "ON"))
28355 i_rdaddress_reg_b <= 0;
28356 else if (outclocken == 1)
28357 i_rdaddress_reg_b <= rdaddress_b;
28360 if (rdcontrol_reg_b == "OUTCLOCK")
28362 if ((aclr == 1) && (rdcontrol_aclr_b_int == "ON"))
28364 else if (outclocken == 1)
28365 i_rden_reg_b <= rden_b;
28367 end // End of always block: @(posedge outclock)
28369 always @(i_rdaddress_reg_a)
28371 i_rdaddress_reg_a_dly <= i_rdaddress_reg_a;
28374 always @(i_rdaddress_reg_b)
28376 i_rdaddress_reg_b_dly <= i_rdaddress_reg_b;
28383 always @(i_data_tmp or i_wren_tmp or i_wraddress_tmp)
28388 always @(posedge new_data or negedge new_data)
28393 // This is where data is being write to the internal memory: mem_data[]
28395 if (i_wren_tmp == 1)
28397 mem_data[i_wraddress_tmp] <= i_data_tmp;
28400 tmp_new_data <= ~tmp_new_data;
28405 always @(tmp_new_data)
28411 // Triple-Port Ram (alt3pram) has one write port and two read ports (a and b)
28412 // Below is the operation to read data from internal memory (mem_data[])
28413 // to the output port (i_qa_tmp or i_qb_tmp)
28414 // Note: i_q*_tmp will serve as the var directly link to the physical
28415 // output port q* if alt3pram is operate in "Shared Clock Mode",
28416 // else data read from i_q*_tmp will need to be latched to i_q*_reg
28417 // through outclock before it is fed to the output port q* (qa or qb).
28419 always @(posedge new_data or negedge new_data or
28420 posedge i_rden_tmp_a or negedge i_rden_tmp_a or
28424 if (i_rden_tmp_a == 1)
28425 i_qa_tmp <= mem_data[i_rdaddress_tmp_a];
28426 else if (rden_low_output_0 == 1)
28431 always @(posedge new_data or negedge new_data or
28432 posedge i_rden_tmp_b or negedge i_rden_tmp_b or
28436 if (i_rden_tmp_b == 1)
28437 i_qb_tmp <= mem_data[i_rdaddress_tmp_b];
28438 else if (rden_low_output_0 == 1)
28448 assign i_wraddress_reg = ((aclr == 1) && (write_aclr_int == "ON")) ?
28449 0 : (write_at_low_clock ?
28450 i_wraddress_lo : i_wraddress_hi);
28452 assign i_wren_reg = ((aclr == 1) && (write_aclr_int == "ON")) ?
28453 0 : ((write_at_low_clock) ?
28454 i_wren_lo : i_wren_hi);
28456 assign i_data_reg = ((aclr == 1) && (indata_aclr_int == "ON")) ?
28457 0 : ((write_at_low_clock) ?
28458 i_data_lo : i_data_hi);
28460 assign i_wraddress_tmp = ((aclr == 1) && (write_aclr_int == "ON")) ?
28461 0 : ((write_reg == "INCLOCK") ?
28462 i_wraddress_reg : wraddress);
28464 assign i_rdaddress_tmp_a = ((aclr == 1) && (rdaddress_aclr_a_int == "ON")) ?
28465 0 : (((rdaddress_reg_a == "INCLOCK") ||
28466 (rdaddress_reg_a == "OUTCLOCK")) ?
28467 i_rdaddress_reg_a_dly : rdaddress_a);
28469 assign i_rdaddress_tmp_b = ((aclr == 1) && (rdaddress_aclr_b_int == "ON")) ?
28470 0 : (((rdaddress_reg_b == "INCLOCK") ||
28471 (rdaddress_reg_b == "OUTCLOCK")) ?
28472 i_rdaddress_reg_b_dly : rdaddress_b);
28474 assign i_wren_tmp = ((aclr == 1) && (write_aclr_int == "ON")) ?
28475 0 : ((write_reg == "INCLOCK") ?
28476 i_wren_reg : wren);
28478 assign i_rden_tmp_a = ((aclr == 1) && (rdcontrol_aclr_a_int == "ON")) ?
28479 0 : (((rdcontrol_reg_a == "INCLOCK") ||
28480 (rdcontrol_reg_a == "OUTCLOCK")) ?
28481 i_rden_reg_a : rden_a);
28483 assign i_rden_tmp_b = ((aclr == 1) && (rdcontrol_aclr_b_int == "ON")) ?
28484 0 : (((rdcontrol_reg_b == "INCLOCK") ||
28485 (rdcontrol_reg_b == "OUTCLOCK")) ?
28486 i_rden_reg_b : rden_b);
28488 assign i_data_tmp = ((aclr == 1) && (indata_aclr_int == "ON")) ?
28489 0 : ((indata_reg == "INCLOCK") ?
28490 i_data_reg : data);
28492 assign qa = ((dev.IS_FAMILY_STRATIX(intended_device_family) == 1) ||
28493 (dev.IS_FAMILY_STRATIXII(intended_device_family) == 1) ||
28494 (dev.IS_FAMILY_STRATIXGX(intended_device_family) == 1) ||
28495 (dev.IS_FAMILY_CYCLONE(intended_device_family) == 1)) ?
28497 (((aclr == 1) && (outdata_aclr_a == "ON")) ?
28498 0 : ((outdata_reg_a == "OUTCLOCK") ?
28499 i_qa_reg : i_qa_tmp));
28501 assign qb = ((dev.IS_FAMILY_STRATIX(intended_device_family) == 1) ||
28502 (dev.IS_FAMILY_STRATIXII(intended_device_family) == 1) ||
28503 (dev.IS_FAMILY_STRATIXGX(intended_device_family) == 1) ||
28504 (dev.IS_FAMILY_CYCLONE(intended_device_family) == 1)) ?
28506 (((aclr == 1) && (outdata_aclr_b == "ON")) ?
28507 0 : ((outdata_reg_b == "OUTCLOCK") ?
28508 i_qb_reg : i_qb_tmp));
28510 assign i_apex_inclock = ((dev.IS_FAMILY_STRATIX(intended_device_family) == 0) &&
28511 (dev.IS_FAMILY_STRATIXII(intended_device_family) == 0) &&
28512 (dev.IS_FAMILY_STRATIXGX(intended_device_family) == 0) &&
28513 (dev.IS_FAMILY_CYCLONE(intended_device_family) == 0)) ?
28516 assign i_apex_outclock = ((dev.IS_FAMILY_STRATIX(intended_device_family) == 0) &&
28517 (dev.IS_FAMILY_STRATIXII(intended_device_family) == 0) &&
28518 (dev.IS_FAMILY_STRATIXGX(intended_device_family) == 0) &&
28519 (dev.IS_FAMILY_CYCLONE(intended_device_family) == 0)) ?
28522 assign i_stratix_inclock = ((dev.IS_FAMILY_STRATIX(intended_device_family) == 1) ||
28523 (dev.IS_FAMILY_STRATIXII(intended_device_family) == 1) ||
28524 (dev.IS_FAMILY_STRATIXGX(intended_device_family) == 1) ||
28525 (dev.IS_FAMILY_CYCLONE(intended_device_family) == 1)) ?
28528 assign i_stratix_outclock = ((dev.IS_FAMILY_STRATIX(intended_device_family) == 1) ||
28529 (dev.IS_FAMILY_STRATIXII(intended_device_family) == 1) ||
28530 (dev.IS_FAMILY_STRATIXGX(intended_device_family) == 1) ||
28531 (dev.IS_FAMILY_CYCLONE(intended_device_family) == 1)) ?
28535 endmodule // end of ALT3PRAM
28537 // START_MODULE_NAME------------------------------------------------------------
28539 // Module Name : ALTQPRAM
28541 // Description : Asynchronous quad ports memory or memory with synchronous
28542 // inputs and/or outputs
28546 // Results expected : [Synchronous Write to Memory (all inputs registered)]
28547 // inclock inclocken wren Function
28549 // not H H No change
28550 // posedge L X No change
28551 // posedge H H Memory content updated
28553 // [Synchronous Read from Memory]
28554 // inclock inclocken rden Function
28556 // not H H No change
28557 // posedge L X No change.
28558 // posedge H H Memory content showed
28559 // at the output port
28561 // [Asynchronous Memory Operations]
28564 // H Memory content updated
28565 // Memory content showed
28566 // at the output port
28568 // END_MODULE_NAME--------------------------------------------------------------
28570 `timescale 1 ps / 1 ps
28572 // BEGINNING OF MODULE
28574 // MODULE DECLARATION
28603 // GLOBAL PARAMETER DECLARATION
28605 parameter operation_mode = "QUAD_PORT";
28607 // Port A write parameters
28608 parameter width_write_a = 1;
28609 parameter widthad_write_a = 1;
28610 parameter numwords_write_a = 0;
28611 parameter indata_reg_a = "INCLOCK_A";
28612 parameter indata_aclr_a = "INACLR_A";
28613 parameter wrcontrol_wraddress_reg_a = "INCLOCK_A";
28614 parameter wrcontrol_aclr_a = "INACLR_A";
28615 parameter wraddress_aclr_a = "INACLR_A";
28617 // Port B write parameters
28618 parameter width_write_b = 1;
28619 parameter widthad_write_b = 1;
28620 parameter numwords_write_b = 0;
28621 parameter indata_reg_b = "INCLOCK_B";
28622 parameter indata_aclr_b = "INACLR_B";
28623 parameter wrcontrol_wraddress_reg_b = "INCLOCK_B";
28624 parameter wrcontrol_aclr_b = "INACLR_B";
28625 parameter wraddress_aclr_b = "INACLR_B";
28627 // Port A read parameters
28628 parameter width_read_a = 1;
28629 parameter widthad_read_a = 1;
28630 parameter numwords_read_a = 0;
28631 parameter rdcontrol_reg_a = "OUTCLOCK_A";
28632 parameter rdcontrol_aclr_a = "OUTACLR_A";
28633 parameter rdaddress_reg_a = "OUTCLOCK_A";
28634 parameter rdaddress_aclr_a = "OUTACLR_A";
28635 parameter outdata_reg_a = "UNREGISTERED";
28636 parameter outdata_aclr_a = "OUTACLR_A";
28638 // Port B read parameters
28639 parameter width_read_b = 1;
28640 parameter widthad_read_b = 1;
28641 parameter numwords_read_b = 0;
28642 parameter rdcontrol_reg_b = "OUTCLOCK_B";
28643 parameter rdcontrol_aclr_b = "OUTACLR_B";
28644 parameter rdaddress_reg_b = "OUTCLOCK_B";
28645 parameter rdaddress_aclr_b = "OUTACLR_B";
28646 parameter outdata_reg_b = "UNREGISTERED";
28647 parameter outdata_aclr_b = "OUTACLR_B";
28649 parameter init_file = "UNUSED";
28650 parameter lpm_hint = "UNUSED";
28651 parameter lpm_type = "altqpram";
28653 // INPUT PORT DECLARATION
28659 input [width_write_a - 1 : 0] data_a;
28660 input [width_write_b - 1 : 0] data_b;
28661 input [widthad_write_a - 1 : 0] wraddress_a;
28662 input [widthad_write_b - 1 : 0] wraddress_b;
28667 input [widthad_read_a - 1 : 0] rdaddress_a;
28668 input [widthad_read_b - 1 : 0] rdaddress_b;
28671 input outclocken_a;
28672 input outclocken_b;
28678 // OUTPUT PORT DECLARATION
28680 output [width_read_a - 1 : 0] q_a;
28681 output [width_read_b - 1 : 0] q_b;
28683 // INTERNAL REGISTERS DECLARATION
28685 reg [width_read_a - 1 : 0] mem_data [0 : (1 << widthad_read_a) - 1];
28686 reg [width_write_a - 1 : 0] mem_data_w [0 : (1 << widthad_write_a) - 1];
28687 reg [width_write_a - 1 : 0] i_data_reg_a;
28688 reg [width_write_a - 1 : 0] i_data_tmp_a;
28689 reg [width_write_a - 1 : 0] i_data2_a;
28690 reg [width_write_a - 1 : 0] temp_wa;
28691 reg [width_write_a - 1 : 0] temp_wa2;
28692 reg [width_write_a - 1 : 0] temp_wa3;
28693 reg [width_write_b - 1 : 0] i_data_reg_b;
28694 reg [width_write_b - 1 : 0] i_data_tmp_b;
28695 reg [width_write_b - 1 : 0] i_data2_b;
28696 reg [width_write_a - 1 : 0] i_data_hi_a;
28697 reg [width_write_a - 1 : 0] i_data_lo_a;
28698 reg [width_write_b - 1 : 0] i_data_hi_b;
28699 reg [width_write_b - 1 : 0] i_data_lo_b;
28700 reg [width_read_a - 1 : 0] i_q_reg_a;
28701 reg [width_read_a - 1 : 0] i_q_tmp_a;
28702 reg [width_read_a - 1 : 0] temp_ra;
28703 reg [width_read_a - 1 : 0] temp_ra2;
28704 reg [width_read_a - 1 : 0] temp_ra3;
28705 reg [width_read_a - 1 : 0] temp_ra4;
28706 reg [width_read_b - 1 : 0] i_q_reg_b;
28707 reg [width_read_b - 1 : 0] i_q_tmp_b;
28708 reg [widthad_write_a - 1 : 0] i_wraddress_reg_a;
28709 reg [widthad_write_a - 1 : 0] i_wraddress_tmp_a;
28710 reg [widthad_write_a - 1 : 0] i_wraddress2_a;
28711 reg [widthad_write_b - 1 : 0] i_wraddress_reg_b;
28712 reg [widthad_write_b - 1 : 0] i_wraddress_tmp_b;
28713 reg [widthad_write_b - 1 : 0] i_wraddress2_b;
28714 reg [widthad_write_a - 1 : 0] i_wraddress_hi_a;
28715 reg [widthad_write_a - 1 : 0] i_wraddress_lo_a;
28716 reg [widthad_write_b - 1 : 0] i_wraddress_hi_b;
28717 reg [widthad_write_b - 1 : 0] i_wraddress_lo_b;
28718 reg [widthad_read_a - 1 : 0] i_rdaddress_reg_a;
28719 reg [widthad_read_a - 1 : 0] i_rdaddress_tmp_a;
28720 reg [widthad_read_b - 1 : 0] i_rdaddress_reg_b;
28721 reg [widthad_read_b - 1 : 0] i_rdaddress_tmp_b;
28722 reg [8*256 : 1] ram_initf;
28740 reg write_at_low_clock_a;
28741 reg write_at_low_clock_b;
28744 wire i_indata_aclr_a;
28745 wire i_wraddress_aclr_a;
28746 wire i_wrcontrol_aclr_a;
28747 wire i_outdata_aclr_a;
28748 wire i_rdaddress_aclr_a;
28749 wire i_rdcontrol_aclr_a;
28750 wire i_indata_aclr_b;
28751 wire i_wraddress_aclr_b;
28752 wire i_wrcontrol_aclr_b;
28753 wire i_outdata_aclr_b;
28754 wire i_rdaddress_aclr_b;
28755 wire i_rdcontrol_aclr_b;
28758 // LOCAL INTEGER DECLARATION
28760 integer i_numwords_read_a;
28761 integer i_numwords_read_b;
28762 integer i_numwords_write_a;
28763 integer i_numwords_write_b;
28764 integer write_ratio;
28765 integer read_ratio;
28766 integer read_write_ratio;
28785 integer simultaneous_write;
28787 // INTERNAL TRI DECLARATION
28814 wire i_inclocken_a;
28815 wire i_inclocken_b;
28818 wire i_outclocken_a;
28819 wire i_outclocken_b;
28827 buf (i_wren_a, wren_a);
28828 buf (i_wren_b, wren_b);
28829 buf (i_rden_a, rden_a);
28830 buf (i_rden_b, rden_b);
28831 buf (i_inclock_a, inclock_a);
28832 buf (i_inclock_b, inclock_b);
28833 buf (i_inclocken_a, inclocken_a);
28834 buf (i_inclocken_b, inclocken_b);
28835 buf (i_outclock_a, outclock_a);
28836 buf (i_outclock_b, outclock_b);
28837 buf (i_outclocken_a, outclocken_a);
28838 buf (i_outclocken_b, outclocken_b);
28839 buf (i_inaclr_a, inaclr_a);
28840 buf (i_inaclr_b, inaclr_b);
28841 buf (i_outaclr_a, outaclr_a);
28842 buf (i_outaclr_b, outaclr_b);
28845 // COMPONENT INSTANTIATIONS
28846 ALTERA_MF_MEMORY_INITIALIZATION mem ();
28848 // INITIAL CONSTRUCT BLOCK
28853 // Check for invalid parameters
28855 if ((operation_mode != "QUAD_PORT") && (operation_mode != "BIDIR_DUAL_PORT") &&
28856 (operation_mode != "DUAL_PORT") && (operation_mode != "SINGLE_PORT") &&
28857 (operation_mode != "ROM"))
28859 $display("Error! operation_mode parameter is invalid.");
28863 if ((width_write_a <= 0) && (operation_mode != "ROM"))
28865 $display("Error! width_write_a parameter must be greater than 0.");
28869 if ((width_write_b <= 0) && ((operation_mode == "QUAD_PORT") || (operation_mode == "BIDIR_DUAL_PORT")))
28871 $display("Error! width_write_b parameter must be greater than 0.");
28875 if ((widthad_write_a <= 0) && (operation_mode != "ROM"))
28877 $display("Error! widthad_write_a parameter must be greater than 0.");
28881 if ((widthad_write_b <= 0) && ((operation_mode == "QUAD_PORT") || (operation_mode == "BIDIR_DUAL_PORT")))
28883 $display("Error! widthad_write_b parameter must be greater than 0.");
28887 if ((width_read_a <= 0) && ((operation_mode == "QUAD_PORT") || (operation_mode == "DUAL_PORT")))
28889 $display("Error! width_read_a parameter must be greater than 0.");
28893 if ((width_read_b <= 0) && (operation_mode == "QUAD_PORT"))
28895 $display("Error! width_read_b parameter must be greater than 0.");
28899 if ((widthad_read_a <= 0) && ((operation_mode == "QUAD_PORT") || (operation_mode == "DUAL_PORT")))
28901 $display("Error! widthad_read_a parameter must be greater than 0.");
28905 if ((widthad_read_b <= 0) && (operation_mode == "QUAD_PORT"))
28907 $display("Error! widthad_read_b parameter must be greater than 0.");
28911 if (((operation_mode == "BIDIR_DUAL_PORT") || (operation_mode == "SINGLE_PORT")) && (width_read_a != width_write_a))
28913 $display("Error! width_read_a must equal width_write_a.");
28917 if ((operation_mode == "BIDIR_DUAL_PORT") && (width_read_b != width_write_b))
28919 $display("Error! width_read_b must equal width_write_b.");
28923 i_numwords_read_a = (numwords_read_a) ? numwords_read_a : (1 << widthad_read_a);
28924 i_numwords_read_b = (numwords_read_b) ? numwords_read_b : (1 << widthad_read_b);
28925 i_numwords_write_a =(numwords_write_a) ?
28926 numwords_write_a : (1 << widthad_write_a);
28927 i_numwords_write_b =(numwords_write_b) ?
28928 numwords_write_b : (1 << widthad_write_b);
28930 if ((width_read_a*i_numwords_read_a != width_write_a*i_numwords_write_a) &&
28931 ((operation_mode == "QUAD_PORT") || (operation_mode == "DUAL_PORT")))
28933 $display("Error! RAM size for port A is inconsistant.");
28937 if ((operation_mode == "QUAD_PORT") || (operation_mode == "BIDIR_DUAL_PORT"))
28939 if ((width_read_b * i_numwords_read_b) != (width_write_b * i_numwords_write_b))
28941 $display("Error! RAM size for port B is inconsistant.");
28945 if (width_read_a*i_numwords_read_a != width_read_b*i_numwords_read_b)
28947 $display("Error! RAM size between port A and port B is inconsistant.");
28952 read_ratio = (width_read_a > width_read_b) ?
28953 (width_read_a / width_read_b)
28954 : (width_read_b / width_read_a);
28955 write_ratio = (width_write_a > width_write_b) ?
28956 (width_write_a / width_write_b)
28957 : (width_write_b / width_write_a);
28958 read_write_ratio = (width_read_a > width_write_a) ?
28959 (width_read_a / width_write_a)
28960 : (width_write_a / width_read_a);
28962 // reset unused ratios to avoid incorrect checking
28963 if ((operation_mode != "QUAD_PORT") || (operation_mode != "BIDIR_DUAL_MODE"))
28969 if (((read_ratio != 1) && (read_ratio != 2) && (read_ratio != 4) &&
28970 (read_ratio != 8) && (read_ratio != 16)) ||
28971 ((write_ratio != 1) && (write_ratio != 2) && (write_ratio != 4) &&
28972 (write_ratio != 8) && (write_ratio != 16)) ||
28973 ((read_write_ratio != 1) && (read_write_ratio != 2) &&
28974 (read_write_ratio != 4) && (read_write_ratio != 8) &&
28975 (read_write_ratio != 16)))
28977 $display("Error! RAM size for port A and / or port B is invalid.");
28981 // Initialize mem_data
28982 if ((init_file == "UNUSED") || (init_file == ""))
28984 if (operation_mode == "ROM")
28986 $display("Error! altqpram needs data file for memory initialization.\n");
28989 else if ((operation_mode == "BIDIR_DUAL_PORT") || (operation_mode == "SINGLE_PORT"))
28990 for (i = 0; i < i_numwords_write_a; i = i + 1)
28992 else // if QP or DP mode
28993 for (i = 0; i < i_numwords_read_a; i = i + 1)
28998 if ((operation_mode == "BIDIR_DUAL_PORT") || (operation_mode == "SINGLE_PORT"))
29001 $readmemh(init_file, mem_data_w);
29004 $readmemh(init_file, mem_data_w);
29006 mem.convert_hex2ver(init_file, width_write_a, ram_initf);
29007 $readmemh(ram_initf, mem_data_w);
29011 else // if ROM, QP or DP mode
29014 $readmemh(init_file, mem_data);
29017 $readmemh(init_file, mem_data);
29019 mem.convert_hex2ver(init_file, width_read_a, ram_initf);
29020 $readmemh(ram_initf, mem_data);
29027 write_at_low_clock_a <= (wrcontrol_wraddress_reg_a != "UNREGISTERED") ?
29029 write_at_low_clock_b <= (wrcontrol_wraddress_reg_b != "UNREGISTERED") ?
29032 // Initialize registers
29041 i_wraddress_reg_a <= 0;
29042 i_wraddress_tmp_a <= 0;
29043 i_wraddress_reg_b <= 0;
29044 i_wraddress_tmp_b <= 0;
29045 i_wraddress_reg_b <= 0;
29046 i_wraddress_tmp_b <= 0;
29047 i_wraddress_hi_a <= 0;
29048 i_wraddress_lo_a <= 0;
29049 i_wraddress_hi_b <= 0;
29050 i_wraddress_lo_b <= 0;
29051 i_rdaddress_reg_a <= 0;
29052 i_rdaddress_tmp_a <= 0;
29053 i_rdaddress_reg_b <= 0;
29054 i_rdaddress_tmp_b <= 0;
29074 i_wraddress2_a <= 0;
29077 i_wraddress2_b <= 0;
29078 clk_a_trigger <= 0;
29079 clk_b_trigger <= 0;
29083 assign i_indata_aclr_a = (indata_aclr_a == "INACLR_A") ?
29086 assign i_wraddress_aclr_a = (wraddress_aclr_a == "INACLR_A") ?
29089 assign i_wrcontrol_aclr_a = (wrcontrol_aclr_a == "INACLR_A") ?
29092 assign i_outdata_aclr_a = ((outdata_aclr_a == "INACLR_A") ? i_inaclr_a :
29093 ((outdata_aclr_a == "OUTACLR_A") ? i_outaclr_a : 0));
29095 assign i_rdaddress_aclr_a = ((rdaddress_aclr_a == "INACLR_A") ? i_inaclr_a :
29096 ((rdaddress_aclr_a == "OUTACLR_A") ? i_outaclr_a : 0));
29098 assign i_rdcontrol_aclr_a = ((rdcontrol_aclr_a == "INACLR_A") ? i_inaclr_a :
29099 ((rdcontrol_aclr_a == "OUTACLR_A") ? i_outaclr_a : 0));
29101 assign i_indata_aclr_b = (indata_aclr_b == "INACLR_B") ?
29104 assign i_wraddress_aclr_b = (wraddress_aclr_b == "INACLR_B") ?
29107 assign i_wrcontrol_aclr_b = (wrcontrol_aclr_b == "INACLR_B") ?
29110 assign i_outdata_aclr_b = ((outdata_aclr_b == "INACLR_B") ? i_inaclr_b :
29111 ((outdata_aclr_b == "OUTACLR_B") ? i_outaclr_b : 0));
29113 assign i_rdaddress_aclr_b = ((rdaddress_aclr_b == "INACLR_B") ? i_inaclr_b :
29114 ((rdaddress_aclr_b == "OUTACLR_B") ? i_outaclr_b : 0));
29116 assign i_rdcontrol_aclr_b = ((rdcontrol_aclr_b == "INACLR_B") ? i_inaclr_b :
29117 ((rdcontrol_aclr_b == "OUTACLR_B") ? i_outaclr_b : 0));
29121 // This always block is to handle registered inputs and output for port A
29122 always @(posedge i_inclock_a)
29124 if (i_indata_aclr_a === 1)
29126 else if (i_inclocken_a == 1)
29127 i_data_hi_a <= data_a;
29129 if (i_wraddress_aclr_a === 1)
29130 i_wraddress_hi_a <= 0;
29131 else if (i_inclocken_a == 1)
29132 i_wraddress_hi_a <= wraddress_a;
29134 if (i_wrcontrol_aclr_a === 1)
29136 else if (i_inclocken_a == 1)
29137 i_wren_hi_a <= i_wren_a;
29139 if (outdata_reg_a == "INCLOCK_A")
29141 if (i_outdata_aclr_a === 1)
29143 else if (i_inclocken_a == 1)
29144 i_q_reg_a <= i_q_tmp_a;
29147 if (rdaddress_reg_a == "INCLOCK_A")
29149 if (i_rdaddress_aclr_a === 1)
29150 i_rdaddress_reg_a <= 0;
29151 else if (i_inclocken_a == 1)
29152 i_rdaddress_reg_a <= rdaddress_a;
29155 if (rdcontrol_reg_a == "INCLOCK_A")
29157 if (i_rdcontrol_aclr_a === 1)
29159 else if (i_inclocken_a == 1)
29160 i_rden_reg_a <= i_rden_a;
29164 // This always block is to handle registered inputs and output for port B
29165 always @(posedge i_inclock_b)
29167 if (i_indata_aclr_b === 1)
29169 else if (i_inclocken_b == 1)
29170 i_data_hi_b <= data_b;
29172 if (i_wraddress_aclr_b === 1)
29173 i_wraddress_hi_b <= 0;
29174 else if (i_inclocken_b == 1)
29175 i_wraddress_hi_b <= wraddress_b;
29177 if (i_wrcontrol_aclr_b === 1)
29179 else if (i_inclocken_b == 1)
29180 i_wren_hi_b <= i_wren_b;
29182 if (outdata_reg_b == "INCLOCK_B")
29184 if (i_outdata_aclr_b === 1)
29186 else if (i_inclocken_b == 1)
29187 i_q_reg_b <= i_q_tmp_b;
29190 if (rdaddress_reg_b == "INCLOCK_B")
29192 if (i_rdaddress_aclr_b === 1)
29193 i_rdaddress_reg_b <= 0;
29194 else if (i_inclocken_b == 1)
29195 i_rdaddress_reg_b <= rdaddress_b;
29198 if (rdcontrol_reg_b == "INCLOCK_B")
29200 if (i_rdcontrol_aclr_b === 1)
29202 else if (i_inclocken_b == 1)
29203 i_rden_reg_b <= i_rden_b;
29208 // This always block is to handle registered inputs for port A
29209 // for negative clock edge
29210 always @(negedge i_inclock_a)
29212 if (i_indata_aclr_a)
29215 i_data_lo_a <= i_data_hi_a;
29217 if (i_wraddress_aclr_a)
29218 i_wraddress_lo_a <= 0;
29220 i_wraddress_lo_a <= i_wraddress_hi_a;
29222 if (i_wrcontrol_aclr_a)
29225 i_wren_lo_a <= i_wren_hi_a;
29227 clk_a_trigger <= 1;
29231 // This process is to handle registered inputs for port B
29232 // for negative clock edge
29233 always @(negedge i_inclock_b)
29235 if (i_indata_aclr_b)
29238 i_data_lo_b <= i_data_hi_b;
29240 if (i_wraddress_aclr_b)
29241 i_wraddress_lo_b <= 0;
29243 i_wraddress_lo_b <= i_wraddress_hi_b;
29245 if (i_wrcontrol_aclr_b)
29248 i_wren_lo_b <= i_wren_hi_b;
29250 clk_b_trigger <= 1;
29254 // This process is to handle registered outputs for port A
29255 always @(posedge i_outclock_a)
29257 if (outdata_reg_a == "OUTCLOCK_A")
29259 if (i_outdata_aclr_a)
29261 else if (i_outclocken_a == 1)
29262 i_q_reg_a <= i_q_tmp_a;
29265 if (rdaddress_reg_a == "OUTCLOCK_A")
29267 if (i_rdaddress_aclr_a)
29268 i_rdaddress_reg_a <= 0;
29269 else if (i_outclocken_a == 1)
29270 i_rdaddress_reg_a <= rdaddress_a;
29273 if (rdcontrol_reg_a == "OUTCLOCK_A")
29275 if (i_rdcontrol_aclr_a)
29277 else if (i_outclocken_a == 1)
29278 i_rden_reg_a <= i_rden_a;
29283 // This process is to handle registered outputs for port B
29284 always @(posedge i_outclock_b)
29286 if (outdata_reg_b == "OUTCLOCK_B")
29288 if (i_outdata_aclr_b)
29290 else if (i_outclocken_b == 1)
29291 i_q_reg_b <= i_q_tmp_b;
29294 if (rdaddress_reg_b == "OUTCLOCK_B")
29296 if (i_rdaddress_aclr_b)
29297 i_rdaddress_reg_b <= 0;
29298 else if (i_outclocken_b == 1)
29299 i_rdaddress_reg_b <= rdaddress_b;
29302 if (rdcontrol_reg_b == "OUTCLOCK_B")
29304 if (i_rdcontrol_aclr_b)
29306 else if (i_outclocken_b == 1)
29307 i_rden_reg_b <= i_rden_b;
29312 // This always block is to update the memory contents with 'X' when both ports intend to
29313 // write at the same location
29314 always @(i_data_tmp_a or i_wren_tmp_a or i_wraddress_tmp_a or i_data_tmp_b or
29315 i_wren_tmp_b or i_wraddress_tmp_b or write_at_low_clock_a or write_at_low_clock_b or
29316 i_inclock_a or i_inclock_b)
29319 if ((write_at_low_clock_a ==1) && (write_at_low_clock_b == 1))
29321 if ((clk_a_trigger ==1) && (clk_b_trigger ==1))
29322 simultaneous_write = 1;
29324 simultaneous_write = 0;
29327 simultaneous_write = 1;
29329 if ((i_wren_tmp_a == 1) && (i_wren_tmp_b == 1 ) &&
29330 (i_inclock_a == 0 ) && (i_inclock_b == 0 ) &&
29331 (simultaneous_write == 1) &&
29332 ((operation_mode == "QUAD_PORT") || (operation_mode == "BIDIR_DUAL_PORT")))
29334 simultaneous_write = 0;
29336 if (operation_mode == "BIDIR_DUAL_PORT")
29338 for (jb = 0; jb < width_write_b; jb = jb + 1)
29340 Pa = ((i_wraddress_tmp_a * width_write_a) + jb) % width_write_a;
29341 Pb = ((i_wraddress_tmp_b * width_write_b) + jb) / width_write_a;
29343 if ((i_wraddress_tmp_a == Pb) && (Pa < width_write_a))
29345 temp_wa3 = mem_data_w[i_wraddress_tmp_a];
29346 temp_wa3[Pa] = 1'bx;
29347 mem_data_w[i_wraddress_tmp_a] = temp_wa3;
29348 simultaneous_write = 1;
29354 for (ja = 0; ja < width_write_a; ja = ja + 1)
29356 for (jb = 0; jb < width_write_b; jb = jb + 1)
29358 Pa1 = ((i_wraddress_tmp_a * width_write_a) + ja) / width_read_a;
29359 Pa2 = ((i_wraddress_tmp_a * width_write_a) + ja) % width_read_a;
29360 Pb1 = ((i_wraddress_tmp_b * width_write_b) + jb) / width_read_a;
29361 Pb2 = ((i_wraddress_tmp_b * width_write_b) + jb) % width_read_a;
29363 if ((Pa1 == Pb1) && (Pa2 == Pb2))
29365 temp_ra4 = mem_data[Pa1];
29366 temp_ra4[Pa2] = 1'b X;
29367 mem_data[Pa1] = temp_ra4;
29368 simultaneous_write = 1;
29375 simultaneous_write = 0;
29377 if (simultaneous_write == 1)
29378 mem_updated = ~mem_updated;
29381 i_data2_a = i_data_tmp_a;
29382 i_wren2_a = i_wren_tmp_a;
29383 i_wraddress2_a = i_wraddress_tmp_a;
29384 i_data2_b = i_data_tmp_b;
29385 i_wren2_b = i_wren_tmp_b;
29386 i_wraddress2_b = i_wraddress_tmp_b;
29394 // This always block is to update the memory contents by port A
29395 always @(i_data2_a or i_wren2_a or i_wraddress2_a or i_wraddress_lo_a or i_wren_lo_a or i_inclock_a)
29397 j4 = i_wraddress2_a * width_write_a;
29399 if ((i_wren2_a == 1) && (i_inclock_a == 0) &&
29400 (operation_mode != "ROM"))
29402 if ((operation_mode == "BIDIR_DUAL_PORT") || (operation_mode == "SINGLE_PORT"))
29403 mem_data_w[i_wraddress2_a] = i_data2_a;
29404 else // QP or DP mode
29405 for (i4 = 0; i4 < width_write_a; i4 = i4 + 1)
29407 temp_ra3 = mem_data[(j4+i4)/width_read_a];
29408 temp_ra3[(j4+i4)%width_read_a] = i_data2_a[i4];
29409 mem_data[(j4+i4)/width_read_a] = temp_ra3;
29412 mem_updated = ~mem_updated;
29417 // This always block is to update the memory contents by port B
29418 always @(i_data2_b or i_wren2_b or i_wraddress2_b or i_wraddress_lo_b or i_wren_lo_b or i_inclock_b)
29420 j3 = i_wraddress2_b * width_write_b;
29422 if ((i_wren2_b == 1) && (i_inclock_b == 0) &&
29423 ((operation_mode == "BIDIR_DUAL_PORT") || (operation_mode == "QUAD_PORT")))
29425 if (operation_mode == "BIDIR_DUAL_PORT")
29426 for (i3 = 0; i3 < width_write_b; i3 = i3 + 1)
29428 temp_wa2 = mem_data_w[(j3+i3)/width_write_a];
29429 temp_wa2[(j3+i3)%width_write_a] = i_data2_b[i3];
29430 mem_data_w[(j3+i3)/width_write_a] = temp_wa2;
29433 for (i3 = 0; i3 < width_write_b; i3 = i3 + 1)
29435 temp_ra2 = mem_data[(j3+i3)/width_read_a];
29436 temp_ra2[(j3+i3)%width_read_a] = i_data2_b[i3];
29437 mem_data[(j3+i3)/width_read_a] = temp_ra2;
29440 mem_updated = ~mem_updated;
29445 // This always block is to read the memory content for port A
29446 always @(posedge i_rden_tmp_a or negedge i_rden_tmp_a or
29447 i_rdaddress_tmp_a or
29448 i_wraddress_tmp_a or mem_updated)
29450 if ((operation_mode == "DUAL_PORT") || (operation_mode == "QUAD_PORT"))
29452 if (i_rden_tmp_a == 1)
29453 i_q_tmp_a = mem_data[i_rdaddress_tmp_a];
29455 else if ((operation_mode == "BIDIR_DUAL_PORT") || (operation_mode == "SINGLE_PORT"))
29456 i_q_tmp_a = mem_data_w[i_wraddress_tmp_a];
29457 else if (operation_mode == "ROM")
29458 i_q_tmp_a = mem_data[i_rdaddress_tmp_a];
29461 // This always block is to read the memory content for port A
29462 always @(posedge i_rden_tmp_b or negedge i_rden_tmp_b or
29463 i_rdaddress_tmp_b or
29464 i_wraddress_tmp_b or
29467 if (operation_mode == "QUAD_PORT")
29469 j2 = i_rdaddress_tmp_b * width_read_b;
29470 if (i_rden_tmp_b == 1)
29471 for (i2 = 0; i2 < width_read_b; i2 = i2 + 1)
29473 temp_ra = mem_data[(j2+i2)/width_read_a];
29474 i_q_tmp_b[i2] = temp_ra[(j2+i2)%width_read_a];
29477 else if (operation_mode == "BIDIR_DUAL_PORT")
29479 j2 = i_wraddress_tmp_b * width_write_b;
29480 for (i2=0; i2<width_write_b; i2=i2+1)
29482 temp_wa = mem_data_w[(j2+i2)/width_write_a];
29483 i_q_tmp_b[i2] = temp_wa[(j2+i2)%width_write_a];
29489 // This always block is to determine actual registered write address from port A
29491 always @(i_wraddress_hi_a or i_wraddress_lo_a or
29492 posedge i_wraddress_aclr_a or negedge i_wraddress_aclr_a)
29494 if ((operation_mode == "QUAD_PORT") || (operation_mode == "DUAL_PORT"))
29495 i_wraddress_reg_a <= (i_wraddress_aclr_a) ?
29496 0 : ((write_at_low_clock_a) ?
29497 i_wraddress_lo_a : i_wraddress_hi_a);
29499 i_wraddress_reg_a <= (i_wraddress_aclr_a) ?
29500 0 : i_wraddress_hi_a;
29504 // This always block is to determine actual registered write control from port A
29506 always @(i_wren_hi_a or i_wren_lo_a or
29507 posedge i_wraddress_aclr_a or negedge i_wraddress_aclr_a)
29509 if (operation_mode != "BIDIR_DUAL_PORT")
29510 i_wren_reg_a <= (i_wrcontrol_aclr_a) ? 0 :
29511 ((write_at_low_clock_a) ?
29512 i_wren_lo_a : i_wren_hi_a);
29514 i_wren_reg_a <= (i_wrcontrol_aclr_a) ?
29520 // This always block is to determine actual registered write data from port A
29522 always @(i_data_hi_a or i_data_lo_a or
29523 posedge i_indata_aclr_a or negedge i_indata_aclr_a)
29525 i_data_reg_a <= (i_indata_aclr_a) ? 0 :
29526 ((write_at_low_clock_a) ?
29527 i_data_lo_a : i_data_hi_a);
29531 // This always block is to determine actual registered write address from port B
29533 always @(i_wraddress_hi_b or i_wraddress_lo_b or
29534 posedge i_wraddress_aclr_b or negedge i_wraddress_aclr_b)
29536 if ((operation_mode == "QUAD_PORT") || (operation_mode == "DUAL_PORT"))
29537 i_wraddress_reg_b <= (i_wraddress_aclr_b) ? 0 :
29538 ((write_at_low_clock_b) ?
29539 i_wraddress_lo_b : i_wraddress_hi_b);
29541 i_wraddress_reg_b <= (i_wraddress_aclr_b) ?
29542 0 : i_wraddress_hi_b;
29546 // This always block is to determine actual registered write control from port B
29548 always @(i_wren_hi_b or i_wren_lo_b or
29549 posedge i_wraddress_aclr_b or negedge i_wraddress_aclr_b)
29551 if (operation_mode != "BIDIR_DUAL_PORT")
29552 i_wren_reg_b <= (i_wrcontrol_aclr_b) ? 0 :
29553 ((write_at_low_clock_b) ?
29554 i_wren_lo_b : i_wren_hi_b);
29556 i_wren_reg_b <= (i_wrcontrol_aclr_b) ?
29562 // This always block is to determine actual registered write data from port B
29564 always @(i_data_hi_b or i_data_lo_b or
29565 posedge i_indata_aclr_b or negedge i_indata_aclr_b)
29567 i_data_reg_b <= (i_indata_aclr_b) ? 0 :
29568 ((write_at_low_clock_b) ?
29569 i_data_lo_b : i_data_hi_b);
29573 // This always block is to determine actual write address from port A
29575 always @(wraddress_a or i_wraddress_reg_a or i_wraddress_aclr_a)
29577 i_wraddress_tmp_a <= (i_wraddress_aclr_a) ? 0 :
29578 ((wrcontrol_wraddress_reg_a == "INCLOCK_A") ?
29579 i_wraddress_reg_a : wraddress_a);
29583 // This always block is to determine actual write address from port B
29585 always @(wraddress_b or i_wraddress_reg_b or i_wraddress_aclr_b)
29587 i_wraddress_tmp_b <= (i_wraddress_aclr_b) ? 0 :
29588 ((wrcontrol_wraddress_reg_b == "INCLOCK_B") ?
29589 i_wraddress_reg_b : wraddress_b);
29593 // This always block is to determine actual read address from port A
29595 always @(rdaddress_a or i_rdaddress_reg_a or i_rdaddress_aclr_a)
29597 i_rdaddress_tmp_a <= (i_rdaddress_aclr_a) ? 0 :
29598 ((rdaddress_reg_a != "UNREGISTERED") ?
29599 i_rdaddress_reg_a : rdaddress_a);
29603 // This always block is to determine actual read address from port B
29605 always @(rdaddress_b or i_rdaddress_reg_b or i_rdaddress_aclr_b)
29607 i_rdaddress_tmp_b <= (i_rdaddress_aclr_b) ? 0 :
29608 ((rdaddress_reg_b != "UNREGISTERED") ?
29609 i_rdaddress_reg_b : rdaddress_b);
29613 // This always block is to determine actual write control from port A
29615 always @(i_wren_a or i_wren_reg_a or i_wrcontrol_aclr_a)
29617 i_wren_tmp_a <= (i_wrcontrol_aclr_a) ? 0 :
29618 ((wrcontrol_wraddress_reg_a == "INCLOCK_A") ?
29619 i_wren_reg_a : i_wren_a);
29623 // This always block is to determine actual write control from port B
29625 always @(i_wren_b or i_wren_reg_b or i_wrcontrol_aclr_b)
29627 i_wren_tmp_b <= (i_wrcontrol_aclr_b) ? 0 :
29628 ((wrcontrol_wraddress_reg_b == "INCLOCK_B") ?
29629 i_wren_reg_b : i_wren_b);
29633 // This always block is to determine actual read control from port A
29635 always @(i_rden_a or i_rden_reg_a or i_rdcontrol_aclr_a)
29637 i_rden_tmp_a <= (i_rdcontrol_aclr_a) ? 0 :
29638 ((rdcontrol_reg_a != "UNREGISTERED") ?
29639 i_rden_reg_a : i_rden_a);
29643 // This always block is to determine actual read control from port B
29645 always @(i_rden_b or i_rden_reg_b or i_rdcontrol_aclr_b)
29647 i_rden_tmp_b <= (i_rdcontrol_aclr_b) ? 0 :
29648 ((rdcontrol_reg_b != "UNREGISTERED") ?
29649 i_rden_reg_b : i_rden_b);
29652 // This always block is to determine actual write data from port A
29654 always @(data_a or i_data_reg_a or i_indata_aclr_a)
29656 i_data_tmp_a <= (i_indata_aclr_a) ? 0 :
29657 ((indata_reg_a == "INCLOCK_A") ?
29658 i_data_reg_a : data_a);
29662 // This always block is to determine actual write data from port B
29664 always @(data_b or i_data_reg_b or i_indata_aclr_b)
29666 i_data_tmp_b <= (i_indata_aclr_b) ? 0 :
29667 ((indata_reg_b == "INCLOCK_B") ?
29668 i_data_reg_b : data_b);
29672 // SIGNAL ASSIGNMENT
29675 assign q_a = (i_outdata_aclr_a) ? 0 :
29676 ((outdata_reg_a != "UNREGISTERED") ? i_q_reg_a : i_q_tmp_a);
29679 assign q_b = ((operation_mode != "BIDIR_DUAL_PORT") && (operation_mode != "QUAD_PORT")) ? 0 :
29680 (i_outdata_aclr_b) ? 0 :
29681 ((outdata_reg_b != "UNREGISTERED") ? i_q_reg_b : i_q_tmp_b);
29683 endmodule // ALTQPRAM
29687 //START_MODULE_NAME------------------------------------------------------------
29689 // Module Name : parallel_add
29691 // Description : Parameterized parallel adder megafunction. The data input
29692 // is a concatenated group of input words. The size
29693 // parameter indicates the number of 'width'-bit words.
29695 // Each word is added together to generate the result output.
29696 // Each word is left shifted according to the shift
29697 // parameter. The shift amount is multiplied by the word
29698 // index, with the least significant word being word 0.
29699 // The shift for word I is (shift * I).
29701 // The most significant word can be subtracted from the total
29702 // by setting the msw_subtract parameter to 1.
29703 // If the result width is less than is required to show the
29704 // full result, the result output can be aligned to the MSB
29705 // or the LSB of the internal result. When aligning to the
29706 // MSB, the internally calculated best_result_width is used
29707 // to find the true MSB.
29708 // The input data can be signed or unsigned, and the output
29709 // can be pipelined.
29711 // Limitations : Minimum data width is 1, and at least 2 words are required.
29713 // Results expected: result - The sum of all inputs.
29715 //END_MODULE_NAME--------------------------------------------------------------
29717 `timescale 1 ps / 1 ps
29719 module parallel_add (
29726 parameter width = 4; // Required
29727 parameter size = 2; // Required
29728 parameter widthr = 4; // Required
29729 parameter shift = 0;
29730 parameter msw_subtract = "NO"; // or "YES"
29731 parameter representation = "UNSIGNED";
29732 parameter pipeline = 0;
29733 parameter result_alignment = "LSB"; // or "MSB"
29734 parameter lpm_type = "parallel_add";
29735 parameter lpm_hint = "UNUSED";
29737 // Maximum precision required for internal calculations.
29738 // This is a pessimistic estimate, but it is guaranteed to be sufficient.
29739 // The +30 is there only to simplify the test generator, which occasionally asks
29740 // for output widths far in excess of what is needed. The excess is always less than 30.
29741 `define max_precision (width+size+shift*(size-1)+30) // Result will not overflow this size
29743 // INPUT PORT DECLARATION
29744 input [width*size-1:0] data; // Required port
29745 input clock; // Required port
29746 input aclr; // Default = 0
29747 input clken; // Default = 1
29749 // OUTPUT PORT DECLARATION
29750 output [widthr-1:0] result; //Required port
29752 // INTERNAL REGISTER DECLARATION
29754 reg [width-1:0] idata_word;
29755 reg [`max_precision-1:0] idata_extended;
29756 reg [`max_precision-1:0] tmp_result;
29757 reg [widthr-1:0] resultpipe [(pipeline +1):0];
29759 // INTERNAL TRI DECLARATION
29762 // INTERNAL WIRE DECLARATION
29763 wire [widthr-1:0] aligned_result;
29765 // LOCAL INTEGER DECLARATION
29767 integer best_result_width;
29770 // Note: The recommended value for WIDTHR parameter,
29771 // the width of addition result, for full
29774 // ((2^WIDTH)-1) * (2^(SIZE*SHIFT)-1)
29775 // WIDTHR = CEIL(LOG2(-----------------------------------))
29778 // Use CALC_PADD_WIDTHR(WIDTH, SIZE, SHIFT):
29779 // DEFINE CALC_PADD_WIDTHR(w, z, s) = (s == 0) ? CEIL(LOG2(z*((2^w)-1))) :
29780 // CEIL(LOG2(((2^w)-1) * (2^(z*s)-1) / ((2^s)-1)));
29781 function integer ceil_log2;
29782 input [`max_precision-1:0] input_num;
29784 reg [`max_precision-1:0] try_result;
29788 while ((try_result << i) < input_num && i < `max_precision)
29797 if (widthr > `max_precision)
29798 $display ("Error! WIDTHR must not exceed WIDTH+SIZE+SHIFT*(SIZE-1).");
29800 $display ("Error! SIZE must be greater than 1.");
29804 best_result_width = width;
29806 best_result_width = best_result_width + ceil_log2(size);
29809 best_result_width = ceil_log2( ((1<<width)-1) * ((1 << (size*shift))-1)
29810 / ((1 << shift)-1));
29812 imsb_align = (result_alignment == "MSB" && widthr < best_result_width) ? 1 : 0;
29814 // Clear the pipeline array
29815 for (ni=0; ni< pipeline +1; ni=ni+1)
29816 resultpipe[ni] = 0;
29824 // Loop over each input data word, and add to the total
29825 for (ni=0; ni<size; ni=ni+1)
29827 // Get input word to add to total
29828 idata_word = (data >> (ni * width));
29830 // If signed and negative, pad MSB with ones to sign extend the input data
29831 if ((representation != "UNSIGNED") && (idata_word[width-1] == 1'b1))
29832 idata_extended = ({{(`max_precision-width-2){1'b1}}, idata_word} << (shift*ni));
29834 idata_extended = (idata_word << (shift*ni)); // zero padding is automatic
29837 if ((msw_subtract == "YES") && (ni == (size-1)))
29838 tmp_result = tmp_result - idata_extended;
29840 tmp_result = tmp_result + idata_extended;
29845 always @(posedge clock or posedge aclr)
29849 // Clear the pipeline array
29850 for (ni=0; ni< (pipeline +1); ni=ni+1)
29851 resultpipe[ni] <= 0;
29854 else if (clken_int == 1'b1)
29856 resultpipe[pipe_ptr] <= aligned_result;
29858 pipe_ptr <= (pipe_ptr + 1) % pipeline;
29862 // Check if output needs MSB alignment
29863 assign aligned_result = (imsb_align == 1)
29864 ? (tmp_result >> (best_result_width-widthr))
29866 assign clken_int = clken;
29867 assign result = (pipeline > 0) ? resultpipe[pipe_ptr] : aligned_result;
29868 endmodule // end of PARALLEL_ADD
29870 //START_MODULE_NAME------------------------------------------------------------
29872 // Module Name : scfifo
29874 // Description : Single Clock FIFO
29876 // Limitation : USE_EAB=OFF is not supported
29878 // Results expected:
29880 //END_MODULE_NAME--------------------------------------------------------------
29882 // BEGINNING OF MODULE
29883 `timescale 1 ps / 1 ps
29885 // MODULE DECLARATION
29886 module scfifo ( data,
29899 // GLOBAL PARAMETER DECLARATION
29900 parameter lpm_width = 1;
29901 parameter lpm_widthu = 1;
29902 parameter lpm_numwords = 2;
29903 parameter lpm_showahead = "OFF";
29904 parameter lpm_type = "scfifo";
29905 parameter lpm_hint = "USE_EAB=ON";
29906 parameter intended_device_family = "APEX20KE";
29907 parameter underflow_checking = "ON";
29908 parameter overflow_checking = "ON";
29909 parameter allow_rwcycle_when_full = "OFF";
29910 parameter use_eab = "ON";
29911 parameter add_ram_output_register = "OFF";
29912 parameter almost_full_value = 0;
29913 parameter almost_empty_value = 0;
29914 parameter maximum_depth = 0;
29915 parameter showahead_area = ((lpm_showahead == "ON") && (add_ram_output_register == "OFF"));
29916 parameter showahead_speed = ((lpm_showahead == "ON") && (add_ram_output_register == "ON"));
29917 parameter legacy_speed = ((lpm_showahead == "OFF") && (add_ram_output_register == "ON"));
29919 // INPUT PORT DECLARATION
29920 input [lpm_width-1:0] data;
29927 // OUTPUT PORT DECLARATION
29928 output [lpm_width-1:0] q;
29929 output [lpm_widthu-1:0] usedw;
29932 output almost_full;
29933 output almost_empty;
29935 // INTERNAL REGISTERS DECLARATION
29936 reg [lpm_width-1:0] mem_data [(1<<lpm_widthu):0];
29937 reg [lpm_widthu-1:0] count_id;
29938 reg [lpm_widthu-1:0] read_id;
29939 reg [lpm_widthu-1:0] write_id;
29946 reg almost_full_flag;
29947 reg almost_empty_flag;
29948 reg [lpm_width-1:0] tmp_q;
29949 reg stratix_family;
29952 reg [lpm_widthu-1:0] write_latency1;
29953 reg [lpm_widthu-1:0] write_latency2;
29954 reg [lpm_widthu-1:0] write_latency3;
29957 reg empty_latency1;
29958 reg empty_latency2;
29960 reg [(1<<lpm_widthu)-1:0] data_ready;
29961 reg [(1<<lpm_widthu)-1:0] data_shown;
29963 // INTERNAL TRI DECLARATION
29966 // LOCAL INTEGER DECLARATION
29969 // COMPONENT INSTANTIATIONS
29970 ALTERA_DEVICE_FAMILIES dev ();
29972 // INITIAL CONSTRUCT BLOCK
29976 stratix_family = ( dev.IS_FAMILY_STRATIX(intended_device_family) ||
29977 dev.IS_FAMILY_STRATIXGX(intended_device_family) ||
29978 dev.FEATURE_FAMILY_STRATIXII(intended_device_family) ||
29979 dev.IS_FAMILY_CYCLONE(intended_device_family) ||
29980 dev.IS_FAMILY_CYCLONEII(intended_device_family));
29982 if (lpm_width <= 0)
29983 $display ("Error! LPM_WIDTH must be greater than 0.");
29984 if (lpm_numwords <= 1)
29985 $display ("Error! LPM_NUMWORDS must be greater than or equal to 2.");
29986 if ((lpm_widthu !=1) && (lpm_numwords > (1 << lpm_widthu)))
29987 $display ("Error! LPM_NUMWORDS must equal to the ceiling of log2(LPM_WIDTHU).");
29988 if (lpm_numwords <= (1 << (lpm_widthu - 1)))
29989 $display ("Error! LPM_WIDTHU is too big for the specified LPM_NUMWORDS.");
29990 if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
29991 $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
29992 if((add_ram_output_register != "ON") && (add_ram_output_register != "OFF"))
29993 $display ("Error! add_ram_output_register must be ON or OFF.");
29995 for (i = 0; i < (1<<lpm_widthu); i = i + 1)
29997 if (dev.IS_FAMILY_STRATIX(intended_device_family) ||
29998 dev.IS_FAMILY_STRATIXGX(intended_device_family) ||
29999 dev.FEATURE_FAMILY_STRATIXII(intended_device_family) ||
30000 dev.IS_FAMILY_CYCLONE(intended_device_family) ||
30001 dev.IS_FAMILY_CYCLONEII(intended_device_family))
30003 if ((add_ram_output_register == "ON") || (use_eab == "OFF"))
30004 mem_data[i] <= {lpm_width{1'b0}};
30006 mem_data[i] <= {lpm_width{1'bx}};
30009 mem_data[i] <= {lpm_width{1'b0}};
30012 if (dev.IS_FAMILY_STRATIX(intended_device_family) ||
30013 dev.IS_FAMILY_STRATIXGX(intended_device_family) ||
30014 dev.FEATURE_FAMILY_STRATIXII(intended_device_family) ||
30015 dev.IS_FAMILY_CYCLONE(intended_device_family) ||
30016 dev.IS_FAMILY_CYCLONEII(intended_device_family))
30018 if ((add_ram_output_register == "ON") || (use_eab == "OFF"))
30019 tmp_q <= {lpm_width{1'b0}};
30021 tmp_q <= {lpm_width{1'bx}};
30024 tmp_q <= {lpm_width{1'b0}};
30026 write_flag <= 1'b0;
30031 empty_flag <= 1'b1;
30032 empty_latency1 <= 1'b1;
30033 empty_latency2 <= 1'b1;
30034 set_q_to_x <= 1'b0;
30037 if (almost_full_value == 0)
30038 almost_full_flag <= 1'b1;
30040 almost_full_flag <= 1'b0;
30042 if (almost_empty_value == 0)
30043 almost_empty_flag <= 1'b0;
30045 almost_empty_flag <= 1'b1;
30048 // ALWAYS CONSTRUCT BLOCK
30049 always @(rdreq or empty_flag)
30051 if (underflow_checking == "OFF")
30052 valid_rreq <= rdreq;
30054 valid_rreq <= rdreq && ~empty_flag;
30057 always @(wrreq or rdreq or full_flag)
30059 if (overflow_checking == "OFF")
30060 valid_wreq <= wrreq;
30061 else if (allow_rwcycle_when_full == "ON")
30062 valid_wreq <= wrreq && (!full_flag || rdreq);
30064 valid_wreq <= wrreq && !full_flag;
30067 always @(posedge clock or posedge aclr)
30071 if ((lpm_showahead == "ON") && (use_eab == "ON"))
30073 tmp_q <= {lpm_width{1'bX}};
30077 if (!stratix_family)
30079 tmp_q <= {lpm_width{1'b0}};
30082 tmp_q <= {lpm_width{1'bX}};
30088 empty_flag <= 1'b1;
30089 empty_latency1 <= 1'b1;
30090 empty_latency2 <= 1'b1;
30091 set_q_to_x <= 1'b0;
30094 if (almost_full_value > 0)
30095 almost_full_flag <= 1'b0;
30096 if (almost_empty_value > 0)
30097 almost_empty_flag <= 1'b1;
30101 if ((use_eab == "ON") && (stratix_family) && ((showahead_speed) || (showahead_area) || (legacy_speed)))
30103 write_latency1 <= 1'bx;
30104 write_latency2 <= 1'bx;
30105 data_shown <= {lpm_width{1'b0}};
30106 tmp_q <= {lpm_width{1'bX}};
30113 tmp_q <= {lpm_width{1'bX}};
30118 empty_flag <= 1'b1;
30119 empty_latency1 <= 1'b1;
30120 empty_latency2 <= 1'b1;
30121 set_q_to_x <= 1'b0;
30124 if (almost_full_value > 0)
30125 almost_full_flag <= 1'b0;
30126 if (almost_empty_value > 0)
30127 almost_empty_flag <= 1'b1;
30129 if (!stratix_family)
30133 write_flag <= 1'b1;
30143 if ((use_eab == "ON") && (stratix_family) && ((showahead_speed) || (showahead_area) || (legacy_speed)))
30145 write_latency1 <= 1'bx;
30146 write_latency2 <= 1'bx;
30147 data_shown <= {lpm_width{1'b0}};
30148 tmp_q <= {lpm_width{1'bX}};
30156 if ((overflow_checking == "OFF" && full_flag && !valid_rreq) || set_q_to_x)
30158 tmp_q <= {lpm_width{1'bX}};
30159 set_q_to_x <= 1'b1;
30163 mem_data[write_id] <= data;
30164 write_flag <= 1'b1;
30166 if (!((use_eab == "ON") && stratix_family && (showahead_speed || showahead_area || legacy_speed)))
30168 empty_flag <= 1'b0;
30172 empty_latency1 <= 1'b0;
30176 wrt_count <= wrt_count + 1;
30180 if (count_id >= (1 << lpm_widthu) - 1)
30183 count_id <= count_id + 1;
30187 if (allow_rwcycle_when_full == "OFF")
30191 if (!(stratix_family) || (stratix_family && !(showahead_speed || showahead_area || legacy_speed)))
30194 if ((count_id == lpm_numwords - 1) && (empty_flag == 1'b0))
30200 if (count_id == lpm_numwords - 1)
30204 if (lpm_showahead == "ON")
30206 if ((use_eab == "ON") && stratix_family && (showahead_speed || showahead_area))
30208 write_latency1 <= write_id;
30209 data_shown[write_id] <= 1'b1;
30210 data_ready[write_id] <= 1'bx;
30214 if ((use_eab == "OFF") && stratix_family && (count_id == 0))
30220 if ((!empty_flag) && (!valid_rreq))
30222 tmp_q <= mem_data[read_id];
30229 if ((use_eab == "ON") && stratix_family && legacy_speed)
30231 write_latency1 <= write_id;
30232 data_shown[write_id] <= 1'b1;
30233 data_ready[write_id] <= 1'bx;
30244 wrt_count <= wrt_count - 1;
30251 count_id <= ((1 << lpm_widthu) - 1);
30253 count_id <= count_id - 1;
30256 if ((use_eab == "ON") && stratix_family && (showahead_speed || showahead_area || legacy_speed))
30258 if ((wrt_count == 1 && valid_rreq && !valid_wreq) || ((wrt_count == 1 ) && valid_wreq && valid_rreq))
30260 empty_flag <= 1'b1;
30264 if (showahead_speed)
30266 if (data_shown[write_latency2] == 1'b0)
30268 empty_flag <= 1'b1;
30271 else if (showahead_area || legacy_speed)
30273 if (data_shown[write_latency1] == 1'b0)
30275 empty_flag <= 1'b1;
30284 if ((count_id == 1) && !(full_flag))
30285 empty_flag <= 1'b1;
30291 tmp_q <= {lpm_width{1'bX}};
30293 else if (read_id >= ((1<<lpm_widthu) - 1))
30295 if (lpm_showahead == "ON")
30297 if ((use_eab == "ON") && stratix_family && (showahead_speed || showahead_area))
30299 if (showahead_speed)
30301 if ((write_latency2 == 0) || (data_ready[0] == 1'b1))
30303 if (data_shown[0] == 1'b1)
30305 tmp_q <= mem_data[0];
30306 data_shown[0] <= 1'b0;
30307 data_ready[0] <= 1'b0;
30313 if ((count_id == 1) && !(full_flag))
30315 tmp_q <= {lpm_width{1'bX}};
30317 else if ((write_latency1 == 0) || (data_ready[0] == 1'b1))
30319 if (data_shown[0] == 1'b1)
30321 tmp_q <= mem_data[0];
30322 data_shown[0] <= 1'b0;
30323 data_ready[0] <= 1'b0;
30330 if ((count_id == 1) && !(full_flag))
30331 tmp_q <= {lpm_width{1'bX}};
30333 tmp_q <= mem_data[0];
30338 if ((use_eab == "ON") && stratix_family && legacy_speed)
30340 if ((write_latency1 == read_id) || (data_ready[read_id] == 1'b1))
30342 if (data_shown[read_id] == 1'b1)
30344 tmp_q <= mem_data[read_id];
30345 data_shown[read_id] <= 1'b0;
30346 data_ready[read_id] <= 1'b0;
30351 tmp_q <= {lpm_width{1'bX}};
30355 tmp_q <= mem_data[read_id];
30359 end // end if (read_id >= ((1<<lpm_widthu) - 1))
30362 if (lpm_showahead == "ON")
30364 if ((use_eab == "ON") && stratix_family && (showahead_speed || showahead_area))
30366 if (showahead_speed)
30368 if ((write_latency2 == read_id+1) || (data_ready[read_id+1] == 1'b1))
30370 if (data_shown[read_id+1] == 1'b1)
30372 tmp_q <= mem_data[read_id + 1];
30373 data_shown[read_id+1] <= 1'b0;
30374 data_ready[read_id+1] <= 1'b0;
30380 if ((count_id == 1) && !(full_flag))
30382 tmp_q <= {lpm_width{1'bX}};
30384 else if ((write_latency1 == read_id+1) || (data_ready[read_id+1] == 1'b1))
30386 if (data_shown[read_id+1] == 1'b1)
30388 tmp_q <= mem_data[read_id + 1];
30389 data_shown[read_id+1] <= 1'b0;
30390 data_ready[read_id+1] <= 1'b0;
30397 if ((count_id == 1) && !(full_flag))
30399 if ((use_eab == "OFF") && stratix_family)
30407 tmp_q <= {lpm_width{1'bX}};
30412 tmp_q <= {lpm_width{1'bX}};
30416 tmp_q <= mem_data[read_id + 1];
30421 if ((use_eab == "ON") && stratix_family && legacy_speed)
30423 if ((write_latency1 == read_id) || (data_ready[read_id] == 1'b1))
30425 if (data_shown[read_id] == 1'b1)
30427 tmp_q <= mem_data[read_id];
30428 data_shown[read_id] <= 1'b0;
30429 data_ready[read_id] <= 1'b0;
30434 tmp_q <= {lpm_width{1'bX}};
30438 tmp_q <= mem_data[read_id];
30441 read_id <= read_id + 1;
30446 if (almost_full_value == 0)
30447 almost_full_flag <= 1'b1;
30448 else if (lpm_numwords > almost_full_value)
30450 if (almost_full_flag)
30452 if ((count_id == almost_full_value) && !wrreq && rdreq)
30453 almost_full_flag <= 1'b0;
30457 if ((almost_full_value == 1) && (count_id == 0) && wrreq)
30458 almost_full_flag <= 1'b1;
30459 else if ((almost_full_value > 1) && (count_id == almost_full_value - 1)
30460 && wrreq && !rdreq)
30461 almost_full_flag <= 1'b1;
30465 if (almost_empty_value == 0)
30466 almost_empty_flag <= 1'b0;
30467 else if (lpm_numwords > almost_empty_value)
30469 if (almost_empty_flag)
30471 if ((almost_empty_value == 1) && (count_id == 0) && wrreq)
30472 almost_empty_flag <= 1'b0;
30473 else if ((almost_empty_value > 1) && (count_id == almost_empty_value - 1)
30474 && wrreq && !rdreq)
30475 almost_empty_flag <= 1'b0;
30479 if ((count_id == almost_empty_value) && !wrreq && rdreq)
30480 almost_empty_flag <= 1'b1;
30485 if ((use_eab == "ON") && stratix_family)
30487 if (showahead_speed)
30489 write_latency2 <= write_latency1;
30490 write_latency3 <= write_latency2;
30491 if (write_latency3 !== write_latency2)
30492 data_ready[write_latency2] <= 1'b1;
30494 empty_latency2 <= empty_latency1;
30496 if (data_shown[write_latency2]==1'b1)
30498 if ((read_id == write_latency2) || aclr || sclr)
30500 if (!(aclr === 1'b1) && !(sclr === 1'b1))
30502 if (write_latency2 !== 1'bx)
30504 tmp_q <= mem_data[write_latency2];
30505 data_shown[write_latency2] <= 1'b0;
30506 data_ready[write_latency2] <= 1'b0;
30509 empty_flag <= empty_latency2;
30515 else if (showahead_area)
30517 write_latency2 <= write_latency1;
30518 if (write_latency2 !== write_latency1)
30519 data_ready[write_latency1] <= 1'b1;
30521 if (data_shown[write_latency1]==1'b1)
30523 if ((read_id == write_latency1) || aclr || sclr)
30525 if (!(aclr === 1'b1) && !(sclr === 1'b1))
30527 if (write_latency1 !== 1'bx)
30529 tmp_q <= mem_data[write_latency1];
30530 data_shown[write_latency1] <= 1'b0;
30531 data_ready[write_latency1] <= 1'b0;
30535 empty_flag <= empty_latency1;
30546 write_latency2 <= write_latency1;
30547 if (write_latency2 !== write_latency1)
30548 data_ready[write_latency1] <= 1'b1;
30550 empty_flag <= empty_latency1;
30552 if ((wrt_count == 1 && !valid_wreq && valid_rreq) || aclr || sclr)
30554 empty_flag <= 1'b1;
30555 empty_latency1 <= 1'b1;
30559 if ((wrt_count == 1) && valid_wreq && valid_rreq)
30561 empty_flag <= 1'b1;
30570 always @(negedge clock)
30574 write_flag <= 1'b0;
30576 if (sclr || aclr || (write_id >= ((1 << lpm_widthu) - 1)))
30579 write_id <= write_id + 1;
30582 if (!(stratix_family))
30586 if ((lpm_showahead == "ON") && ($time > 0))
30587 tmp_q <= mem_data[read_id];
30592 always @(full_flag)
30594 if (lpm_numwords == almost_full_value)
30596 almost_full_flag <= 1'b1;
30598 almost_full_flag <= 1'b0;
30600 if (lpm_numwords == almost_empty_value)
30602 almost_empty_flag <= 1'b0;
30604 almost_empty_flag <= 1'b1;
30607 // CONTINOUS ASSIGNMENT
30609 assign full = full_flag;
30610 assign empty = empty_flag;
30611 assign usedw = count_id;
30612 assign almost_full = almost_full_flag;
30613 assign almost_empty = almost_empty_flag;
30615 endmodule // scfifo
30618 //START_MODULE_NAME------------------------------------------------------------
30620 // Module Name : dcfifo_dffpipe
30622 // Description : Dual Clocks FIFO
30626 // Results expected:
30628 //END_MODULE_NAME--------------------------------------------------------------
30630 // BEGINNING OF MODULE
30631 `timescale 1 ps / 1 ps
30633 // MODULE DECLARATION
30634 module dcfifo_dffpipe ( d, clock, aclr,
30637 // GLOBAL PARAMETER DECLARATION
30638 parameter lpm_delay = 1;
30639 parameter lpm_width = 64;
30641 // INPUT PORT DECLARATION
30642 input [lpm_width-1:0] d;
30646 // OUTPUT PORT DECLARATION
30647 output [lpm_width-1:0] q;
30649 // INTERNAL REGISTERS DECLARATION
30650 reg [lpm_width-1:0] dffpipe [lpm_delay:0];
30651 reg [lpm_width-1:0] q;
30653 // LOCAL INTEGER DECLARATION
30656 // INITIAL CONSTRUCT BLOCK
30659 delay <= lpm_delay - 1;
30660 for (i = 0; i < lpm_delay; i = i + 1)
30665 // ALWAYS CONSTRUCT BLOCK
30666 always @(posedge clock or posedge aclr)
30670 for (i = 0; i < lpm_delay; i = i + 1)
30676 if ((lpm_delay > 0) && ($time > 0))
30680 for (i = delay; i > 0; i = i - 1)
30681 dffpipe[i] <= dffpipe[i - 1];
30682 q <= dffpipe[delay - 1];
30690 end // @(posedge aclr or posedge clock)
30694 if (lpm_delay == 0)
30698 endmodule // dcfifo_dffpipe
30701 //START_MODULE_NAME------------------------------------------------------------
30703 // Module Name : dcfifo_fefifo
30705 // Description : Dual Clock FIFO
30709 // Results expected:
30711 //END_MODULE_NAME--------------------------------------------------------------
30713 // BEGINNING OF MODULE
30714 `timescale 1 ps / 1 ps
30716 // MODULE DECLARATION
30717 module dcfifo_fefifo ( usedw_in, wreq, rreq, clock, aclr,
30720 // GLOBAL PARAMETER DECLARATION
30721 parameter lpm_widthad = 1;
30722 parameter lpm_numwords = 1;
30723 parameter underflow_checking = "ON";
30724 parameter overflow_checking = "ON";
30725 parameter lpm_mode = "READ";
30727 // INPUT PORT DECLARATION
30728 input [lpm_widthad-1:0] usedw_in;
30733 // OUTPUT PORT DECLARATION
30734 output empty, full;
30736 // INTERNAL REGISTERS DECLARATION
30737 reg [1:0] sm_empty;
30739 reg i_empty, i_full;
30741 // LOCAL INTEGER DECLARATION
30742 integer almostfull;
30744 // INITIAL CONSTRUCT BLOCK
30747 if ((lpm_mode != "READ") && (lpm_mode != "WRITE"))
30748 $display ("Error! LPM_MODE must be READ or WRITE.");
30749 if ((underflow_checking != "ON") && (underflow_checking != "OFF"))
30750 $display ("Error! UNDERFLOW_CHECKING must be ON or OFF.");
30751 if ((overflow_checking != "ON") && (overflow_checking != "OFF"))
30752 $display ("Error! OVERFLOW_CHECKING must be ON or OFF.");
30758 if (lpm_numwords >= 3)
30759 almostfull <= lpm_numwords - 3;
30764 // ALWAYS CONSTRUCT BLOCK
30765 always @(posedge aclr)
30771 end // @(posedge aclr)
30773 always @(posedge clock)
30775 if (underflow_checking == "OFF")
30778 lrreq <= rreq && ~i_empty;
30780 if (~aclr && $time > 0)
30782 if (lpm_mode == "READ")
30791 if (rreq && (((usedw_in == 1) && !lrreq) || ((usedw_in == 2) && lrreq)))
30800 $display ("Error! Invalid sm_empty state in read mode.");
30802 end // if (lpm_mode == "READ")
30803 else if (lpm_mode == "WRITE")
30818 else if (usedw_in == 0)
30821 $display ("Error! Invalid sm_empty state in write mode.");
30823 end // if (lpm_mode == "WRITE")
30825 if (~aclr && (usedw_in >= almostfull) && ($time > 0))
30829 end // if (~aclr && $time > 0)
30830 end // @(posedge clock)
30834 i_empty <= !sm_empty[0];
30838 // CONTINOUS ASSIGNMENT
30839 assign empty = i_empty;
30840 assign full = i_full;
30841 endmodule // dcfifo_fefifo
30844 //START_MODULE_NAME------------------------------------------------------------
30846 // Module Name : dcfifo_async
30848 // Description : Asynchronous Dual Clocks FIFO
30852 // Results expected:
30854 //END_MODULE_NAME--------------------------------------------------------------
30856 // BEGINNING OF MODULE
30857 `timescale 1 ps / 1 ps
30859 // MODULE DECLARATION
30860 module dcfifo_async (data, rdclk, wrclk, aclr, rdreq, wrreq,
30861 rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q);
30863 // GLOBAL PARAMETER DECLARATION
30864 parameter lpm_width = 1;
30865 parameter lpm_widthu = 1;
30866 parameter lpm_numwords = 2;
30867 parameter delay_rdusedw = 1;
30868 parameter delay_wrusedw = 1;
30869 parameter rdsync_delaypipe = 3;
30870 parameter wrsync_delaypipe = 3;
30871 parameter intended_device_family = "APEX20KE";
30872 parameter lpm_showahead = "OFF";
30873 parameter underflow_checking = "ON";
30874 parameter overflow_checking = "ON";
30875 parameter use_eab = "ON";
30876 parameter add_ram_output_register = "OFF";
30878 // INPUT PORT DECLARATION
30879 input [lpm_width-1:0] data;
30886 // OUTPUT PORT DECLARATION
30891 output [lpm_widthu-1:0] rdusedw;
30892 output [lpm_widthu-1:0] wrusedw;
30893 output [lpm_width-1:0] q;
30895 // INTERNAL REGISTERS DECLARATION
30896 reg [lpm_width-1:0] mem_data [(1<<lpm_widthu)-1:0];
30897 reg [lpm_width-1:0] mem_data2 [(1<<lpm_widthu)-1:0];
30898 reg data_ready [(1<<lpm_widthu)-1:0];
30899 reg [2:0] data_delay_count [(1<<lpm_widthu)-1:0];
30900 reg [lpm_width-1:0] i_data_tmp;
30901 reg [lpm_widthu-1:0] i_rdptr;
30902 reg [lpm_widthu-1:0] i_wrptr;
30903 reg [lpm_widthu-1:0] i_wrptr_tmp;
30908 reg i_showahead_flag;
30909 reg i_showahead_flag1;
30910 reg i_showahead_flag2;
30911 reg i_showahead_flag3;
30912 reg [lpm_widthu-1:0] i_wr_udwn;
30913 reg [lpm_widthu-1:0] i_rd_udwn;
30914 reg [lpm_widthu:0] i_rdusedw;
30915 reg [lpm_widthu-1:0] i_wrusedw;
30916 reg [lpm_width-1:0] i_q_tmp;
30918 // INTERNAL WIRE DECLARATION
30923 wire [lpm_widthu-1:0] w_rdptrrg;
30924 wire [lpm_widthu-1:0] w_wrdelaycycle;
30925 wire [lpm_widthu-1:0] w_ws_nbrp;
30926 wire [lpm_widthu-1:0] w_rs_nbwp;
30927 wire [lpm_widthu-1:0] w_ws_dbrp;
30928 wire [lpm_widthu-1:0] w_rs_dbwp;
30929 wire [lpm_widthu-1:0] w_rd_dbuw;
30930 wire [lpm_widthu-1:0] w_wr_dbuw;
30931 wire [lpm_widthu-1:0] w_rdusedw;
30932 wire [lpm_widthu-1:0] w_wrusedw;
30934 // INTERNAL TRI DECLARATION
30937 // LOCAL INTEGER DECLARATION
30942 // COMPONENT INSTANTIATION
30943 ALTERA_DEVICE_FAMILIES dev ();
30945 // INITIAL CONSTRUCT BLOCK
30948 if((lpm_showahead != "ON") && (lpm_showahead != "OFF"))
30949 $display ("Error! lpm_showahead must be ON or OFF.");
30950 if((underflow_checking != "ON") && (underflow_checking != "OFF"))
30951 $display ("Error! underflow_checking must be ON or OFF.");
30952 if((overflow_checking != "ON") && (overflow_checking != "OFF"))
30953 $display ("Error! overflow_checking must be ON or OFF.");
30954 if((use_eab != "ON") && (use_eab != "OFF"))
30955 $display ("Error! use_eab must be ON or OFF.");
30956 if((add_ram_output_register != "ON") && (add_ram_output_register != "OFF"))
30957 $display ("Error! add_ram_output_register must be ON or OFF.");
30958 if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
30959 $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
30961 for (i = 0; i < (1 << lpm_widthu); i = i + 1)
30965 data_ready[i] <= 1'b0;
30966 data_delay_count[i] <= 0;
30969 if ((add_ram_output_register == "OFF") &&
30970 (dev.IS_FAMILY_STRATIX(intended_device_family) ||
30971 dev.IS_FAMILY_STRATIXGX(intended_device_family) ||
30972 dev.IS_FAMILY_CYCLONE(intended_device_family)))
30974 for (i = 0; i < (1 << lpm_widthu); i = i + 1)
30976 mem_data2[i] <= {lpm_width{1'bx}};
30981 for (i = 0; i < (1 << lpm_widthu); i = i + 1)
30999 // COMPONENT INSTANTIATIONS
31000 // Delays & DFF Pipes
31001 dcfifo_dffpipe DP_RDPTR_D (
31003 .clock (i_rdenclock),
31006 dcfifo_dffpipe DP_WRPTR_D (
31010 .q (w_wrdelaycycle));
31012 DP_RDPTR_D.lpm_delay = 0,
31013 DP_RDPTR_D.lpm_width = lpm_widthu,
31014 DP_WRPTR_D.lpm_delay = 1,
31015 DP_WRPTR_D.lpm_width = lpm_widthu;
31017 dcfifo_dffpipe DP_WS_NBRP (
31022 dcfifo_dffpipe DP_RS_NBWP (
31023 .d (w_wrdelaycycle),
31027 dcfifo_dffpipe DP_WS_DBRP (
31032 dcfifo_dffpipe DP_RS_DBWP (
31038 DP_WS_NBRP.lpm_delay = wrsync_delaypipe,
31039 DP_WS_NBRP.lpm_width = lpm_widthu,
31040 DP_RS_NBWP.lpm_delay = rdsync_delaypipe,
31041 DP_RS_NBWP.lpm_width = lpm_widthu,
31042 DP_WS_DBRP.lpm_delay = 1, // gray_delaypipe
31043 DP_WS_DBRP.lpm_width = lpm_widthu,
31044 DP_RS_DBWP.lpm_delay = 1, // gray_delaypipe
31045 DP_RS_DBWP.lpm_width = lpm_widthu;
31047 dcfifo_dffpipe DP_WRUSEDW (
31052 dcfifo_dffpipe DP_RDUSEDW (
31057 dcfifo_dffpipe DP_WR_DBUW (
31062 dcfifo_dffpipe DP_RD_DBUW (
31068 DP_WRUSEDW.lpm_delay = delay_wrusedw,
31069 DP_WRUSEDW.lpm_width = lpm_widthu,
31070 DP_RDUSEDW.lpm_delay = delay_rdusedw,
31071 DP_RDUSEDW.lpm_width = lpm_widthu,
31072 DP_WR_DBUW.lpm_delay = 1, // wrusedw_delaypipe
31073 DP_WR_DBUW.lpm_width = lpm_widthu,
31074 DP_RD_DBUW.lpm_delay = 1, // rdusedw_delaypipe
31075 DP_RD_DBUW.lpm_width = lpm_widthu;
31078 dcfifo_fefifo WR_FE (
31079 .usedw_in (w_wr_dbuw),
31084 .empty (w_wrempty),
31086 dcfifo_fefifo RD_FE (
31087 .usedw_in (w_rd_dbuw),
31092 .empty (w_rdempty),
31095 WR_FE.lpm_widthad = lpm_widthu,
31096 WR_FE.lpm_numwords = lpm_numwords,
31097 WR_FE.underflow_checking = underflow_checking,
31098 WR_FE.overflow_checking = overflow_checking,
31099 WR_FE.lpm_mode = "WRITE",
31100 RD_FE.lpm_widthad = lpm_widthu,
31101 RD_FE.lpm_numwords = lpm_numwords,
31102 RD_FE.underflow_checking = underflow_checking,
31103 RD_FE.overflow_checking = overflow_checking,
31104 RD_FE.lpm_mode = "READ";
31106 // ALWAYS CONSTRUCT BLOCK
31107 always @(posedge aclr)
31111 if (!(dev.IS_FAMILY_STRATIX(intended_device_family) ||
31112 dev.IS_FAMILY_STRATIXGX(intended_device_family) ||
31113 dev.IS_FAMILY_CYCLONE(intended_device_family)) ||
31114 (use_eab == "OFF"))
31116 if (lpm_showahead == "ON")
31117 i_q_tmp <= mem_data[0];
31121 else if ((add_ram_output_register == "ON") &&
31122 (dev.IS_FAMILY_STRATIX(intended_device_family) ||
31123 dev.IS_FAMILY_STRATIXGX(intended_device_family) ||
31124 dev.IS_FAMILY_CYCLONE(intended_device_family)))
31126 if (lpm_showahead == "OFF")
31130 i_q_tmp <= {lpm_width{1'bx}};
31132 for (j = 0; j < (1<<lpm_widthu); j = j + 1)
31134 data_ready[i_wrptr_tmp] <= 1'b0;
31135 data_delay_count[k] <= 0;
31139 end // @(posedge aclr)
31142 always @(rdreq or w_rdempty)
31144 if (underflow_checking == "OFF")
31147 i_rden <= rdreq && !w_rdempty;
31148 end // @(rdreq or w_rdempty)
31150 always @(wrreq or w_wrfull)
31152 if (overflow_checking == "OFF")
31155 i_wren <= wrreq && !w_wrfull;
31156 end // @(wrreq or w_wrfull)
31158 always @(posedge wrclk)
31160 if (aclr && (!(dev.IS_FAMILY_STRATIX(intended_device_family) ||
31161 dev.IS_FAMILY_STRATIXGX(intended_device_family) ||
31162 dev.IS_FAMILY_CYCLONE(intended_device_family)) ||
31163 (add_ram_output_register == "ON") || (use_eab == "OFF")))
31169 else if (wrclk && ($time > 0))
31171 i_data_tmp <= data;
31172 i_wrptr_tmp <= i_wrptr;
31173 i_wren_tmp <= i_wren;
31177 if (~aclr && ((i_wrptr < (1<<lpm_widthu)-1) || (overflow_checking == "OFF")))
31178 i_wrptr <= i_wrptr + 1;
31182 if (use_eab == "OFF")
31184 mem_data[i_wrptr] <= data;
31186 if (lpm_showahead == "ON")
31187 i_showahead_flag3 <= 1'b1;
31191 end // @(posedge wrclk)
31193 always @(negedge wrclk)
31195 if ((~wrclk && (use_eab == "ON")) && ($time > 0))
31199 mem_data[i_wrptr_tmp] <= i_data_tmp;
31200 data_ready[i_wrptr_tmp] <= 1'b0;
31203 if ((lpm_showahead == "ON") &&
31204 (!(dev.IS_FAMILY_STRATIX(intended_device_family) ||
31205 dev.IS_FAMILY_STRATIXGX(intended_device_family) ||
31206 dev.IS_FAMILY_CYCLONE(intended_device_family))))
31207 i_showahead_flag3 <= 1'b1;
31209 end // @(negedge wrclk)
31211 always @(posedge rdclk)
31214 if (rdclk && ($time > 0))
31216 if ((lpm_showahead == "ON") && (add_ram_output_register == "ON") &&
31217 (dev.IS_FAMILY_STRATIX(intended_device_family) ||
31218 dev.IS_FAMILY_STRATIXGX(intended_device_family) ||
31219 dev.IS_FAMILY_CYCLONE(intended_device_family)))
31221 for (k = 0; k < (1<<lpm_widthu); k = k + 1)
31223 if (data_ready[k] == 1'b0)
31224 data_delay_count[k] <= data_delay_count[k] + 1;
31226 if (data_delay_count[k] == (rdsync_delaypipe+2))
31228 data_ready[k] = 1'b1;
31229 data_delay_count[k] <= 0;
31235 i_showahead_flag3 <= 1'b1;
31241 if (aclr && (!(dev.IS_FAMILY_STRATIX(intended_device_family) ||
31242 dev.IS_FAMILY_STRATIXGX(intended_device_family) ||
31243 dev.IS_FAMILY_CYCLONE(intended_device_family)) ||
31244 (use_eab == "OFF")))
31246 if (lpm_showahead == "ON")
31247 i_q_tmp <= mem_data[0];
31251 else if (aclr && (add_ram_output_register == "ON") &&
31252 (dev.IS_FAMILY_STRATIX(intended_device_family) ||
31253 dev.IS_FAMILY_STRATIXGX(intended_device_family) ||
31254 dev.IS_FAMILY_CYCLONE(intended_device_family)))
31256 if (lpm_showahead == "ON")
31257 i_q_tmp <= {lpm_width{1'bx}};
31261 else if (rdclk && i_rden && ($time > 0))
31263 if (~aclr && ((i_rdptr < (1<<lpm_widthu)-1) || (underflow_checking == "OFF")))
31264 i_rdptr <= i_rdptr + 1;
31268 if (lpm_showahead == "ON")
31269 i_showahead_flag3 <= 1'b1;
31271 i_q_tmp <= mem_data[i_rdptr];
31273 end // @(posedge rdclk)
31275 always @(i_showahead_flag3)
31277 i_showahead_flag2 <= i_showahead_flag3;
31280 always @(i_showahead_flag2)
31282 i_showahead_flag1 <= i_showahead_flag2;
31285 always @(i_showahead_flag1)
31287 i_showahead_flag <= i_showahead_flag1;
31291 always @(posedge i_showahead_flag)
31293 if ((lpm_showahead == "ON") && (add_ram_output_register == "ON") &&
31294 (dev.IS_FAMILY_STRATIX(intended_device_family) ||
31295 dev.IS_FAMILY_STRATIXGX(intended_device_family) ||
31296 dev.IS_FAMILY_CYCLONE(intended_device_family)))
31298 if (w_rdempty == 1'b0)
31300 if (data_ready[i_rdptr] == 1'b1)
31302 i_q_tmp <= mem_data[i_rdptr];
31303 mem_data2[i_rdptr] <= mem_data[i_rdptr];
31306 i_q_tmp <= mem_data2[i_rdptr];
31310 i_q_tmp <= mem_data[i_rdptr];
31311 i_showahead_flag3 <= 1'b0;
31312 end // @(posedge i_showahead_flag)
31314 // Delays & DFF Pipes
31315 always @(negedge rdclk)
31318 end // @(negedge rdclk)
31320 always @(posedge rdclk)
31324 end // @(posedge rdclk)
31326 always @(i_wrptr or w_ws_dbrp)
31328 i_wr_udwn <= i_wrptr - w_ws_dbrp;
31329 end // @(i_wrptr or w_ws_dbrp)
31331 always @(i_rdptr or w_rs_dbwp)
31333 i_rd_udwn <= w_rs_dbwp - i_rdptr;
31334 end // @(i_rdptr or w_rs_dbwp)
31336 // CONTINOUS ASSIGNMENT
31337 assign q = i_q_tmp;
31338 assign wrfull = w_wrfull;
31339 assign rdfull = w_rdfull;
31340 assign wrempty = w_wrempty;
31341 assign rdempty = w_rdempty;
31342 assign wrusedw = w_wrusedw;
31343 assign rdusedw = w_rdusedw;
31345 endmodule // dcfifo_async
31348 //START_MODULE_NAME------------------------------------------------------------
31350 // Module Name : dcfifo_sync
31352 // Description : Synchronous Dual Clock FIFO
31356 // Results expected:
31358 //END_MODULE_NAME--------------------------------------------------------------
31360 // BEGINNING OF MODULE
31361 `timescale 1 ps / 1 ps
31363 // MODULE DECLARATION
31364 module dcfifo_sync (data, rdclk, wrclk, aclr, rdreq, wrreq,
31365 rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q);
31367 // GLOBAL PARAMETER DECLARATION
31368 parameter lpm_width = 1;
31369 parameter lpm_widthu = 1;
31370 parameter lpm_numwords = 2;
31371 parameter intended_device_family = "APEX20KE";
31372 parameter lpm_showahead = "OFF";
31373 parameter underflow_checking = "ON";
31374 parameter overflow_checking = "ON";
31375 parameter use_eab = "ON";
31376 parameter add_ram_output_register = "OFF";
31378 // INPUT PORT DECLARATION
31379 input [lpm_width-1:0] data;
31386 // OUTPUT PORT DECLARATION
31391 output [lpm_widthu-1:0] rdusedw;
31392 output [lpm_widthu-1:0] wrusedw;
31393 output [lpm_width-1:0] q;
31395 // INTERNAL REGISTERS DECLARATION
31396 reg [lpm_width-1:0] mem_data [(1<<lpm_widthu)-1:0];
31397 reg [lpm_width-1:0] i_data_tmp;
31398 reg [lpm_widthu:0] i_rdptr;
31399 reg [lpm_widthu:0] i_wrptr;
31400 reg [lpm_widthu-1:0] i_wrptr_tmp;
31404 reg i_showahead_flag;
31405 reg i_showahead_flag2;
31410 reg [lpm_widthu:0] i_rdusedw;
31411 reg [lpm_widthu:0] i_wrusedw;
31412 reg [lpm_width-1:0] i_q_tmp;
31414 // INTERNAL WIRE DECLARATION
31415 wire [lpm_widthu:0] w_rdptr_s;
31416 wire [lpm_widthu:0] w_wrptr_s;
31417 wire [lpm_widthu:0] w_wrptr_r;
31419 // LOCAL INTEGER DECLARATION
31423 // COMPONENT INSTANTIATION
31424 ALTERA_DEVICE_FAMILIES dev ();
31426 // INITIAL CONSTRUCT BLOCK
31429 if ((lpm_showahead != "ON") && (lpm_showahead != "OFF"))
31430 $display ("Error! LPM_SHOWAHEAD must be ON or OFF.");
31431 if ((underflow_checking != "ON") && (underflow_checking != "OFF"))
31432 $display ("Error! UNDERFLOW_CHECKING must be ON or OFF.");
31433 if ((overflow_checking != "ON") && (overflow_checking != "OFF"))
31434 $display ("Error! OVERFLOW_CHECKING must be ON or OFF.");
31435 if ((use_eab != "ON") && (use_eab != "OFF"))
31436 $display ("Error! USE_EAB must be ON or OFF.");
31437 if (lpm_numwords > (1 << lpm_widthu))
31438 $display ("Error! LPM_NUMWORDS must be less than or equal to 2**LPM_WIDTHU.");
31439 if((add_ram_output_register != "ON") && (add_ram_output_register != "OFF"))
31440 $display ("Error! add_ram_output_register must be ON or OFF.");
31441 if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
31442 $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
31444 for (i = 0; i < (1 << lpm_widthu); i = i + 1)
31460 if (lpm_numwords == (1 << lpm_widthu))
31461 cnt_mod <= 1 << (lpm_widthu + 1);
31463 cnt_mod <= 1 << lpm_widthu;
31466 // COMPONENT INSTANTIATIONS
31467 dcfifo_dffpipe RDPTR_D (
31472 dcfifo_dffpipe WRPTR_D (
31477 dcfifo_dffpipe WRPTR_E (
31483 RDPTR_D.lpm_delay = 1,
31484 RDPTR_D.lpm_width = lpm_widthu + 1,
31485 WRPTR_D.lpm_delay = 1,
31486 WRPTR_D.lpm_width = lpm_widthu + 1,
31487 WRPTR_E.lpm_delay = 1,
31488 WRPTR_E.lpm_width = lpm_widthu + 1;
31490 // ALWAYS CONSTRUCT BLOCK
31491 always @(posedge aclr)
31495 if (!(dev.IS_FAMILY_STRATIX(intended_device_family) ||
31496 dev.IS_FAMILY_STRATIXGX(intended_device_family) ||
31497 dev.IS_FAMILY_CYCLONE(intended_device_family)) ||
31498 ((add_ram_output_register == "ON") && (use_eab == "OFF")))
31499 if (lpm_showahead == "ON")
31500 i_q_tmp <= mem_data[0];
31503 end // @(posedge aclr)
31506 always @(rdreq or i_rdempty)
31508 if (underflow_checking == "OFF")
31511 i_rden <= rdreq && !i_rdempty;
31512 end // @(rdreq or i_rdempty)
31514 always @(wrreq or i_wrfull)
31516 if (overflow_checking == "OFF")
31519 i_wren <= wrreq && !i_wrfull;
31520 end // @(wrreq or i_wrfull)
31522 always @(posedge wrclk)
31524 if (aclr && (!(dev.IS_FAMILY_STRATIX(intended_device_family) ||
31525 dev.IS_FAMILY_STRATIXGX(intended_device_family) ||
31526 dev.IS_FAMILY_CYCLONE(intended_device_family)) ||
31527 ((add_ram_output_register == "ON") && (use_eab == "OFF"))))
31533 else if (wrclk && ($time > 0))
31535 i_data_tmp <= data;
31536 i_wrptr_tmp <= i_wrptr[lpm_widthu-1:0];
31537 i_wren_tmp <= i_wren;
31541 if (~aclr && (i_wrptr < cnt_mod - 1))
31542 i_wrptr <= i_wrptr + 1;
31546 if (use_eab == "OFF")
31548 mem_data[i_wrptr[lpm_widthu-1:0]] <= data;
31550 if (lpm_showahead == "ON")
31551 i_showahead_flag2 <= 1'b1;
31555 end // @(posedge wrclk)
31557 always @(negedge wrclk)
31559 if ((~wrclk && (use_eab == "ON")) && ($time > 0))
31563 mem_data[i_wrptr_tmp] <= i_data_tmp;
31566 if ((lpm_showahead == "ON") &&
31567 (!( dev.IS_FAMILY_STRATIX(intended_device_family) ||
31568 dev.IS_FAMILY_STRATIXGX(intended_device_family) ||
31569 dev.IS_FAMILY_CYCLONE(intended_device_family))))
31570 i_showahead_flag2 <= 1'b1;
31572 end // @(negedge wrclk)
31574 always @(posedge rdclk)
31576 if (aclr && (!(dev.IS_FAMILY_STRATIX(intended_device_family) ||
31577 dev.IS_FAMILY_STRATIXGX(intended_device_family) ||
31578 dev.IS_FAMILY_CYCLONE(intended_device_family)) ||
31579 ((add_ram_output_register == "ON") && (use_eab == "OFF"))))
31581 if (lpm_showahead == "ON")
31582 i_q_tmp <= mem_data[0];
31586 else if (rdclk && i_rden && ($time > 0))
31588 if (~aclr && (i_rdptr < cnt_mod - 1))
31589 i_rdptr <= i_rdptr + 1;
31593 if ((lpm_showahead == "ON") && (!((use_eab == "ON") &&
31594 (dev.IS_FAMILY_STRATIX(intended_device_family) ||
31595 dev.IS_FAMILY_STRATIXGX(intended_device_family) ||
31596 dev.IS_FAMILY_CYCLONE(intended_device_family)))))
31597 i_showahead_flag2 <= 1'b1;
31599 i_q_tmp <= mem_data[i_rdptr[lpm_widthu-1:0]];
31603 always @(posedge i_showahead_flag)
31605 i_q_tmp <= mem_data[i_rdptr[lpm_widthu-1:0]];
31606 i_showahead_flag2 <= 1'b0;
31607 end // @(posedge i_showahead_flag)
31609 always @(i_showahead_flag2)
31611 i_showahead_flag <= i_showahead_flag2;
31612 end // @(i_showahead_flag2)
31614 // Usedw, Empty, Full
31615 always @(i_rdptr or w_wrptr_s or cnt_mod)
31617 if (w_wrptr_s >= i_rdptr)
31618 i_rdusedw <= w_wrptr_s - i_rdptr;
31620 i_rdusedw <= w_wrptr_s + cnt_mod - i_rdptr;
31621 end // @(i_rdptr or w_wrptr_s)
31623 always @(i_wrptr or w_rdptr_s or cnt_mod)
31625 if (i_wrptr >= w_rdptr_s)
31626 i_wrusedw <= i_wrptr - w_rdptr_s;
31628 i_wrusedw <= i_wrptr + cnt_mod - w_rdptr_s;
31629 end // @(i_wrptr or w_rdptr_s)
31631 always @(i_rdusedw)
31633 if (i_rdusedw == 0)
31638 if (((lpm_numwords == (1 << lpm_widthu)) && i_rdusedw[lpm_widthu]) ||
31639 ((lpm_numwords < (1 << lpm_widthu)) && (i_rdusedw == lpm_numwords)))
31643 end // @(i_rdusedw)
31645 always @(i_wrusedw)
31647 if (i_wrusedw == 0)
31652 if (((lpm_numwords == (1 << lpm_widthu)) && i_wrusedw[lpm_widthu]) ||
31653 ((lpm_numwords < (1 << lpm_widthu)) && (i_wrusedw == lpm_numwords)))
31657 end // @(i_wrusedw)
31659 // CONTINOUS ASSIGNMENT
31660 assign rdempty = i_rdempty;
31661 assign wrempty = i_wrempty;
31662 assign rdfull = i_rdfull;
31663 assign wrfull = i_wrfull;
31664 assign wrusedw = i_wrusedw[lpm_widthu-1:0];
31665 assign rdusedw = i_rdusedw[lpm_widthu-1:0];
31666 assign q = i_q_tmp;
31668 endmodule // dcfifo_sync
31671 //START_MODULE_NAME------------------------------------------------------------
31673 // Module Name : dcfifo_low_latency
31675 // Description : Dual Clocks FIFO with lowest latency. This fifo implements
31676 // the fifo behavior for Stratix II, Cyclone II and Stratix
31677 // showahead area mode (LPM_SHOWAHEAD=ON, ADD_RAM_OUTPUT_REGISTER=OFF)
31681 // Results expected:
31683 //END_MODULE_NAME--------------------------------------------------------------
31685 // BEGINNING OF MODULE
31686 `timescale 1 ps / 1 ps
31688 // MODULE DECLARATION
31689 module dcfifo_low_latency (data, rdclk, wrclk, aclr, rdreq, wrreq,
31690 rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q);
31692 // GLOBAL PARAMETER DECLARATION
31693 parameter lpm_width = 1;
31694 parameter lpm_widthu = 1;
31695 parameter lpm_numwords = 2;
31696 parameter delay_rdusedw = 2;
31697 parameter delay_wrusedw = 2;
31698 parameter rdsync_delaypipe = 1;
31699 parameter wrsync_delaypipe = 1;
31700 parameter intended_device_family = "Stratix";
31701 parameter lpm_showahead = "OFF";
31702 parameter underflow_checking = "ON";
31703 parameter overflow_checking = "ON";
31705 input [lpm_width-1:0] data;
31712 // OUTPUT PORT DECLARATION
31717 output [lpm_widthu-1:0] rdusedw;
31718 output [lpm_widthu-1:0] wrusedw;
31719 output [lpm_width-1:0] q;
31721 // INTERNAL REGISTERS DECLARATION
31722 reg [lpm_width-1:0] mem_data [(1<<lpm_widthu)-1:0];
31723 reg [lpm_width-1:0] i_data_tmp;
31724 reg [lpm_widthu-1:0] i_rdptr_g;
31725 reg [lpm_widthu-1:0] i_wrptr_g;
31726 reg [lpm_widthu-1:0] i_wrptr_g_tmp;
31727 reg [lpm_widthu-1:0] i_wrptr_g1;
31728 reg [lpm_widthu-1:0] i_rdptr_g1p;
31729 reg [lpm_widthu-1:0] i_delayed_wrptr_g;
31736 reg i_rdempty_rreg;
31740 reg [lpm_widthu-1:0] i_rdusedw_tmp;
31741 reg [lpm_widthu-1:0] i_wrusedw_tmp;
31742 reg [lpm_width-1:0] i_q;
31743 reg i_q_is_registered;
31745 // INTERNAL WIRE DECLARATION
31746 wire [lpm_widthu-1:0] i_rs_dgwp;
31747 wire [lpm_widthu-1:0] i_ws_dgrp;
31748 wire [lpm_widthu-1:0] i_rdusedw;
31749 wire [lpm_widthu-1:0] i_wrusedw;
31751 // INTERNAL TRI DECLARATION
31754 // LOCAL INTEGER DECLARATION
31758 // COMPONENT INSTANTIATION
31759 ALTERA_DEVICE_FAMILIES dev ();
31761 // INITIAL CONSTRUCT BLOCK
31764 if ((lpm_showahead != "ON") && (lpm_showahead != "OFF"))
31765 $display ("Error! LPM_SHOWAHEAD must be ON or OFF.");
31766 if ((underflow_checking != "ON") && (underflow_checking != "OFF"))
31767 $display ("Error! UNDERFLOW_CHECKING must be ON or OFF.");
31768 if ((overflow_checking != "ON") && (overflow_checking != "OFF"))
31769 $display ("Error! OVERFLOW_CHECKING must be ON or OFF.");
31770 if (lpm_numwords > (1 << lpm_widthu))
31771 $display ("Error! LPM_NUMWORDS must be less than or equal to 2**LPM_WIDTHU.");
31772 if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
31773 $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
31775 for (i = 0; i < (1 << lpm_widthu); i = i + 1)
31776 mem_data[i] <= {lpm_width{1'bx}};
31782 i_wrptr_g_tmp <= 0;
31784 i_delayed_wrptr_g <= 0;
31787 i_rdempty_rreg <= 1;
31790 i_wrfull_wreg <= 0;
31791 i_q <= {lpm_width{1'bx}};
31793 if (lpm_numwords == (1 << lpm_widthu))
31794 cnt_mod <= 1 << (lpm_widthu + 1);
31796 cnt_mod <= 1 << lpm_widthu;
31798 if ((lpm_showahead == "OFF") &&
31799 ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ||
31800 (dev.IS_FAMILY_CYCLONEII(intended_device_family))))
31801 i_q_is_registered <= 1'b1;
31803 i_q_is_registered <= 1'b0;
31806 // COMPONENT INSTANTIATIONS
31807 dcfifo_dffpipe DP_WS_DGRP (
31813 DP_WS_DGRP.lpm_delay = wrsync_delaypipe,
31814 DP_WS_DGRP.lpm_width = lpm_widthu;
31816 dcfifo_dffpipe DP_RS_DGWP (
31817 .d (i_delayed_wrptr_g),
31822 DP_RS_DGWP.lpm_delay = rdsync_delaypipe,
31823 DP_RS_DGWP.lpm_width = lpm_widthu;
31825 dcfifo_dffpipe DP_RDUSEDW (
31826 .d (i_rdusedw_tmp),
31830 dcfifo_dffpipe DP_WRUSEDW (
31831 .d (i_wrusedw_tmp),
31836 DP_RDUSEDW.lpm_delay = (delay_rdusedw > 2) ? 2 : delay_rdusedw,
31837 DP_RDUSEDW.lpm_width = lpm_widthu,
31838 DP_WRUSEDW.lpm_delay = (delay_wrusedw > 2) ? 2 : delay_wrusedw,
31839 DP_WRUSEDW.lpm_width = lpm_widthu;
31841 // ALWAYS CONSTRUCT BLOCK
31842 always @(posedge aclr)
31849 i_wrptr_g_tmp <= 0;
31851 i_delayed_wrptr_g <= 0;
31854 i_rdempty_rreg <= 1;
31857 i_wrfull_wreg <= 0;
31858 if(i_q_is_registered)
31860 end // @(posedge aclr)
31863 always @(rdreq or i_rdempty)
31865 if (underflow_checking == "OFF")
31868 i_rden <= rdreq && !i_rdempty;
31869 end // @(rdreq or i_rdempty)
31871 always @(wrreq or i_wrfull)
31873 if (overflow_checking == "OFF")
31876 i_wren <= wrreq && !i_wrfull;
31877 end // @(wrreq or i_wrfull)
31879 always @(posedge wrclk)
31881 i_data_tmp <= data;
31882 i_wrptr_g_tmp <= i_wrptr_g;
31883 i_wren_tmp <= i_wren;
31885 if (~aclr && ($time > 0))
31889 if (i_wrptr_g1 < cnt_mod - 1)
31890 i_wrptr_g1 <= i_wrptr_g1 + 1;
31894 i_wrptr_g <= i_wrptr_g1;
31896 i_delayed_wrptr_g <= i_wrptr_g;
31900 always @(negedge wrclk)
31902 if (i_wren_tmp && ($time > 0))
31903 mem_data[i_wrptr_g_tmp] <= i_data_tmp;
31907 always @(posedge rdclk)
31911 if (i_rden && ($time > 0))
31913 if (i_rdptr_g1p < cnt_mod - 1)
31914 i_rdptr_g1p <= i_rdptr_g1p + 1;
31918 i_rdptr_g <= i_rdptr_g1p;
31923 always @(posedge rdclk)
31925 if ((! i_q_is_registered) && ($time > 0))
31927 if (i_rdempty == 1'b1)
31928 i_q <= mem_data[i_rdptr_g];
31930 i_q <= mem_data[i_rdptr_g1p];
31932 else if (~aclr && i_rden && ($time > 0))
31933 i_q <= mem_data[i_rdptr_g];
31936 // Usedw, Empty, Full
31937 always @(i_wrptr_g or i_ws_dgrp or cnt_mod)
31939 if (i_wrptr_g < i_ws_dgrp)
31940 i_wrusedw_tmp <= cnt_mod + i_wrptr_g - i_ws_dgrp;
31942 i_wrusedw_tmp <= i_wrptr_g - i_ws_dgrp;
31943 end // @(i_wrptr_g or i_ws_dgrp)
31945 always @(i_rdptr_g or i_rs_dgwp or cnt_mod)
31947 if (i_rs_dgwp < i_rdptr_g)
31948 i_rdusedw_tmp <= cnt_mod + i_rs_dgwp - i_rdptr_g;
31950 i_rdusedw_tmp <= i_rs_dgwp - i_rdptr_g;
31951 end // @(i_wrptr_g or i_rs_dgwp)
31953 always @(i_wrptr_g1 or i_ws_dgrp)
31955 if (i_wrptr_g1 == i_ws_dgrp)
31959 end // @(i_wrptr_g1 or i_ws_dgrp)
31961 always @(i_rdptr_g or i_rs_dgwp)
31963 if (i_rdptr_g == i_rs_dgwp)
31967 end // @(i_rdptr_g or i_rs_dgwp)
31969 always @(posedge rdclk)
31971 i_rdfull <= i_wrfull_wreg;
31972 i_rdempty_rreg <= i_rdempty;
31973 end // @(posedge rdclk)
31975 always @(posedge wrclk)
31977 i_wrempty <= i_rdempty_rreg;
31978 i_wrfull_wreg <= i_wrfull;
31979 end // @(posedge wrclk)
31981 // CONTINOUS ASSIGNMENT
31982 assign rdempty = i_rdempty;
31983 assign wrempty = i_wrempty;
31984 assign rdfull = i_rdfull;
31985 assign wrfull = i_wrfull;
31986 assign wrusedw = i_wrusedw[lpm_widthu-1:0];
31987 assign rdusedw = i_rdusedw[lpm_widthu-1:0];
31990 endmodule // dcfifo_low_latency
31993 //START_MODULE_NAME------------------------------------------------------------
31995 // Module Name : dcfifo
31997 // Description : Dual Clocks FIFO
32001 // Results expected:
32003 //END_MODULE_NAME--------------------------------------------------------------
32005 // BEGINNING OF MODULE
32006 `timescale 1 ps / 1 ps
32008 // MODULE DECLARATION
32009 module dcfifo ( data, rdclk, wrclk, aclr, rdreq, wrreq,
32010 rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q);
32012 // GLOBAL PARAMETER DECLARATION
32013 parameter lpm_width = 1;
32014 parameter lpm_widthu = 1;
32015 parameter lpm_numwords = 2;
32016 parameter delay_rdusedw = 1;
32017 parameter delay_wrusedw = 1;
32018 parameter rdsync_delaypipe = 3;
32019 parameter wrsync_delaypipe = 3;
32020 parameter intended_device_family = "APEX20KE";
32021 parameter lpm_showahead = "OFF";
32022 parameter underflow_checking = "ON";
32023 parameter overflow_checking = "ON";
32024 parameter clocks_are_synchronized = "FALSE";
32025 parameter use_eab = "ON";
32026 parameter add_ram_output_register = "OFF";
32027 parameter add_width = 1;
32028 parameter lpm_hint = "USE_EAB=ON";
32029 parameter lpm_type = "dcfifo";
32031 // INPUT PORT DECLARATION
32032 input [lpm_width-1:0] data;
32039 // OUTPUT PORT DECLARATION
32044 output [lpm_widthu-1:0] rdusedw;
32045 output [lpm_widthu-1:0] wrusedw;
32046 output [lpm_width-1:0] q;
32048 // INTERNAL WIRE DECLARATION
32061 wire [lpm_widthu-1:0] w_rdusedw_s;
32062 wire [lpm_widthu-1:0] w_wrusedw_s;
32063 wire [lpm_widthu-1:0] w_rdusedw_a;
32064 wire [lpm_widthu-1:0] w_wrusedw_a;
32065 wire [lpm_widthu-1:0] w_rdusedw_l;
32066 wire [lpm_widthu-1:0] w_wrusedw_l;
32067 wire [lpm_width-1:0] w_q_s;
32068 wire [lpm_width-1:0] w_q_a;
32069 wire [lpm_width-1:0] w_q_l;
32071 // INTERNAL TRI DECLARATION
32074 // COMPONENT INSTANTIATIONS
32075 ALTERA_DEVICE_FAMILIES dev ();
32084 .rdfull (w_rdfull_s),
32085 .wrfull (w_wrfull_s),
32086 .rdempty (w_rdempty_s),
32087 .wrempty (w_wrempty_s),
32088 .rdusedw (w_rdusedw_s),
32089 .wrusedw (w_wrusedw_s),
32092 SYNC.lpm_width = lpm_width,
32093 SYNC.lpm_widthu = lpm_widthu,
32094 SYNC.lpm_numwords = lpm_numwords,
32095 SYNC.intended_device_family = intended_device_family,
32096 SYNC.lpm_showahead = lpm_showahead,
32097 SYNC.underflow_checking = underflow_checking,
32098 SYNC.overflow_checking = overflow_checking,
32099 SYNC.use_eab = use_eab,
32100 SYNC.add_ram_output_register = add_ram_output_register;
32102 dcfifo_async ASYNC (
32109 .rdfull (w_rdfull_a),
32110 .wrfull (w_wrfull_a),
32111 .rdempty (w_rdempty_a),
32112 .wrempty (w_wrempty_a),
32113 .rdusedw (w_rdusedw_a),
32114 .wrusedw (w_wrusedw_a),
32117 ASYNC.lpm_width = lpm_width,
32118 ASYNC.lpm_widthu = lpm_widthu,
32119 ASYNC.lpm_numwords = lpm_numwords,
32120 ASYNC.delay_rdusedw = delay_rdusedw,
32121 ASYNC.delay_wrusedw = delay_wrusedw,
32122 ASYNC.rdsync_delaypipe = rdsync_delaypipe,
32123 ASYNC.wrsync_delaypipe = wrsync_delaypipe,
32124 ASYNC.intended_device_family = intended_device_family,
32125 ASYNC.lpm_showahead = lpm_showahead,
32126 ASYNC.underflow_checking = underflow_checking,
32127 ASYNC.overflow_checking = overflow_checking,
32128 ASYNC.use_eab = use_eab,
32129 ASYNC.add_ram_output_register = add_ram_output_register;
32131 dcfifo_low_latency LOWLATENCY (
32138 .rdfull (w_rdfull_l),
32139 .wrfull (w_wrfull_l),
32140 .rdempty (w_rdempty_l),
32141 .wrempty (w_wrempty_l),
32142 .rdusedw (w_rdusedw_l),
32143 .wrusedw (w_wrusedw_l),
32146 LOWLATENCY.lpm_width = lpm_width,
32147 LOWLATENCY.lpm_widthu = lpm_widthu,
32148 LOWLATENCY.lpm_numwords = lpm_numwords,
32149 LOWLATENCY.delay_rdusedw = delay_rdusedw,
32150 LOWLATENCY.delay_wrusedw = delay_wrusedw,
32151 LOWLATENCY.rdsync_delaypipe = (rdsync_delaypipe > 3 ? rdsync_delaypipe - 2 : 1),
32152 LOWLATENCY.wrsync_delaypipe = (wrsync_delaypipe > 3 ? wrsync_delaypipe - 2 : 1),
32153 LOWLATENCY.intended_device_family = intended_device_family,
32154 LOWLATENCY.lpm_showahead = lpm_showahead,
32155 LOWLATENCY.underflow_checking = underflow_checking,
32156 LOWLATENCY.overflow_checking = overflow_checking;
32158 // CONTINOUS ASSIGNMENT
32159 assign rdfull = ((dev.FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family) ||
32160 (dev.FEATURE_FAMILY_STRATIX(intended_device_family) &&
32161 (lpm_showahead == "ON") &&
32162 (add_ram_output_register == "OFF"))) &&
32163 (use_eab == "ON")) ? w_rdfull_l :
32164 (clocks_are_synchronized == "TRUE") ? w_rdfull_s : w_rdfull_a;
32166 assign wrfull = ((dev.FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family) ||
32167 (dev.FEATURE_FAMILY_STRATIX(intended_device_family) &&
32168 (lpm_showahead == "ON") &&
32169 (add_ram_output_register == "OFF"))) &&
32170 (use_eab == "ON")) ? w_wrfull_l :
32171 (clocks_are_synchronized == "TRUE") ? w_wrfull_s : w_wrfull_a;
32173 assign rdempty = ((dev.FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family) ||
32174 (dev.FEATURE_FAMILY_STRATIX(intended_device_family) &&
32175 (lpm_showahead == "ON") &&
32176 (add_ram_output_register == "OFF"))) &&
32177 (use_eab == "ON")) ? w_rdempty_l :
32178 (clocks_are_synchronized == "TRUE") ? w_rdempty_s : w_rdempty_a;
32180 assign wrempty = ((dev.FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family) ||
32181 (dev.FEATURE_FAMILY_STRATIX(intended_device_family) &&
32182 (lpm_showahead == "ON") &&
32183 (add_ram_output_register == "OFF"))) &&
32184 (use_eab == "ON")) ? w_wrempty_l :
32185 (clocks_are_synchronized == "TRUE") ? w_wrempty_s : w_wrempty_a;
32187 assign rdusedw = ((dev.FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family) ||
32188 (dev.FEATURE_FAMILY_STRATIX(intended_device_family) &&
32189 (lpm_showahead == "ON") &&
32190 (add_ram_output_register == "OFF"))) &&
32191 (use_eab == "ON")) ? w_rdusedw_l :
32192 (clocks_are_synchronized == "TRUE") ? w_rdusedw_s : w_rdusedw_a;
32194 assign wrusedw = ((dev.FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family) ||
32195 (dev.FEATURE_FAMILY_STRATIX(intended_device_family) &&
32196 (lpm_showahead == "ON") &&
32197 (add_ram_output_register == "OFF"))) &&
32198 (use_eab == "ON")) ? w_wrusedw_l :
32199 (clocks_are_synchronized == "TRUE") ? w_wrusedw_s : w_wrusedw_a;
32201 assign q = ((dev.FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family) ||
32202 (dev.FEATURE_FAMILY_STRATIX(intended_device_family) &&
32203 (lpm_showahead == "ON") &&
32204 (add_ram_output_register == "OFF"))) &&
32205 (use_eab == "ON")) ? w_q_l :
32206 (clocks_are_synchronized == "TRUE") ? w_q_s : w_q_a;
32208 endmodule // dcfifo
32211 //--------------------------------------------------------------------------
32212 // Module Name : altshift_taps
32214 // Description : Parameterized shift register with taps megafunction.
32215 // Implements a RAM-based shift register for efficient
32216 // creation of very large shift registers
32218 // Limitation : This megafunction is provided only for backward
32219 // compatibility in Cyclone, Stratix, and Stratix GX
32222 // Results expected : Produce output from the end of the shift register
32223 // and from the regularly spaced taps along the
32226 //--------------------------------------------------------------------------
32227 `timescale 1 ps / 1 ps
32229 // MODULE DECLARATION
32230 module altshift_taps (shiftin, clock, clken, shiftout, taps);
32232 // PARAMETER DECLARATION
32233 parameter number_of_taps = 4; // Specifies the number of regularly spaced
32234 // taps along the shift register
32235 parameter tap_distance = 3; // Specifies the distance between the
32236 // regularly spaced taps in clock cycles
32237 // This number translates to the number of
32238 // memory words that will be needed
32239 parameter width = 8; // Specifies the width of the input pattern
32240 parameter power_up_state = "CLEARED";
32241 parameter lpm_type = "altshift_taps";
32242 parameter lpm_hint = "UNUSED";
32244 // Following parameters are used as constant
32245 parameter RAM_WIDTH = width * number_of_taps;
32246 parameter TOTAL_TAP_DISTANCE = number_of_taps * tap_distance;
32248 // INPUT PORT DECLARATION
32249 input [width-1:0] shiftin; // Data input to the shifter
32250 input clock; // Positive-edge triggered clock
32251 input clken; // Clock enable for the clock port
32253 // OUTPUT PORT DECLARATION
32254 output [width-1:0] shiftout; // Output from the end of the shift
32256 output [RAM_WIDTH-1:0] taps; // Output from the regularly spaced taps
32257 // along the shift register
32259 // INTERNAL REGISTERS DECLARATION
32260 reg [width-1:0] shiftout;
32261 reg [RAM_WIDTH-1:0] taps;
32262 reg [width-1:0] shiftout_tmp;
32263 reg [RAM_WIDTH-1:0] taps_tmp;
32264 reg [width-1:0] contents [0:TOTAL_TAP_DISTANCE-1];
32266 // LOCAL INTEGER DECLARATION
32267 integer head; // pointer to memory
32268 integer i; // for loop index
32269 integer j; // for loop index
32270 integer k; // for loop index
32273 // TRI STATE DECLARATION
32276 // INITIAL CONSTRUCT BLOCK
32280 if (power_up_state == "CLEARED")
32284 for (i = 0; i < TOTAL_TAP_DISTANCE; i = i + 1)
32288 for (j = 0; j < RAM_WIDTH; j = j + 1)
32296 // ALWAYS CONSTRUCT BLOCK
32297 always @(posedge clock)
32301 contents[head] = shiftin;
32302 head = (head + 1) % TOTAL_TAP_DISTANCE;
32303 shiftout_tmp = contents[head];
32307 for (k=0; k < number_of_taps; k=k+1)
32309 place = (((number_of_taps - k - 1) * tap_distance) + head ) %
32310 TOTAL_TAP_DISTANCE;
32311 taps_tmp = taps_tmp | (contents[place] << (k * width));
32316 always @(shiftout_tmp)
32318 shiftout <= shiftout_tmp;
32326 endmodule // altshift_taps
32328 //START_MODULE_NAME------------------------------------------------------------
32330 // Module Name : a_graycounter
32332 // Description : Gray counter with Count-enable, Up/Down, aclr and sclr
32334 // Limitation : Sync sigal priority: clk_en (higher),sclr,cnt_en (lower)
32336 // Results expected: q is graycounter output and qbin is normal counter
32338 //END_MODULE_NAME--------------------------------------------------------------
32340 // BEGINNING OF MODULE
32341 `timescale 1 ps / 1 ps
32343 // MODULE DECLARATION
32344 module a_graycounter (clock, cnt_en, clk_en, updown, aclr, sclr,
32346 // GLOBAL PARAMETER DECLARATION
32347 parameter width = 3;
32348 parameter pvalue = 0;
32349 parameter lpm_hint = "UNUSED";
32350 parameter lpm_type = "a_graycounter";
32352 // INPUT PORT DECLARATION
32360 // OUTPUT PORT DECLARATION
32361 output [width-1:0] q;
32362 output [width-1:0] qbin;
32364 // INTERNAL REGISTERS DECLARATION
32365 reg [width-1:0] cnt;
32367 // INTERNAL TRI DECLARATION
32374 // LOCAL INTEGER DECLARATION
32376 // COMPONENT INSTANTIATIONS
32378 // INITIAL CONSTRUCT BLOCK
32382 $display ("Error! WIDTH of a_greycounter must be greater than 0.");
32387 // ALWAYS CONSTRUCT BLOCK
32388 always @(posedge aclr or posedge clock)
32409 // CONTINOUS ASSIGNMENT
32411 assign q = cnt ^ (cnt >>1);
32413 endmodule // a_graycounter
32417 //--------------------------------------------------------------------------
32419 //--------------------------------------------------------------------------
32421 `timescale 1 ps / 1 ps
32422 module alt_exc_dpram (portadatain,
32436 // default parameters
32437 parameter operation_mode = "SINGLE_PORT" ;
32438 parameter addrwidth = 14 ;
32439 parameter width = 32 ;
32440 parameter depth = 16384 ;
32441 parameter ramblock = 65535 ;
32442 parameter output_mode = "UNREG" ;
32443 parameter lpm_file = "NONE" ;
32444 parameter lpm_type = "alt_exc_dpram";
32445 parameter lpm_hint = "UNUSED";
32447 // size of memory array
32449 reg [width-1:0] dpram_content[depth-1:0];
32451 // input/output signals
32460 input [width-1:0] portadatain ;
32461 input [width-1:0] portbdatain ;
32463 input [addrwidth-1:0] portaaddr ;
32464 input [addrwidth-1:0] portbaddr ;
32466 output [width-1:0] portadataout ,
32469 // internal signals/registers
32471 reg portaclk_in_last ;
32472 reg portbclk_in_last ;
32481 wire [width-1:0] portadatain_in ;
32482 wire [width-1:0] portbdatain_in ;
32483 wire [width-1:0] portadatain_tmp ;
32484 wire [width-1:0] portbdatain_tmp ;
32486 wire [addrwidth-1:0] portaaddr_in ;
32487 wire [addrwidth-1:0] portbaddr_in ;
32489 reg [width-1:0] portadataout_tmp ;
32490 reg [width-1:0] portbdataout_tmp ;
32491 reg [width-1:0] portadataout_reg ;
32492 reg [width-1:0] portbdataout_reg ;
32493 reg [width-1:0] portadataout_reg_out ;
32494 reg [width-1:0] portbdataout_reg_out ;
32495 wire [width-1:0] portadataout_tmp2 ;
32496 wire [width-1:0] portbdataout_tmp2 ;
32498 reg portawe_latched ;
32499 reg portbwe_latched ;
32500 reg [addrwidth-1:0] portaaddr_latched ;
32501 reg [addrwidth-1:0] portbaddr_latched ;
32503 // assign to internal signals
32505 assign portadatain_in = portadatain;
32506 assign portaaddr_in = portaaddr;
32507 assign portaena_in = portaena;
32508 assign portaclk_in = portaclk;
32509 assign portawe_in = portawe;
32511 assign portbdatain_in = portbdatain;
32512 assign portbaddr_in = portbaddr;
32513 assign portbena_in = portbena;
32514 assign portbclk_in = portbclk;
32515 assign portbwe_in = portbwe;
32518 // Dual Port Contention Port A address = Port B address
32520 // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+
32521 // | Port A | Port B | A Data In | B Data In | A Data Out | B Data Out | Memory State |
32522 // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+
32523 // | read | read | DA | DB | memory | memory | no change |
32524 // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+
32525 // | write | read | DA | DB | unknown | unknown | memory <= DA |
32526 // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+
32527 // | read | write | DA | DB | unknown | unknown | memory <= DB |
32528 // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+
32529 // | write | write | DA | DB | unknown | unknown | memory <= unknown |
32530 // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+
32532 // Dual Port Contention Port A address != Port B address
32534 // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+
32535 // | Port A | Port B | A Data In | B Data In | A Data Out | B Data Out | Memory State |
32536 // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+
32537 // | read | read | DA | DB | mem[A_addr] | mem[B_Addr] | no change |
32538 // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+
32539 // | write | read | DA | DB | unknown | mem[B_Addr] | mem[A_Addr] <= DA |
32540 // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+
32541 // | read | write | DA | DB | mem[A_addr] | unknown | mem[B_Addr] <= DB |
32542 // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+
32543 // | write | write | DA | DB | unknown | unknown | mem[A_Addr] <= DA |
32544 // | | | | | | | mem[B_Addr] <= DB |
32545 // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+
32547 // NB: Output state is always unknown when writing.
32552 // Initialise dpram memory contents from file (if filename specified).
32553 if (lpm_file != "NONE" && lpm_file != "none") $readmemh(lpm_file, dpram_content);
32555 portaclk_in_last = 0;
32556 portbclk_in_last = 0;
32559 always @(portaclk_in)
32561 if (portaclk_in != 0 && portaclk_in_last == 0) // rising edge port a clock
32564 portawe_latched = portawe_in ;
32565 portaaddr_latched = portaaddr_in ;
32567 if (portawe_latched == 'b0)
32572 if (portaaddr_latched == portbaddr_latched && portbwe_latched != 'b0)
32575 // B simultaneously writing to same address (effect of B write to memory handled below)
32577 portadataout_reg = portadataout_tmp;
32578 portadataout_tmp = 'bx;
32584 // B reading from same address, or reading/writing to different address.
32586 portadataout_reg = portadataout_tmp;
32587 portadataout_tmp = dpram_content[portaaddr_latched];
32597 if (portaaddr_latched == portbaddr_latched && portawe_latched != 'b0 && portbwe_latched != 'b0)
32600 // A and B simultaneously writing to same address
32602 portadataout_reg = portadataout_tmp ;
32603 dpram_content[portaaddr_latched] = 'bx ;
32604 portadataout_tmp = 'bx ;
32610 // B reading from same address or reading/writing to different address
32612 portadataout_reg = portadataout_tmp;
32613 dpram_content[portaaddr_latched] = portadatain_tmp ;
32614 portadataout_tmp = 'bx ;
32617 end // writing to A
32618 end // rising edge port a clock
32619 portaclk_in_last = portaclk_in;
32620 end // portaclk_in change event
32622 always @(portbclk_in)
32624 if (portbclk_in != 0 && portbclk_in_last == 0 && (operation_mode == "DUAL_PORT" || operation_mode == "dual_port")) // rising edge port b clock
32627 portbwe_latched = portbwe_in ;
32628 portbaddr_latched = portbaddr_in ;
32630 if (portbwe_latched == 'b0)
32635 if (portbaddr_latched == portaaddr_latched && portawe_latched != 'b0)
32638 // A simultaneously writing to same address (effect of A write to memory handled above)
32640 portbdataout_reg = portbdataout_tmp;
32641 portbdataout_tmp = 'bx;
32647 // A reading from same address, or reading/writing to different address.
32649 portbdataout_reg = portbdataout_tmp;
32650 portbdataout_tmp = dpram_content[portbaddr_latched];
32659 if (portbaddr_latched == portaaddr_latched && portbwe_latched != 'b0 && portawe_latched != 'b0)
32662 // B and A simultaneously writing to same address
32664 portbdataout_reg = portbdataout_tmp ;
32665 dpram_content[portbaddr_latched] = 'bx ;
32666 portbdataout_tmp = 'bx ;
32672 // A reading from same address or reading/writing to different address
32674 portbdataout_reg = portbdataout_tmp;
32675 dpram_content[portbaddr_latched] = portbdatain_tmp ;
32676 portbdataout_tmp = 'bx ;
32679 end // writing to B
32680 end // rising edge port B clock
32682 portbclk_in_last = portbclk_in;
32684 end // portbclk_in change event
32686 // registered Port A output enabled ?
32688 always @(portaena_in or portadataout_reg)
32690 if (output_mode == "REG" || output_mode == "reg")
32691 if ( portaena_in == 1'b1 )
32692 portadataout_reg_out = portadataout_reg ;
32695 // registered Port B output enabled ?
32697 always @(portbena_in or portbdataout_reg)
32699 if (output_mode == "REG" || output_mode == "reg")
32700 if ( portbena_in == 1'b1 )
32701 portbdataout_reg_out = portbdataout_reg ;
32704 // Registered or Unregistered mode ?
32706 assign portadataout_tmp2 = (output_mode == "REG" || output_mode == "reg") ? portadataout_reg_out[width-1:0] : portadataout_tmp[width-1:0];
32707 assign portbdataout_tmp2 = (output_mode == "REG" || output_mode == "reg") ? portbdataout_reg_out[width-1:0] : portbdataout_tmp[width-1:0];
32709 assign portadatain_tmp[width-1:0] = portadatain;
32710 assign portbdatain_tmp[width-1:0] = portbdatain;
32712 assign portadataout = portadataout_tmp2;
32713 assign portbdataout = portbdataout_tmp2;
32716 endmodule // alt_exc_dpram
32718 //--------------------------------------------------------------------------
32720 //--------------------------------------------------------------------------
32722 `timescale 1 ps / 1 ps
32724 module alt_exc_upcore (
32725 intpld, intuart, inttimer0, inttimer1, intcommtx, intcommrx, intproctimer, intprocbridge,
32726 debugrq, debugext0, debugext1, debugiebrkpt, debugdewpt, debugextin, debugack,
32727 debugrng0, debugrng1, debugextout,
32730 slavehwrite, slavehreadyi, slavehselreg, slavehsel, slavehmastlock, slavehaddr,
32731 slavehwdata, slavehtrans, slavehsize, slavehburst, slavehreadyo, slavebuserrint,
32732 slavehrdata, slavehresp,
32735 masterhrdata, masterhresp, masterhwrite, masterhlock, masterhbusreq, masterhaddr,
32736 masterhwdata, masterhtrans, masterhsize, masterhready, masterhburst, masterhgrant,
32738 lockreqdp0, lockreqdp1,
32739 lockgrantdp0, lockgrantdp1,
32741 ebiack, ebiwen, ebioen, ebiclk, ebibe, ebicsn, ebiaddr, ebidq,
32743 uarttxd, uartrtsn, uartdtrn, uartctsn, uartdsrn, uartrxd, uartdcdn,
32746 sdramclk, sdramclkn, sdramclke, sdramwen, sdramcasn, sdramrasn, sdramdqm,
32747 sdramaddr, sdramdq, sdramdqs, sdramcsn,
32750 intextpin, traceclk, tracesync, tracepipestat, tracepkt, clk_ref, intnmi, perreset,
32751 npor, nreset, gpi, gpo
32754 parameter processor = "ARM";
32755 parameter source = "";
32756 parameter sdram_width = 32;
32757 parameter sdramdqm_width = 4;
32758 parameter gpio_width = 4;
32759 parameter lpm_type = "alt_exc_upcore";
32760 parameter lpm_hint = "UNUSED";
32762 // AHB2 Master and Slave bridges
32763 // Interupt, debug and trace ports
32766 input slavehclk, masterhclk;
32768 input slavehwrite, slavehreadyi, slavehselreg, slavehsel,
32769 slavehmastlock, masterhready, masterhgrant;
32771 input lockreqdp0, lockreqdp1,
32772 debugrq, debugext0, debugext1, debugiebrkpt, debugdewpt;
32774 input [31:0] slavehaddr, slavehwdata, masterhrdata;
32775 input [1:0] slavehtrans, slavehsize, masterhresp;
32776 input [3:0] debugextin;
32777 input [5:0] intpld;
32778 input [2:0] slavehburst;
32780 output masterhwrite, masterhlock, masterhbusreq, slavehreadyo, slavebuserrint,
32781 intuart, inttimer0, inttimer1, intcommtx, intcommrx,
32782 debugack, debugrng0, debugrng1,
32783 lockgrantdp0, lockgrantdp1;
32785 output [31:0] masterhaddr, masterhwdata, slavehrdata;
32786 output [1:0] masterhtrans, masterhsize, slavehresp;
32787 output [2:0] masterhburst;
32788 output [3:0] debugextout;
32790 // Shared IO connections
32791 // EBI Expansion bus
32793 // UART and trace port
32796 output ebiwen, ebioen, ebiclk;
32797 output [1:0] ebibe;
32798 output [3:0] ebicsn;
32799 output [24:0] ebiaddr;
32800 inout [15:0] ebidq;
32802 input uartctsn, uartdsrn, uartrxd;
32803 output uarttxd, uartrtsn, uartdtrn;
32804 inout uartdcdn, uartrin;
32806 output sdramclk, sdramclkn, sdramclke,
32807 sdramwen, sdramcasn, sdramrasn;
32808 output [1:0] sdramcsn;
32809 output [sdramdqm_width-1:0] sdramdqm;
32810 output [14:0] sdramaddr;
32812 inout [sdram_width-1:0] sdramdq;
32813 inout [sdramdqm_width-1:0] sdramdqs;
32816 output traceclk, tracesync;
32817 output [2:0] tracepipestat;
32818 output [15:0] tracepkt;
32820 input clk_ref, npor;
32822 output intproctimer, intprocbridge;
32825 input [gpio_width-1:0] gpi;
32826 output [gpio_width-1:0] gpo;
32829 /////////////////////////////////////////////////////////////////////////////////////////////////
32831 /////////////////////////////////////////////////////////////////////////////////////////////////
32833 // responses (HRESP)
32834 `define H_OKAY 2'b00
32835 `define H_ERROR 2'b01
32836 `define H_RETRY 2'b10
32837 `define H_SPLIT 2'b11
32839 // transcation types (HTRANS)
32840 `define H_IDLE 2'b00
32841 `define H_BUSY 2'b01
32842 `define H_NONSEQ 2'b10
32843 `define H_SEQ 2'b11
32845 // burst mode (HBURST)
32846 `define H_SINGLE 3'b000
32847 `define H_INCR 3'b001
32848 `define H_WRAP4 3'b010
32849 `define H_INCR4 3'b011
32850 `define H_WRAP8 3'b100
32851 `define H_INCR8 3'b101
32852 `define H_WRAP16 3'b110
32853 `define H_INCR16 3'b111
32855 // transaction sizes (HSIZE 8,16,32 bits -- larger sizes not supported)
32856 `define H_BYTE 2'b00
32857 `define H_HWORD 2'b01
32858 `define H_WORD 2'b10
32860 /////////////////////////////////////////////////////////////////////////////////////////////////
32862 /////////////////////////////////////////////////////////////////////////////////////////////////
32865 wire slavehwrite_in, slavehreadyi_in, slavehselreg_in, slavehsel_in,
32867 wire [31:0] slavehaddr_in, slavehwdata_in;
32868 wire [1:0] slavehtrans_in, slavehsize_in;
32869 wire [2:0] slavehburst_in;
32870 wire slavehreadyo_out, slavebuserrint_out;
32871 wire [31:0] slavehrdata_out;
32872 wire [1:0] slavehresp_out;
32875 assign slavehclk_in = slavehclk ;
32876 assign slavehwrite_in = slavehwrite ;
32877 assign slavehreadyi_in = slavehreadyi ;
32878 assign slavehselreg_in = slavehselreg ;
32879 assign slavehsel_in = slavehsel ;
32880 assign slavehmastlock_in = slavehmastlock;
32882 assign slavehaddr_in = slavehaddr;
32884 assign slavehwdata_in = slavehwdata;
32886 assign slavehtrans_in = slavehtrans;
32887 assign slavehsize_in = slavehsize;
32888 assign slavehburst_in = slavehburst;
32891 assign slavehreadyo = slavehreadyo_out;
32892 assign slavebuserrint= slavebuserrint_out;
32894 assign slavehrdata = slavehrdata_out;
32895 assign slavehresp = slavehresp_out;
32897 /////////////////////////////////////////////////////////////////////////////////////////////////
32898 /////////////////////////////////////////////////////////////////////////////////////////////////
32901 reg slavehreadyo_out_r ;
32902 reg [1:0] slavehresp_out_r ;
32904 assign slavehreadyo_out = slavehreadyo_out_r ;
32905 assign slavehresp_out = slavehresp_out_r ;
32908 // record of address and control information (latched on address phase)
32909 reg [31:0] startReg; // start address for burst
32910 reg [31:0] addrReg;
32911 reg [1:0] transReg;
32914 reg [2:0] burstReg;
32918 // Implement 6 banks of 256K = (1.5MB of address space)
32919 // ///////////////////////////////////////////////////////////////////
32920 reg [79:0] memCfg[0:5]; // slavememory.cfg.dat
32921 reg [31:0] memStart[0:5];
32922 reg [31:0] memEnd[0:5];
32923 reg [7:0] memWaitStart[0:5];
32924 reg [7:0] memWait[0:5];
32925 reg [31:0] memMapA[0:65535]; // slavememory.0.dat
32926 reg [31:0] memMapB[0:65535];
32927 reg [31:0] memMapC[0:65535];
32928 reg [31:0] memMapD[0:65535];
32929 reg [31:0] memMapE[0:65535];
32930 reg [31:0] memMapF[0:65535]; // slavememory.5.dat
32935 integer output_file ;
32939 // Open the results file
32940 output_file = $fopen("output.dat") ;
32941 if ( !output_file )
32942 $display("ERROR: Cannot open Output File") ;
32945 // Initialise memory banks from config and map files
32946 //////////////////////////////////////////////////////////////////////
32947 temp=80'h00000000_00000000_00_00;
32948 for (memBank=0;memBank<6;memBank=memBank+1)
32950 memCfg[memBank]=temp;
32953 // 79..48 start address
32954 // 47..16 end address
32955 // 15...8 wait states on first access
32956 // 7...0 wait states per cycle
32957 $readmemh("slavememory.cfg.dat", memCfg);
32958 for (memBank=0;memBank<6;memBank=memBank+1)
32960 temp=memCfg[memBank];
32961 memStart[memBank] =temp[79:48];
32962 memEnd[memBank] =temp[47:16];
32963 memWaitStart[memBank] =temp[15:8];
32964 memWait[memBank] =temp[7:0];
32967 if (memStart[0]!=memEnd[0]) $readmemh("slavememory.0.dat", memMapA);
32968 if (memStart[1]!=memEnd[1]) $readmemh("slavememory.1.dat", memMapB);
32969 if (memStart[2]!=memEnd[2]) $readmemh("slavememory.2.dat", memMapC);
32970 if (memStart[3]!=memEnd[3]) $readmemh("slavememory.3.dat", memMapD);
32971 if (memStart[4]!=memEnd[4]) $readmemh("slavememory.4.dat", memMapE);
32972 if (memStart[5]!=memEnd[5]) $readmemh("slavememory.5.dat", memMapF);
32973 //////////////////////////////////////////////////////////////////////
32979 burstReg=`H_NONSEQ;
32982 slavehresp_out_r=`H_OKAY;
32987 wire sel = slavehsel_in & slavehreadyi_in;
32989 // determine if the transaction includes an operation / a "busy"
32990 wire doWork = selReg & ((transReg==`H_NONSEQ || transReg==`H_SEQ) ? 1'b1 : 1'b0);
32991 wire doBusyWork = selReg & ( transReg==`H_BUSY ? 1'b1 : 1'b0);
32994 // BURST MODE SUPPORT
32995 ///////////////////////////////////////////////////////////////////////////////
32997 // If we are in burst mode we'll compute our own address and control settings
32998 // based on the spec.
33000 // compute values SEQuential (burst) transfers
33001 wire seqTrans = ( selReg &
33002 ( doWork | doBusyWork) &
33003 ( (slavehtrans_in==`H_SEQ || slavehtrans_in==`H_BUSY) ) ? 1'b1 : 1'b0 );
33006 // mask to determine which bits are retained from the start address
33007 wire [31:0] wrapmask;
33009 ( burstReg==`H_WRAP4 ? {32{1'b1}} << 2: // all but 2
33010 ( burstReg==`H_WRAP8 ? {32{1'b1}} << 3: // all but 3
33011 ( burstReg==`H_WRAP16 ? {32{1'b1}} << 4: // all but 4
33012 {32{1'b0}} ) )); // none
33013 wire [31:0] wrapmask_w;
33014 assign wrapmask_w = // correct for word size
33015 ( sizeReg==`H_WORD ? wrapmask<<2 :
33016 ( sizeReg==`H_HWORD ? wrapmask<<1 :
33017 /* H_BYTE */ wrapmask ));
33019 wire [31:0] seqPlusAddr; // work out the next sequential address
33020 assign seqPlusAddr =
33021 ( burstReg == `H_SINGLE) ? addrReg :
33022 addrReg + ( sizeReg==`H_BYTE ? 1 :
33023 ( sizeReg==`H_HWORD ? 2 :
33024 ( sizeReg==`H_WORD ? 4 : 0) ) ) ;
33026 wire [31:0] seqAddr; // apply the mask to wrap at boundaries
33027 assign seqAddr = (slavehtrans_in==`H_BUSY) ? addrReg :
33028 ( (startReg&wrapmask_w) | (seqPlusAddr&~wrapmask_w));
33031 // if this is a sequential transaction only sample HTRANS
33032 wire [31:0] startNext;
33033 wire [31:0] addrNext;
33034 wire [1:0] transNext;
33035 wire [1:0] sizeNext;
33036 wire [2:0] burstNext;
33039 assign startNext = seqTrans ? startReg : slavehaddr_in;
33040 assign addrNext = seqTrans ? seqAddr : slavehaddr_in;
33041 assign transNext = slavehtrans_in;
33042 assign sizeNext = seqTrans ? sizeReg : slavehsize_in;
33043 assign burstNext = seqTrans ? burstReg : slavehburst_in;
33044 assign writeNext = seqTrans ? writeReg : slavehwrite_in;
33047 // Latch the control data if we are selected
33048 ///////////////////////////////////////////////////////////////////////////////////
33049 always @ (posedge slavehclk_in)
33051 // if readin is low another device is wait stating its
33052 // data phase and hence extending our address phase
33053 if (slavehreadyi_in)
33056 if (sel) // latch the control data
33058 startReg <= startNext;
33059 addrReg <= addrNext;
33060 transReg <= transNext;
33061 sizeReg <= sizeNext;
33062 writeReg <= writeNext;
33063 burstReg <= burstNext;
33069 transReg <= `H_IDLE;
33070 sizeReg <= `H_WORD;
33072 burstReg <= `H_SINGLE;
33078 // Implment memory banks
33079 ///////////////////////////////////////////////////////////////////////////////////
33081 wire bankA = ( addrReg>=memStart[0] && addrReg<=memEnd[0] && memStart[0]!=memEnd[0]) ? 1'b1 : 1'b0;
33082 wire bankB = ( addrReg>=memStart[1] && addrReg<=memEnd[1] && memStart[1]!=memEnd[1]) ? 1'b1 : 1'b0;
33083 wire bankC = ( addrReg>=memStart[2] && addrReg<=memEnd[2] && memStart[2]!=memEnd[2]) ? 1'b1 : 1'b0;
33084 wire bankD = ( addrReg>=memStart[3] && addrReg<=memEnd[3] && memStart[3]!=memEnd[3]) ? 1'b1 : 1'b0;
33085 wire bankE = ( addrReg>=memStart[4] && addrReg<=memEnd[4] && memStart[4]!=memEnd[4]) ? 1'b1 : 1'b0;
33086 wire bankF = ( addrReg>=memStart[5] && addrReg<=memEnd[5] && memStart[5]!=memEnd[5]) ? 1'b1 : 1'b0;
33088 // byte offset into bank //word offset into bank
33089 wire [31:0] offsetA = addrReg-memStart[0]; wire [15:0] wordA = offsetA[17:2];
33090 wire [31:0] offsetB = addrReg-memStart[1]; wire [15:0] wordB = offsetB[17:2];
33091 wire [31:0] offsetC = addrReg-memStart[2]; wire [15:0] wordC = offsetC[17:2];
33092 wire [31:0] offsetD = addrReg-memStart[3]; wire [15:0] wordD = offsetD[17:2];
33093 wire [31:0] offsetE = addrReg-memStart[4]; wire [15:0] wordE = offsetE[17:2];
33094 wire [31:0] offsetF = addrReg-memStart[5]; wire [15:0] wordF = offsetF[17:2];
33097 wire [31:0] dataA = memMapA[wordA];
33098 wire [31:0] dataB = memMapB[wordB];
33099 wire [31:0] dataC = memMapC[wordC];
33100 wire [31:0] dataD = memMapD[wordD];
33101 wire [31:0] dataE = memMapE[wordE];
33102 wire [31:0] dataF = memMapF[wordF];
33104 reg [31:0] currentVal;
33105 always @(dataA or dataB or dataC or dataD or dataE or dataF or
33106 bankA or bankB or bankC or bankD or bankE or bankF )
33108 if (bankA) currentVal=dataA;
33109 else if (bankB) currentVal=dataB;
33110 else if (bankC) currentVal=dataC;
33111 else if (bankD) currentVal=dataD;
33112 else if (bankE) currentVal=dataE;
33113 else if (bankF) currentVal=dataF;
33118 wire be0 = (sizeReg==`H_WORD ||
33119 (sizeReg==`H_HWORD && addrReg[1]==1'b0) ||
33120 (sizeReg==`H_BYTE && addrReg[1:0]==2'b00) ) ? 1'b1 : 1'b0;
33121 wire be1 = (sizeReg==`H_WORD ||
33122 (sizeReg==`H_HWORD && addrReg[1]==1'b0) ||
33123 (sizeReg==`H_BYTE && addrReg[1:0]==2'b01) ) ? 1'b1 : 1'b0;
33124 wire be2 = (sizeReg==`H_WORD ||
33125 (sizeReg==`H_HWORD && addrReg[1]==1'b1) ||
33126 (sizeReg==`H_BYTE && addrReg[1:0]==2'b10) ) ? 1'b1 : 1'b0;
33127 wire be3 = (sizeReg==`H_WORD ||
33128 (sizeReg==`H_HWORD && addrReg[1]==1'b1) ||
33129 (sizeReg==`H_BYTE && addrReg[1:0]==2'b11) ) ? 1'b1 : 1'b0;
33131 wire [31:0] readDataMask = {be3 ? 8'hFF : 8'h00,
33132 be2 ? 8'hFF : 8'h00,
33133 be1 ? 8'hFF : 8'h00,
33134 be0 ? 8'hFF : 8'h00 };
33138 // wait state generation
33139 ///////////////////////////////////////////////////////////////////////////////////
33141 reg s_addr_latch; // address latched this cycle
33142 reg [7:0] waitStart;
33150 always @(bankA or bankB or bankC or bankD or bankE or bankF )
33152 if (bankA) waitStart = memWaitStart[0];
33153 else if (bankB) waitStart = memWaitStart[1];
33154 else if (bankC) waitStart = memWaitStart[2];
33155 else if (bankD) waitStart = memWaitStart[3];
33156 else if (bankE) waitStart = memWaitStart[4];
33157 else if (bankF) waitStart = memWaitStart[5];
33160 always @(bankA or bankB or bankC or bankD or bankE or bankF )
33162 if (bankA) waitSeq = memWait[0];
33163 else if (bankB) waitSeq = memWait[1];
33164 else if (bankC) waitSeq = memWait[2];
33165 else if (bankD) waitSeq = memWait[3];
33166 else if (bankE) waitSeq = memWait[4];
33167 else if (bankF) waitSeq = memWait[5];
33173 // first beat and memWaitStart and addr has just been latched
33175 // first beat and waitReg (more than 1 wait state)
33177 // seq beat and waitReg
33181 always @(posedge slavehclk_in)
33182 s_addr_latch <= slavehreadyi_in & slavehsel_in;
33184 always @(doWork or transReg or waitReg or waitStart or s_addr_latch)
33186 if ( doWork & (transReg==`H_NONSEQ) & (waitStart!=8'h00) & s_addr_latch )
33188 slavehreadyo_out_r = 1'b0;
33189 // $fdisplay(output_file, "SLAVE: wait on first" );
33191 else if ( doWork & (transReg==`H_NONSEQ) & waitReg!=8'h00 )
33193 slavehreadyo_out_r = 1'b0;
33194 // $fdisplay(output_file, "SLAVE: wait" );
33196 else if (doWork & (transReg==`H_SEQ) & (waitReg!=8'h00))
33198 slavehreadyo_out_r = 1'b0;
33199 // $fdisplay(output_file, "SLAVE: wait" );
33202 slavehreadyo_out_r = 1'b1;
33206 // if we are waiting (waitReg>0) and not in a busy decrement the counter
33207 // otherwise get the new value from memWait of memWaitStart according to
33208 // the transaction type
33210 wire [7:0] waitStartNext;
33211 assign waitStartNext = ( waitStart>8'h01 ? (waitStart-1) : 8'h00);
33213 always @ (posedge slavehclk_in)
33214 waitReg<= (waitReg!=8'h00 & ~doBusyWork) ? (waitReg - 1'b1) :
33215 ( doWork & (transReg==`H_NONSEQ) & (waitStart!=8'h00) & s_addr_latch ? waitStartNext :
33216 ( seqTrans ? waitSeq : 8'h00 ));
33220 ///////////////////////////////////////////////////////////////////////////////////
33221 assign slavehrdata_out =(doWork & ~writeReg & slavehreadyo_out_r) ?
33222 (readDataMask & currentVal) : {32{1'b0}};
33226 // record writes in memory banks + report on screen
33227 ///////////////////////////////////////////////////////////////////////////////////
33228 reg [31:0] memWord; // the word to be updated / read
33229 always @ (posedge slavehclk_in)
33231 if (doWork & slavehreadyo_out_r)
33233 memWord = currentVal;
33236 if (be0) memWord[7:0] =slavehwdata_in[7:0] ;
33237 if (be1) memWord[15:8] =slavehwdata_in[15:8] ;
33238 if (be2) memWord[23:16] =slavehwdata_in[23:16];
33239 if (be3) memWord[31:24] =slavehwdata_in[31:24];
33241 if (bankA) memMapA[wordA] = memWord;
33242 if (bankB) memMapB[wordB] = memWord;
33243 if (bankC) memMapC[wordC] = memWord;
33244 if (bankD) memMapD[wordD] = memWord;
33245 if (bankE) memMapE[wordE] = memWord;
33246 if (bankF) memMapF[wordF] = memWord;
33249 $fdisplay(output_file,
33250 "SLAVE: addr=[%h] %s data=[%h] %s",
33252 writeReg ? "WRITE" : "READ",
33253 writeReg ? slavehwdata_in : slavehrdata_out ,
33254 sizeReg==`H_BYTE ? "BYTE" :
33255 ( sizeReg==`H_HWORD ? "HALF WORD" : "WORD" ) );
33258 "SLAVE: addr=[%h] %s data=[%h] %s",
33260 writeReg ? "WRITE" : "READ",
33261 writeReg ? slavehwdata_in : slavehrdata_out ,
33262 sizeReg==`H_BYTE ? "BYTE" :
33263 ( sizeReg==`H_HWORD ? "HALF WORD" : "WORD" ) );
33268 /////////////////////////////////////////////////////////////////////////////////////////////////
33269 // Master Port transactor
33270 /////////////////////////////////////////////////////////////////////////////////////////////////
33272 // timing data - setup and holds
33273 ////////////////////////////////
33274 wire masterhclk_in;
33275 wire masterhready_in, masterhgrant_in;
33276 wire [31:0] masterhrdata_in;
33277 wire [1:0] masterhresp_in;
33278 wire masterhwrite_out, masterhlock_out, masterhbusreq_out;
33279 wire [31:0] masterhaddr_out, masterhwdata_out;
33280 wire [1:0] masterhtrans_out, masterhsize_out;
33281 wire [2:0] masterhburst_out;
33284 assign masterhclk_in = masterhclk;
33285 assign masterhready_in = masterhready;
33286 assign masterhgrant_in = masterhgrant;
33288 assign masterhrdata_in = masterhrdata;
33289 assign masterhresp_in = masterhresp;
33292 assign masterhwrite = masterhwrite_out;
33293 assign masterhlock = masterhlock_out;
33294 assign masterhbusreq = masterhbusreq_out;
33296 assign masterhtrans = masterhtrans_out;
33297 assign masterhsize = masterhsize_out;
33298 assign masterhburst = masterhburst_out;
33300 assign masterhaddr = masterhaddr_out;
33301 assign masterhwdata = masterhwdata_out;
33304 /////////////////////////////////////////////////////////////////////////////////////////////////
33305 /////////////////////////////////////////////////////////////////////////////////////////////////
33307 // Transaction Record Format
33309 // 253..252 response
33310 // 251..220 read data
33313 // 216..208 number of beats in sequential transaction
33314 // 207..176 start address of transaction
33315 // 175..144 expected data
33316 // 143..128 transaction number
33317 // ------------------------------------- following field read from command file
33320 // 108 bus command (0 => inactive)
33321 // 107.. 76 address
33324 // 71.. 40 write data / expected read data
33326 // 36 lock (not implemented)
33328 // 32 check expected data (not implemented)
33330 // 29.. 28 transaction type
33332 // 21.. 20 burst type
33335 // 15.. 00 repeat count
33337 // register outputs
33338 reg [31:0] masterhaddr_out_r;
33339 reg [31:0] masterhwdata_out_r;
33340 reg [2:0] masterhburst_out_r;
33341 reg [1:0] masterhtrans_out_r;
33342 reg masterhwrite_out_r;
33344 assign masterhaddr_out = masterhaddr_out_r;
33345 assign masterhwdata_out = masterhwdata_out_r;
33346 assign masterhburst_out = masterhburst_out_r;
33347 assign masterhtrans_out = masterhtrans_out_r;
33348 assign masterhwrite_out = masterhwrite_out_r;
33350 reg [2:0] masterhsize_outl; // the transactor implements the full 3 bit size
33351 assign masterhsize_out=masterhsize_outl[1:0]; // field but upCore only uses 2
33354 // ////////////////////////////////////////////////////////////////////////////////////////////
33356 reg [128:0] transactions[1:65535]; // space for NUMTRANS transactions
33357 reg [128:0] tmp_transaction;
33358 reg [8:0] tmp_beats, tmp_num;
33360 // Transaction records
33361 reg [255:0] n_trans; // next
33362 reg [255:0] c_trans; // control / address phase
33363 reg [255:0] d_trans; // data phase
33364 reg [255:0] retry_trans; // retrying
33365 reg [255:0] r_trans; // reporting
33367 reg [255:0] i_trans; // IDLE Transaction
33369 reg [15:0] trans_num; // the current control phase transaction
33370 reg [31:0] resp_data;
33372 /*----------------------------------------------------------------------------
33373 Control signals for master transactor
33374 ----------------------------------------------------------------------------*/
33376 wire start = n_trans[108];
33378 wire continue_after_error = 1'b1;
33379 wire generate_data = 1'b0;
33380 wire [1:0] insert_busy = 2'b00;
33381 wire go_busy = n_trans[219];
33382 wire [8:0] beats = n_trans[216:208]; // 511 beats max
33383 wire [2:0] burst = n_trans[23:20];
33384 wire [2:0] size = n_trans[18:16];
33385 wire write = n_trans[72];
33386 wire [31:0] start_address = n_trans[207:176];
33387 wire [31:0] data = n_trans[71:40];
33390 /*----------------------------------------------------------------------------
33391 Transactor state and responses
33392 ----------------------------------------------------------------------------*/
33393 reg [2:0] original_burst;
33394 reg masterhgrant_in_r;
33395 reg [1:0] busy_states;
33396 reg [1:0] busy_counter;
33397 reg [9:0] init_wrap_mask, wrap_mask;
33398 reg [7:0] masterhaddr_out_r_inc, init_wrap_boundary_bit;
33399 reg [10:0] init_next_masterhaddr_out_r, wrap_boundary_bit;
33400 reg [9:0] next_masterhaddr_out_r;
33403 reg address_bus_owned, data_bus_owned;
33404 reg add_go, data_go;
33405 reg reading, writing;
33406 reg first_beat, need_retry, wrap, replay_wrap;
33408 wire first_masterhtrans_out_r;
33412 /*----------------------------------------------------------------------------
33414 ----------------------------------------------------------------------------*/
33417 i_trans ={256{1'b0}}; // set up a null transaction record
33418 i_trans[143:128]=16'hFFFF;
33419 i_trans[29:28] =`H_IDLE;
33421 d_trans=i_trans; // fill pipe with null's
33424 // initialise the transactions database
33425 tmp_transaction={128{1'b0}};
33427 // we're using the bus functional language so load the commands
33429 for (trans_num=1;trans_num<65535;trans_num=trans_num+1)
33431 transactions[trans_num]=tmp_transaction;
33433 $readmemh("mastercommands.dat", transactions);
33435 tmp_num = 9'b000000000;
33436 tmp_beats = 9'b000000000;
33437 trans_num=16'h0000;
33440 n_trans[2]=1'b1; // repeat 4
33442 reset=0; // reset the transactor on start
33450 /*----------------------------------------------------------------------------
33451 Report completed transactions
33453 We could mask and shift the received data for HALFWORD and BYTE
33454 transactions but we won't.
33455 ----------------------------------------------------------------------------*/
33458 wire [31:0] r_r_data = r_trans[72]==1'b1 ? r_trans[71:40] : r_trans[251:220];
33459 wire [31:0] e_r_data = r_trans[175:144];
33460 wire [31:0] mr_r_data, me_r_data; // byte lane masked recovered and expected
33462 mr_r_data = r_trans[17:16] == `H_WORD ? r_r_data :
33463 (r_trans[17:16] == `H_HWORD ?
33464 { 16'h0000, (r_trans[77]==1'b1 ? r_r_data[31:16] : r_r_data[15:0]) } :
33466 { 24'h000000, ( r_trans[77:76]==2'b00 ? r_r_data[7:0] :
33467 r_trans[77:76]==2'b01 ? r_r_data[15:8] :
33468 r_trans[77:76]==2'b10 ? r_r_data[23:16] :
33469 r_r_data[31:24]) } );
33471 r_rdata = r_trans[17:16] == `H_WORD ? r_e_data :
33472 (r_trans[17:16] == `H_HWORD ?
33473 { 16'h0000, (r_trans[77]==1'b1 ? r_e_data[31:16] : r_e_data[15:0]) } :
33475 { 24'h000000, ( r_trans[77:76]==2'b00 ? r_e_data[7:0] :
33476 r_trans[77:76]==2'b01 ? r_e_data[15:8] :
33477 r_trans[77:76]==2'b10 ? r_e_data[23:16] :
33478 r_e_data[31:24]) } );
33480 always @(posedge masterhclk_in)
33482 if (r_trans[108]==1'b1) // r_trans contains a valid transaction
33486 $fdisplay(output_file,
33487 "MASTER: trans=[%d] addr=[%h] %s data=[%h] expected=[%h] %s %s",
33490 r_trans[72]==1'b1 ? "WRITE" : "READ",
33491 r_trans[72]==1'b1 ? r_trans[71:40] : r_trans[251:220],
33493 r_trans[17:16]==`H_BYTE ? "BYTE" :
33494 ( r_trans[17:16]==`H_HWORD ? "HALF WORD" : "WORD" ),
33495 r_trans[253:252]==`H_OKAY ? "OKAY" : "ERROR" );
33498 "MASTER: trans=[%d] addr=[%h] %s data=[%h] expected=[%h] %s %s",
33501 r_trans[72]==1'b1 ? "WRITE" : "READ",
33502 r_trans[72]==1'b1 ? r_trans[71:40] : r_trans[251:220],
33504 r_trans[17:16]==`H_BYTE ? "BYTE" :
33505 ( r_trans[17:16]==`H_HWORD ? "HALF WORD" : "WORD" ),
33506 r_trans[253:252]==`H_OKAY ? "OKAY" : "ERROR" );
33515 /*----------------------------------------------------------------------------
33516 Get Next Transaction
33517 ----------------------------------------------------------------------------*/
33518 reg [216:208] tmp_repeats;
33522 while ( trans_num<16'hFFFF)
33525 if (n_trans[15:0]==16'h0000)
33527 // get the next record
33528 trans_num = trans_num+1;
33530 tmp_transaction = transactions[trans_num];
33532 n_trans[175:144]<= tmp_transaction[71:40]; // expected data
33533 n_trans[143:128]<= trans_num;
33534 n_trans[127:0] <= tmp_transaction;
33537 // check for a BUSY
33538 n_trans[219] <= tmp_transaction[29:28]==`H_BUSY ? 1'b1 : 1'b0;
33540 // update the start address
33541 if (tmp_transaction[29:28]!=`H_SEQ&&tmp_transaction[29:28]!=`H_BUSY)
33543 n_trans[207:176] <= tmp_transaction[107:76]; // start address
33547 // compute the number of beats in burst
33548 if (tmp_transaction[23:20]!=`H_SINGLE && tmp_transaction[29:28]==`H_NONSEQ)
33550 tmp_beats=9'b0_0000_0001;
33551 tmp_repeats[216:208]=9'b0_0000_0001;
33553 // get the transaction from the database
33554 tmp_transaction=transactions[trans_num+tmp_beats];
33556 while (tmp_transaction[29:28]==`H_SEQ||tmp_transaction[29:28]==`H_BUSY)
33558 tmp_repeats[216:208]=tmp_repeats[216:208]+tmp_transaction[15:0]+1;
33559 tmp_beats=tmp_beats+1;
33561 // get the transaction from the database
33562 tmp_transaction = transactions[trans_num+tmp_beats];
33565 n_trans[216:208]<=tmp_repeats[216:208];
33572 n_trans[15:0]<=n_trans[15:0]-1;
33575 // wait for the current transaction to be accepted
33576 @(posedge masterhclk_in);
33577 while (~(addr_ack|data_ack) && n_trans[108])
33578 @(posedge masterhclk_in);
33580 end // while transactions in buffer
33581 if (output_file) $fclose(output_file) ;
33589 /*----------------------------------------------------------------------------
33590 Compute burst length
33592 add_go_r prevents a newly loaded length being decremented by the last data
33593 beat of the previous transaction.
33594 ----------------------------------------------------------------------------*/
33597 always @(posedge masterhclk_in)
33598 if (masterhready_in)
33599 add_go_r <= add_go;
33601 always @(posedge masterhclk_in or posedge reset)
33606 `H_SINGLE: length <= 9'h1;
33607 `H_INCR: length <= beats;
33609 `H_INCR4: length <= 9'h4;
33611 `H_INCR8: length <= 9'h8;
33613 `H_INCR16: length <= 9'h10;
33615 else if ((reading | writing) & masterhready_in & ~add_go_r & ((masterhresp_in == `H_OKAY) | (masterhresp_in == `H_ERROR)))
33616 length <= length - (|length);
33618 reg [8:0] address_length;
33619 always @(posedge masterhclk_in or posedge reset)
33621 address_length <= 5'h0;
33624 `H_SINGLE: address_length <= 9'h1;
33625 `H_INCR: address_length <= beats;
33627 `H_INCR4: address_length <= 9'h4;
33629 `H_INCR8: address_length <= 9'h8;
33631 `H_INCR16: address_length <= 9'h10;
33633 else if (data_bus_owned & ~masterhready_in & ((masterhresp_in == `H_RETRY) | (masterhresp_in == `H_SPLIT)))
33634 address_length <= address_length + 9'h1;
33635 else if (address_bus_owned & masterhready_in & ~(|busy_states) & (masterhtrans_out_r != `H_IDLE))
33636 address_length <= address_length - (|address_length);
33637 else if (address_bus_owned & masterhready_in & (|busy_states) & (masterhtrans_out_r == `H_BUSY) & ~(|busy_counter))
33638 address_length <= address_length - (|address_length);
33640 /*----------------------------------------------------------------------------
33641 Bus request state machine
33643 Bus request machine follows the principle that the arbiter will generally
33644 only re-assign bus grants at the end of a burst transaction. For defined
33645 bursts masterhbusreq_out is removed as soon as we masterhave started the transaction.
33646 Undefined (INCR) bursts will masterhold masterhbusreq_out asserted until the last beat of the
33649 Locked transactions must always assert masterhlock_out for at least one cycle before
33650 the address to be locked to allow the arbiter to see the lock. In practice,
33651 this means inserting an idle cycle.
33653 Have to be careful using burst and beats from the control word. As soon as
33654 the master address phase masterhas finished and the addr_ack is asserted the
33655 testbench can change the control word. So don't use them after the initial
33656 request. Use the ahb outputs instead which will tell us what sort of
33657 transaction we're doing.
33658 ----------------------------------------------------------------------------*/
33659 reg [2:0] req_state;
33660 parameter req_idle = 3'b000,
33661 req_first = 3'b001,
33663 req_masterhold = 3'b011,
33664 req_using = 3'b010,
33665 req_again = 3'b111;
33666 assign masterhbusreq_out = start
33667 | (req_state == req_first)
33668 | (req_state == req_wait)
33669 | (req_state == req_masterhold)
33670 | (req_state == req_again);
33672 wire single_beat = (burst == `H_SINGLE)
33673 | (burst == `H_INCR) & (beats == 9'b1);
33676 always @(posedge masterhclk_in)
33678 // save single_beat for use after it may masterhave changed
33679 single_beat_r = single_beat;
33681 wire last_beat = address_bus_owned & masterhready_in & (address_length <= 9'b1);
33682 wire retry = data_bus_owned & ((masterhresp_in == `H_RETRY) | (masterhresp_in == `H_SPLIT));
33683 wire error = data_bus_owned & masterhready_in & (masterhresp_in == `H_ERROR);
33685 /*----------------------------------------------------------------------------
33686 Bus request machine masterhas five states:
33687 req_idle: masterhbusreq_out negated. Wmasterhen we want to do something we jump to req_first.
33688 The last beat may get a retry response in which case we jump to
33690 req_first: masterhbusreq_out asserted. Wait masterhere for masterhgrant_in and until the transaction
33691 starts. If granted and it's an undefined and not a single beat then
33692 jump to req_masterhold. Else if it's a single beat jump to req_idle.
33693 Otherwise jump to req_using.
33694 req_masterhold: masterhbusreq_out asserted. Hold masterhbusreq_out asserted until last beat of an
33695 undefined. If there's a new request then we jump to req_first,
33696 otherwise back to req_idle. If we lose masterhgrant_in in this state then we
33697 just stay masterhere with masterhbusreq_out asserted until the transaction can be
33698 finished. Also masterhold in this state if retry is asserted to reduce the
33699 chance of releaseing the bus and masterhaving to re-request it to complete
33701 req_using: masterhbusreq_out negated. Wait masterhere for last beat of defined length
33702 transaction. If there's a new request then we jump to req_first,
33703 otherwise back to req_idle. If a posted write is errored before the
33704 last beat or a transaction is retried or we lose masterhgrant_in then we jump
33706 req_again: masterhbusreq_out asserted for completion of transaction interrupted by loss
33707 of masterhgrant_in. Wait masterhere for masterhgrant_in and until the transaction starts then
33708 jump to req_using if first_beat is asserted or req_masterhold if not.
33709 *** We may see a new address toggle whilst in this state.
33710 ----------------------------------------------------------------------------*/
33711 always @(posedge masterhclk_in or posedge reset)
33713 req_state <= req_idle;
33719 req_state <= req_again;
33721 req_state <= req_first;
33724 req_state <= req_idle;
33728 req_state <= req_again;
33729 else if (~masterhgrant_in & ~((masterhtrans_out_r == `H_NONSEQ) & masterhready_in))
33730 req_state <= req_first;
33731 else if ((masterhtrans_out_r == `H_NONSEQ) & masterhready_in)
33734 req_state <= req_first;
33735 else if ((burst == `H_INCR) & ~single_beat)
33736 req_state <= req_masterhold;
33737 else if (single_beat)
33738 req_state <= req_idle;
33740 req_state <= req_using;
33743 req_state <= req_wait;
33747 req_state <= req_again;
33748 else if (~masterhgrant_in & ~((masterhtrans_out_r == `H_NONSEQ) & masterhready_in))
33749 req_state <= req_first;
33750 else if (masterhgrant_in & ~((masterhtrans_out_r == `H_NONSEQ) & masterhready_in))
33751 req_state <= req_wait;
33753 req_state <= req_first;
33754 else if ((burst == `H_INCR) & ~single_beat)
33755 req_state <= req_masterhold;
33756 else if (single_beat_r)
33757 req_state <= req_idle;
33759 req_state <= req_using;
33762 if (error & ~continue_after_error)
33763 req_state <= req_idle;
33764 else if (~masterhgrant_in & (address_length > 9'b1)
33766 req_state <= req_again;
33767 else if (last_beat)
33770 req_state <= req_first;
33772 req_state <= req_idle;
33775 req_state <= req_first;
33777 req_state <= req_masterhold;
33780 if (error & ~continue_after_error)
33781 req_state <= req_idle;
33782 else if (last_beat)
33785 req_state <= req_first;
33787 req_state <= req_idle;
33789 else if (~masterhgrant_in & (address_length > 9'b1)
33791 req_state <= req_again;
33793 req_state <= req_using;
33796 if (error & ~continue_after_error)
33797 req_state <= req_idle;
33798 else if ((~data_bus_owned
33799 | data_bus_owned & (masterhresp_in == `H_OKAY))
33800 & address_bus_owned & (masterhtrans_out_r == `H_IDLE) & masterhready_in & ~masterhlock_out)
33801 req_state <= req_idle;
33802 else if (~masterhgrant_in & (address_length > 9'b1)
33803 | ~((masterhtrans_out_r == `H_NONSEQ) & masterhready_in))
33804 req_state <= req_again;
33805 else if (last_beat | (masterhburst_out_r == `H_SINGLE)
33806 | (masterhburst_out_r == `H_INCR) & single_beat_r)
33807 req_state <= req_idle;
33808 else if (first_beat)
33809 req_state <= req_using;
33811 req_state <= req_masterhold;
33813 default: req_state <= req_idle;
33816 /*----------------------------------------------------------------------------
33817 Address acknowledge
33819 Signals when an address masterhas been transferred and a new one may be presented
33820 for the next transaction.
33821 ----------------------------------------------------------------------------*/
33822 assign addr_ack = add_go;
33824 /*----------------------------------------------------------------------------
33827 Signals when an address masterhas been transferred and a new one may be presented
33828 for the next transaction.
33829 ----------------------------------------------------------------------------*/
33830 assign data_ack = data_go;
33832 /*----------------------------------------------------------------------------
33835 Data bus ownership follows address by one cycle
33836 ----------------------------------------------------------------------------*/
33837 always @(posedge masterhclk_in or posedge reset)
33840 address_bus_owned <= 1'b0;
33841 data_bus_owned <= 1'b0;
33843 else if (masterhready_in)
33845 address_bus_owned <= masterhgrant_in;
33846 data_bus_owned <= address_bus_owned;
33849 /*----------------------------------------------------------------------------
33850 add_go enables the address phase for a new transaction (not the continuation
33851 of a retried transaction or a transaction during which we lose the bus).
33853 It asserts immediately on address request if we're not actively using the bus
33854 and not waiting for it to be re-granted to complete a previous transaction,
33855 the (masterhtrans_out_r == `IDLE) term ensuring it only asserts for one clock.
33856 ----------------------------------------------------------------------------*/
33857 always @(start or masterhbusreq_out or masterhgrant_in or masterhready_in or reading
33858 or writing or masterhtrans_out_r or req_state or length or reset)
33859 if (start & masterhbusreq_out & masterhgrant_in & masterhready_in & ~reading & ~writing
33860 & (masterhtrans_out_r == `H_IDLE) & (req_state != req_again) & ~reset)
33862 else if (start & masterhbusreq_out & masterhgrant_in & masterhready_in & (length < 9'h2) & ~retry
33863 & (masterhtrans_out_r != `H_BUSY) & (masterhtrans_out_r != `H_NONSEQ) & ~reset)
33869 /*----------------------------------------------------------------------------
33870 data_go indicates the completion of the data phase for a transaction
33872 Like add_go it asserts when the master takes control of the address lines to
33873 start a transaction.
33874 It also asserts on all the accepted data beats of a burst except the last.
33875 ----------------------------------------------------------------------------*/
33876 wire trans_end = data_bus_owned & (reading | writing) &
33877 masterhready_in & (masterhresp_in == `H_OKAY || masterhresp_in == `H_ERROR);
33879 always @(start or masterhbusreq_out or masterhgrant_in or masterhready_in or reading
33880 or writing or masterhtrans_out_r or req_state or length or reset
33881 or need_retry or trans_end )
33882 if (start & masterhbusreq_out & masterhgrant_in & masterhready_in & ~reading & ~writing
33883 & (masterhtrans_out_r == `H_IDLE) & (req_state != req_again) & ~reset & ~need_retry)
33885 else if (start & masterhbusreq_out & masterhgrant_in & masterhready_in & (address_length > 9'h1) & ~retry
33886 & ~reset & (~need_retry|trans_end))
33892 /*----------------------------------------------------------------------------
33895 Updated on any clock that starts a new transaction
33896 ----------------------------------------------------------------------------*/
33897 always @(posedge masterhclk_in or posedge reset)
33899 masterhwrite_out_r <= 1'b0;
33901 masterhwrite_out_r <= write;
33903 /*----------------------------------------------------------------------------
33906 Updated on any clock that starts a new transaction
33907 ----------------------------------------------------------------------------*/
33908 always @(posedge masterhclk_in or posedge reset)
33910 masterhsize_outl <= 3'b0;
33912 masterhsize_outl <= size;
33914 /*----------------------------------------------------------------------------
33917 Insert BUSY states into burst transactions.
33919 Capture control word. Load counter on every active phase and decrement to
33921 ----------------------------------------------------------------------------*/
33922 always @(posedge masterhclk_in or posedge reset)
33924 busy_states <= 1'b0;
33926 busy_states <= insert_busy;
33928 always @(posedge masterhclk_in or posedge reset)
33930 busy_counter <= 1'b0;
33931 else if ((masterhtrans_out_r == `H_NONSEQ) | (masterhtrans_out_r == `H_SEQ))
33932 busy_counter <= busy_states - 1;
33934 busy_counter <= busy_counter - (|busy_counter);
33936 /*----------------------------------------------------------------------------
33937 first_masterhtrans_out_r is asserted to enable the first beat of a transaction, which is
33939 - The first beat of a new transaction (addr_ack).
33940 - To restart a transaction that was interrupted by loss of masterhgrant_in if we
33941 receive a new masterhgrant_in whilst in req_again or req_masterhold states.
33942 - To restart a transaction after a RETRY response.
33943 - To restart a transaction after a SPLIT response.
33945 - Break an undefined `INCR replay of a retried or split wrapping burst at
33946 the wrap address boundary.
33947 ----------------------------------------------------------------------------*/
33948 always @(posedge masterhclk_in)
33949 masterhgrant_in_r <= masterhgrant_in;
33951 wire masterhgrant_in_leading_edge = masterhgrant_in & ~masterhgrant_in_r;
33953 always @(posedge masterhclk_in or posedge reset)
33956 else if (masterhgrant_in_leading_edge & ~first_masterhtrans_out_r)
33958 else if (first_masterhtrans_out_r | ~masterhgrant_in)
33961 assign first_masterhtrans_out_r = addr_ack
33962 | (masterhgrant_in_leading_edge | masterhgrant_in & new_grant) & masterhready_in & ~masterhwrite_out_r
33963 & ((req_state == req_masterhold) | (req_state == req_again))
33964 | (masterhgrant_in_leading_edge | masterhgrant_in & new_grant) & masterhready_in & masterhwrite_out_r
33965 & ((req_state == req_masterhold) | (req_state == req_again))
33966 | data_bus_owned & masterhready_in & (masterhresp_in == `H_RETRY)
33967 | data_bus_owned & masterhready_in & (masterhresp_in == `H_SPLIT)
33968 | address_bus_owned & masterhready_in & ~first_beat
33969 & break_wrap & (length > 9'b1);
33971 /*----------------------------------------------------------------------------
33972 The only time masterhtrans_out_r changes when masterhready_in is negated is during reset or after
33973 the first cycle of a two-cyle error response. Otherwise, masterhtrans_out_r can only
33974 change when masterhgrant_in and masterhready_in are asserted.
33975 ----------------------------------------------------------------------------*/
33976 always @(posedge masterhclk_in or posedge reset)
33978 masterhtrans_out_r <= `H_IDLE;
33979 else if (data_bus_owned & ~masterhready_in & (masterhresp_in != `H_OKAY)
33980 & ~continue_after_error) // ERROR'ed transactions cancelled
33981 masterhtrans_out_r <= `H_IDLE;
33982 else if (data_bus_owned & ~masterhready_in & (masterhresp_in != `H_OKAY) & (masterhresp_in != `H_ERROR)
33983 & continue_after_error) // ERROR'ed transactions not cancelled
33984 masterhtrans_out_r <= `H_IDLE;
33985 else if (masterhgrant_in & masterhready_in)
33986 case (masterhtrans_out_r)
33988 if (first_masterhtrans_out_r)
33989 masterhtrans_out_r <= `H_NONSEQ;
33991 masterhtrans_out_r <= `H_IDLE;
33993 if (first_masterhtrans_out_r)
33994 masterhtrans_out_r <= `H_NONSEQ;
33995 else if ((masterhburst_out_r == `H_SINGLE) | (address_length <= 9'h1))
33997 masterhtrans_out_r <= `H_IDLE;
33998 else if (go_busy) // (|busy_states)
33999 masterhtrans_out_r <= `H_BUSY;
34001 masterhtrans_out_r <= `H_SEQ;
34004 if (first_masterhtrans_out_r)
34005 masterhtrans_out_r <= `H_NONSEQ;
34006 else if (go_busy) //(|busy_counter)
34007 masterhtrans_out_r <= `H_BUSY;
34009 masterhtrans_out_r <= `H_SEQ;
34011 else if (masterhready_in & ~masterhgrant_in)
34012 masterhtrans_out_r <= `H_IDLE;
34014 /*----------------------------------------------------------------------------
34015 One of reading or writing is asserted during any data beat for which we are
34016 actively using the bus.
34017 ----------------------------------------------------------------------------*/
34018 always @(posedge masterhclk_in or posedge reset)
34024 else if (masterhready_in)
34026 reading <= ~masterhwrite_out_r & address_bus_owned
34027 & (masterhtrans_out_r != `H_IDLE) & (masterhtrans_out_r != `H_BUSY);
34028 writing <= masterhwrite_out_r & address_bus_owned
34029 & (masterhtrans_out_r != `H_IDLE) & (masterhtrans_out_r != `H_BUSY);
34032 /*----------------------------------------------------------------------------
34035 first_beat is used to keep masterhburst_out_r unchanged when the first beat is to be
34036 replayed. It alse controls the bus request. A transaction that is split or
34037 retried on any other beat will be replayed as INCR and masterhbusreq_out must be masterheld
34040 Tmasterhis means that a defined length read that us interrupted mid-burst will
34041 complete as an undefined INCR and may pre-fetch past the end of the defined
34042 length (unless, of course, no_prefetch is asserted).
34043 ----------------------------------------------------------------------------*/
34044 always @(posedge masterhclk_in or posedge reset)
34046 first_beat <= 1'b0;
34048 first_beat <= 1'b1;
34049 else if (data_bus_owned & (reading | writing) & masterhready_in & (masterhresp_in == `H_OKAY))
34050 first_beat <= 1'b0;
34052 always @(posedge masterhclk_in or posedge reset)
34054 masterhburst_out_r <= 3'b0;
34056 masterhburst_out_r <= burst;
34057 else if (first_masterhtrans_out_r & ~first_beat)
34058 masterhburst_out_r <= `H_INCR;
34060 /*----------------------------------------------------------------------------
34062 ----------------------------------------------------------------------------*/
34063 always @(posedge masterhclk_in or posedge reset)
34065 need_retry <= 1'b0;
34066 else if (data_bus_owned & ~masterhready_in & ((masterhresp_in == `H_RETRY) | (masterhresp_in == `H_SPLIT)))
34067 need_retry <= 1'b1;
34068 else if (data_bus_owned & masterhready_in & (reading | writing)
34069 & ((masterhresp_in == `H_OKAY) | (masterhresp_in == `H_ERROR)))
34070 need_retry <= 1'b0;
34072 always @(posedge masterhclk_in or posedge reset)
34076 wrap <= (burst == `H_WRAP4) | (burst == `H_WRAP8)
34077 | (burst == `H_WRAP16);
34079 always @(posedge masterhclk_in or posedge reset)
34081 original_burst <= 3'b0;
34083 original_burst <= burst;
34085 always @(posedge masterhclk_in or posedge reset)
34087 replay_wrap <= 3'b0;
34089 replay_wrap <= 3'b0;
34090 else if (data_bus_owned & ~masterhready_in & wrap & ((masterhresp_in == `H_RETRY) | (masterhresp_in == `H_SPLIT)))
34091 replay_wrap <= 3'b1;
34093 /*----------------------------------------------------------------------------
34096 Used to modify next_masterhaddr_out_r during wrapping bursts. First case statement forms
34097 a mask based on the transfer size. Tmasterhis is then shifted left with '1's
34098 inserted to form the final mask. E.g. masterhsize_outl == word (3'b010) wrapped at a
34099 four beat boundary results in wrap_mask set to 10'b0000001111 allowing the
34100 four lsbs of the address to increment and wrap addressing sixteen bytes in
34102 ----------------------------------------------------------------------------*/
34103 always @(masterhsize_outl)
34104 case (masterhsize_outl)
34105 3'b000: init_wrap_mask <= 10'b0;
34106 3'b001: init_wrap_mask <= 10'b1;
34107 3'b010: init_wrap_mask <= 10'b11;
34108 3'b011: init_wrap_mask <= 10'b111;
34109 3'b100: init_wrap_mask <= 10'b1111;
34110 3'b101: init_wrap_mask <= 10'b11111;
34111 3'b110: init_wrap_mask <= 10'b111111;
34112 3'b111: init_wrap_mask <= 10'b1111111;
34115 always @(original_burst or init_wrap_mask)
34116 case (original_burst)
34117 `H_WRAP4: wrap_mask <= {init_wrap_mask[7:0], 2'b11};
34118 `H_WRAP8: wrap_mask <= {init_wrap_mask[6:0], 3'b111};
34119 `H_WRAP16: wrap_mask <= {init_wrap_mask[5:0], 4'b1111};
34120 default: wrap_mask <= 10'b0;
34123 always @(masterhsize_outl)
34124 case (masterhsize_outl)
34125 3'b000: init_wrap_boundary_bit <= 8'b1;
34126 3'b001: init_wrap_boundary_bit <= 8'b10;
34127 3'b010: init_wrap_boundary_bit <= 8'b100;
34128 3'b011: init_wrap_boundary_bit <= 8'b1000;
34129 3'b100: init_wrap_boundary_bit <= 8'b10000;
34130 3'b101: init_wrap_boundary_bit <= 8'b100000;
34131 3'b110: init_wrap_boundary_bit <= 8'b1000000;
34132 3'b111: init_wrap_boundary_bit <= 8'b10000000;
34135 always @(original_burst or init_wrap_boundary_bit)
34136 case (original_burst)
34137 `H_WRAP4: wrap_boundary_bit <= {init_wrap_boundary_bit, 2'b0};
34138 `H_WRAP8: wrap_boundary_bit <= {init_wrap_boundary_bit, 3'b0};
34139 `H_WRAP16:wrap_boundary_bit <= {init_wrap_boundary_bit[6:0], 4'b0};
34140 default: wrap_boundary_bit <= 11'b0;
34143 /*----------------------------------------------------------------------------
34144 Compute address increment
34146 Tmasterhis code allows for all possibilities by inferring a 3-to-8 decoder on the
34147 transfer size. AHB spec is unclear masterhow a burst with a transfer size greater
34148 than the bus width should be masterhandled.
34149 ----------------------------------------------------------------------------*/
34150 always @(masterhsize_outl)
34152 masterhaddr_out_r_inc <= 10'b0;
34153 masterhaddr_out_r_inc[masterhsize_outl] <= 1'b1;
34156 /*----------------------------------------------------------------------------
34157 Compute next address
34159 Next address is based on the increment computed from the transfer size, and
34160 the burst type, which may tell us to wrap. Wrapping is achieved by preserving
34161 some of the upper bits through use of wrap_mask.
34163 If beat n is retried, we're already putting out the address for beat n+1 so
34164 we need to decrement.
34165 ----------------------------------------------------------------------------*/
34166 always @(data_bus_owned or masterhresp_in or masterhready_in or masterhaddr_out_r or masterhaddr_out_r_inc)
34167 if (data_bus_owned & ((masterhresp_in == `H_RETRY) | (masterhresp_in == `H_SPLIT)))
34168 init_next_masterhaddr_out_r <= {1'b0, masterhaddr_out_r[9:0]} - masterhaddr_out_r_inc;
34170 init_next_masterhaddr_out_r <= {1'b0, masterhaddr_out_r[9:0]} + masterhaddr_out_r_inc;
34172 always @(original_burst or wrap_mask or init_next_masterhaddr_out_r or masterhaddr_out_r)
34173 if ((original_burst == `H_WRAP4) | (original_burst == `H_WRAP8)
34174 | (original_burst == `H_WRAP16))
34175 next_masterhaddr_out_r <= wrap_mask & init_next_masterhaddr_out_r | ~wrap_mask & masterhaddr_out_r;
34177 next_masterhaddr_out_r <= init_next_masterhaddr_out_r;
34179 assign break_wrap = replay_wrap & ((|(init_next_masterhaddr_out_r & wrap_boundary_bit))
34180 ^ (|(masterhaddr_out_r[10:0] & wrap_boundary_bit)));
34182 /*----------------------------------------------------------------------------
34185 AHB address has to track the changing address during bursts. next_masterhaddr_out_r
34186 computes the next address.
34188 NOTE: It is incumbent upon the command file not to attempt a transaction that
34189 would cross a 1Kbyte address boundary.
34191 Address is normally updated after each address phase. It is also updated
34192 during the second cycle of a two cycle retry or split response to rewind the
34193 address and allow the transaction to be replayed.
34194 ----------------------------------------------------------------------------*/
34195 always @(posedge masterhclk_in or posedge reset)
34197 masterhaddr_out_r <= 32'b0;
34199 masterhaddr_out_r <= start_address;
34200 else if (data_bus_owned & masterhready_in & ((masterhresp_in == `H_RETRY) | (masterhresp_in == `H_SPLIT)))
34201 masterhaddr_out_r[9:0] <= next_masterhaddr_out_r;
34202 else if (address_bus_owned & masterhready_in
34203 & ((masterhtrans_out_r == `H_NONSEQ) | (masterhtrans_out_r == `H_SEQ)))
34204 masterhaddr_out_r[9:0] <= next_masterhaddr_out_r;
34206 /*----------------------------------------------------------------------------
34209 If generate_data is negated then initial data is taken from data input. If
34210 generate_data is asserted then data is generated from the address offset to
34211 match that expected by the checkers.
34213 The expected data and the transaction number follow the write data.
34215 At the end of a burst data is set to x so we can ensure nothing is relying on
34217 ----------------------------------------------------------------------------*/
34219 reg [31:0] masterhwdata_out_r_pipe;
34220 reg [31:0] masterhwdata_out_r_retry;
34222 always @(posedge masterhclk_in)
34223 if (data_bus_owned & ~masterhready_in & (masterhresp_in==`H_RETRY||masterhresp_in==`H_SPLIT))
34225 masterhwdata_out_r_retry <= masterhwdata_out_r;
34227 else if (addr_ack || data_ack)
34228 masterhwdata_out_r_pipe <= data;
34231 wire [7:0] addr_offset = {masterhaddr_out_r[7:2], 2'b0};
34233 always @(posedge masterhclk_in or posedge reset)
34235 masterhwdata_out_r <= {32{1'b0}};
34236 else if (~address_bus_owned & masterhready_in)
34237 masterhwdata_out_r <= {32{1'b0}};
34238 else if (masterhready_in & ~generate_data)
34240 if (address_bus_owned & masterhwrite_out_r & need_retry & ~trans_end)
34241 masterhwdata_out_r <= masterhwdata_out_r_retry;
34242 else if (address_bus_owned & masterhwrite_out_r & (masterhtrans_out_r == `H_NONSEQ))
34243 masterhwdata_out_r <= masterhwdata_out_r_pipe;
34244 else if ((length == 9'b0))
34245 masterhwdata_out_r <= {32{1'b0}};
34246 else if (address_bus_owned & masterhwrite_out_r & (masterhtrans_out_r == `H_SEQ))
34247 masterhwdata_out_r <= masterhwdata_out_r_pipe;
34249 masterhwdata_out_r <= {32{1'b0}};
34251 else if (masterhready_in & generate_data)
34253 if (address_bus_owned & masterhwrite_out_r & (masterhtrans_out_r == `H_NONSEQ))
34254 masterhwdata_out_r <= {addr_offset, addr_offset, addr_offset, addr_offset};
34255 else if ((length == 9'b0))
34256 masterhwdata_out_r <= {32{1'b0}};
34257 else if (address_bus_owned & masterhwrite_out_r & (masterhtrans_out_r == `H_SEQ))
34258 masterhwdata_out_r <= {addr_offset, addr_offset, addr_offset, addr_offset};
34261 /*----------------------------------------------------------------------------
34262 Transaction Details
34264 The transactor pipeline consists of four stages
34266 n_trans - the next transaction from the store
34267 c_trans - the current control / address stage transaction
34268 d_trans - the data stage transaction
34269 rTrans - the completed stage for reporting
34272 c_trans is updated from n_trans when a new transaction begins or from d_trans in
34273 the case of split/retry
34274 ----------------------------------------------------------------------------*/
34276 always @(posedge masterhclk_in)
34277 if (data_bus_owned & ~masterhready_in & (masterhresp_in==`H_RETRY||masterhresp_in==`H_SPLIT))
34279 // c_trans<=d_trans; // RETRY/SPLIT causes transaction to be replayed
34280 retry_trans<=d_trans;
34282 else if (addr_ack || data_ack)
34287 always @(posedge masterhclk_in or posedge reset)
34288 if (address_bus_owned & masterhready_in & ~reset & (~need_retry|trans_end) )
34290 d_trans <= c_trans;
34291 d_trans[107:76] <= masterhaddr_out_r;
34292 d_trans[72] <= masterhwrite_out_r;
34293 d_trans[36] <= masterhlock_out;
34294 d_trans[29:28] <= masterhtrans_out_r;
34295 d_trans[21:20] <= masterhburst_out_r;
34296 d_trans[18:16] <= masterhsize_out;
34298 else if (address_bus_owned & masterhready_in & ~reset & need_retry )
34300 d_trans <= retry_trans;
34301 d_trans[107:76] <= masterhaddr_out_r;
34302 d_trans[72] <= masterhwrite_out_r;
34303 d_trans[36] <= masterhlock_out;
34304 d_trans[29:28] <= masterhtrans_out_r;
34305 d_trans[21:20] <= masterhburst_out_r;
34306 d_trans[18:16] <= masterhsize_out;
34308 else if ( ( ~address_bus_owned & masterhready_in) | reset)
34312 always @(posedge masterhclk_in)
34313 if (trans_end & ~need_retry)
34315 r_trans[253:252]<=masterhresp_in;
34316 r_trans[251:220]<=masterhrdata_in;
34317 r_trans[219:0] <=d_trans[219:0];
34319 else if (trans_end & need_retry)
34321 r_trans[253:252]<=masterhresp_in;
34322 r_trans[251:220]<=masterhrdata_in;
34323 r_trans[219:0] <=retry_trans[219:0];
34329 /*----------------------------------------------------------------------------
34331 ----------------------------------------------------------------------------*/
34332 assign masterhlock_out = 1'b0;
34333 /*----------------------------------------------------------------------------
34334 ----------------------------------------------------------------------------*/
34335 endmodule // alt_exc_upcore
34337 //START_MODULE_NAME------------------------------------------------------------
34339 // Module Name : altsquare
34341 // Description : Parameterized integer square megafunction.
34342 // The input data can be signed or unsigned, and the output
34343 // can be pipelined.
34345 // Limitations : Minimum data width is 1.
34347 // Results expected: result - The square of input data.
34349 //END_MODULE_NAME--------------------------------------------------------------
34351 `timescale 1 ps / 1 ps
34361 // GLOBAL PARAMETER DECLARATION
34362 parameter data_width = 1;
34363 parameter result_width = 1;
34364 parameter pipeline = 0;
34365 parameter representation = "UNSIGNED";
34366 parameter lpm_hint = "UNUSED";
34367 parameter lpm_type = "altsquare";
34369 // INPUT PORT DECLARATION
34370 input [data_width - 1 : 0] data;
34375 // OUTPUT PORT DECLARATION
34376 output [result_width - 1 : 0] result;
34378 // INTERNAL REGISTER DECLARATION
34379 reg [result_width - 1 : 0]stage_values[pipeline : 0];
34380 reg [data_width - 1 : 0] pos_data_value;
34382 // LOCAL INTEGER DECLARATION
34385 // INTERNAL WIRE DECLARATION
34389 // INTERNAL TRI DECLARATION
34394 buf (i_clock, clock);
34395 buf (i_aclr, aclr);
34396 buf (i_clken, ena);
34399 // INITIAL CONSTRUCT BLOCK
34404 $display("data_width (%d) must be greater than 0.(ERROR)\n", data_width);
34407 if(result_width < 1)
34409 $display("result_width (%d) must be greater than 0.(ERROR)\n", result_width);
34414 // ALWAYS CONSTRUCT BLOCK
34415 always @(data or i_aclr)
34417 if (i_aclr) // clear the pipeline
34418 for (i = 0; i <= pipeline; i = i + 1)
34419 stage_values[i] = 'b0;
34422 if ((representation == "SIGNED") && (data[data_width - 1] == 1))
34423 pos_data_value = (~data) + 1;
34425 pos_data_value = data;
34427 stage_values[pipeline] = pos_data_value * pos_data_value;
34432 always @(posedge i_clock)
34434 if (!i_aclr && i_clken == 1)
34436 for(i = 0; i < pipeline; i = i + 1)
34437 stage_values[i] <= stage_values[i + 1];
34441 // CONTINOUS ASSIGNMENT
34442 assign result = stage_values[0];
34443 endmodule // altsquare
34446 module sld_signaltap (
34469 parameter SLD_NODE_CRC_LOWORD = 50132;
34470 parameter SLD_RAM_BLOCK_TYPE = "AUTO";
34471 parameter SLD_ADVANCED_TRIGGER_ENTITY = "basic";
34472 parameter SLD_ADVANCED_TRIGGER_1 = "NONE";
34473 parameter SLD_MEM_ADDRESS_BITS = 7;
34474 parameter SLD_TRIGGER_BITS = 8;
34475 parameter SLD_ADVANCED_TRIGGER_2 = "NONE";
34476 parameter SLD_TRIGGER_LEVEL = 1;
34477 parameter SLD_ADVANCED_TRIGGER_3 = "NONE";
34478 parameter SLD_ADVANCED_TRIGGER_4 = "NONE";
34479 parameter SLD_ADVANCED_TRIGGER_5 = "NONE";
34480 parameter SLD_ADVANCED_TRIGGER_6 = "NONE";
34481 parameter SLD_ENABLE_ADVANCED_TRIGGER = 0;
34482 parameter SLD_NODE_CRC_HIWORD = 41394;
34483 parameter SLD_ADVANCED_TRIGGER_7 = "NONE";
34484 parameter SLD_TRIGGER_LEVEL_PIPELINE = 1;
34485 parameter SLD_ADVANCED_TRIGGER_8 = "NONE";
34486 parameter SLD_ADVANCED_TRIGGER_9 = "NONE";
34487 parameter SLD_INCREMENTAL_ROUTING = 0;
34488 parameter SLD_ADVANCED_TRIGGER_10 = "NONE";
34489 parameter SLD_TRIGGER_IN_ENABLED = 1;
34490 parameter SLD_NODE_CRC_BITS = 32;
34491 parameter SLD_SAMPLE_DEPTH = 128;
34492 parameter SLD_DATA_BIT_CNTR_BITS = 4;
34493 parameter SLD_DATA_BITS = 8;
34495 parameter ELA_STATUS_BITS = 3;
34496 parameter MAX_NUMBER_OF_BITS_FOR_TRIGGERS = 4;
34497 parameter SLD_IR_BITS = ELA_STATUS_BITS + MAX_NUMBER_OF_BITS_FOR_TRIGGERS;
34499 input [SLD_IR_BITS-1:0] ir_in;
34501 output [SLD_TRIGGER_BITS-1:0] acq_trigger_out;
34502 input [SLD_DATA_BITS-1:0] acq_data_in;
34503 input jtag_state_udr;
34506 output trigger_out;
34507 input jtag_state_cdr;
34508 input [SLD_TRIGGER_BITS-1:0] acq_trigger_in;
34511 input jtag_state_uir;
34513 input jtag_state_e1dr;
34516 input [SLD_NODE_CRC_BITS-1:0] crc;
34519 input jtag_state_sdr;
34521 endmodule //sld_signaltap
34523 module altstratixii_oct (
34529 parameter lpm_type = "altstratixii_oct";
34533 input terminationclock;
34534 input terminationenable;
34537 endmodule //altstratixii_oct