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   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  Phy_sim.v                                                   ////
   4 ////                                                              ////
   5 ////  This file is part of the Ethernet IP core project           ////
   6 ////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Jon Gao (gaojon@yahoo.com)                            ////
  10 ////                                                              ////
  11 ////                                                              ////
  12 //////////////////////////////////////////////////////////////////////
  13 ////                                                              ////
  14 //// Copyright (C) 2001 Authors                                   ////
  15 ////                                                              ////
  16 //// This source file may be used and distributed without         ////
  17 //// restriction provided that this copyright statement is not    ////
  18 //// removed from the file and that any derivative work contains  ////
  19 //// the original copyright notice and the associated disclaimer. ////
  20 ////                                                              ////
  21 //// This source file is free software; you can redistribute it   ////
  22 //// and/or modify it under the terms of the GNU Lesser General   ////
  23 //// Public License as published by the Free Software Foundation; ////
  24 //// either version 2.1 of the License, or (at your option) any   ////
  25 //// later version.                                               ////
  26 ////                                                              ////
  27 //// This source is distributed in the hope that it will be       ////
  28 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  29 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  30 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  31 //// details.                                                     ////
  32 ////                                                              ////
  33 //// You should have received a copy of the GNU Lesser General    ////
  34 //// Public License along with this source; if not, download it   ////
  35 //// from http://www.opencores.org/lgpl.shtml                     ////
  36 ////                                                              ////
  37 //////////////////////////////////////////////////////////////////////
  38 //
  39 // CVS Revision History
  40 //
  41 // $Log: Phy_sim.v,v $
  42 // Revision 1.3  2006/11/17 17:53:07  maverickist
  43 // no message
  44 //
  45 // Revision 1.2  2006/01/19 14:07:50  maverickist
  46 // verification is complete.
  47 //
  48 // Revision 1.1.1.1  2005/12/13 01:51:44  Administrator
  49 // no message
  50 //
  51
  52 `timescale 1ns/100ps
  53
  54 module Phy_sim (input                   Gtx_clk                                 ,//used only in GMII mode
  55                 output                  Rx_clk                                  ,
  56                 output                  Tx_clk                                  ,//used only in MII mode
  57                 input                   Tx_er                                   ,
  58                 input                   Tx_en                                   ,
  59                 input   [7:0]   Txd                                             ,
  60                 output                  Rx_er                                   ,
  61                 output                  Rx_dv                                   ,
  62                 output  [7:0]   Rxd                                             ,
  63                 output                  Crs                                             ,
  64                 output                  Col                                             ,
  65                 input   [2:0]   Speed
  66                 );
  67
  68    // ////////////////////////////////////////////////////////////////////
  69    // this file used to simulate Phy.
  70    // generate clk and loop the Tx data to Rx data
  71    // full duplex mode can be verified on loop mode.
  72    // ////////////////////////////////////////////////////////////////////
  73    // ////////////////////////////////////////////////////////////////////
  74    // internal signals
  75    // ////////////////////////////////////////////////////////////////////
  76    reg                          Clk_25m                 ;//used for 100 Mbps mode
  77    reg                          Clk_2_5m                ;//used for 10 Mbps mode
  78    //wire                       Rx_clk                  ;
  79    //wire                       Tx_clk                  ;//used only in MII mode
  80    // ////////////////////////////////////////////////////////////////////
  81    always
  82      begin
  83         #20             Clk_25m=0;
  84         #20             Clk_25m=1;
  85      end
  86
  87    always
  88      begin
  89         #200    Clk_2_5m=0;
  90         #200    Clk_2_5m=1;
  91      end
  92
  93    assign       Rx_clk=Speed[2]?Gtx_clk:Speed[1]?Clk_25m:Speed[0]?Clk_2_5m:0;
  94    assign       Tx_clk=Speed[2]?Gtx_clk:Speed[1]?Clk_25m:Speed[0]?Clk_2_5m:0;
  95
  96    assign       Rx_dv   =Tx_en  ;
  97    assign       Rxd             =Txd    ;
  98    assign       Rx_er   =0              ;
  99    assign       Crs     =Tx_en  ;
 100    assign       Col             =0              ;
 101
 102 endmodule // Phy_sim