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   1 /* $Id: aeMB_sim.v,v 1.2 2008/06/06 09:36:02 sybreon Exp $
   2 **
   3 ** AEMB EDK 3.2 Compatible Core
   4 ** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
   5 **
   6 ** This file is part of AEMB.
   7 **
   8 ** AEMB is free software: you can redistribute it and/or modify it
   9 ** under the terms of the GNU Lesser General Public License as
  10 ** published by the Free Software Foundation, either version 3 of the
  11 ** License, or (at your option) any later version.
  12 **
  13 ** AEMB is distributed in the hope that it will be useful, but WITHOUT
  14 ** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15 ** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
  16 ** Public License for more details.
  17 **
  18 ** You should have received a copy of the GNU Lesser General Public
  19 ** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
  20 */
  21
  22 module aeMB_sim (/*AUTOARG*/
  23    // Outputs
  24    iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o,
  25    fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o,
  26    // Inputs
  27    sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, fsl_dat_i,
  28    fsl_ack_i, dwb_dat_i, dwb_ack_i
  29    );
  30    // Bus widths
  31    parameter IW = 32; /// Instruction bus address width
  32    parameter DW = 32; /// Data bus address width
  33
  34    // Optional functions
  35    parameter MUL = 1; // Multiplier
  36    parameter BSF = 1; // Barrel Shifter
  37
  38    /*AUTOOUTPUT*/
  39    // Beginning of automatic outputs (from unused autoinst outputs)
  40    output [DW-1:2]      dwb_adr_o;              // From cpu of aeMB_edk32.v
  41    output [31:0]        dwb_dat_o;              // From cpu of aeMB_edk32.v
  42    output [3:0]         dwb_sel_o;              // From cpu of aeMB_edk32.v
  43    output               dwb_stb_o;              // From cpu of aeMB_edk32.v
  44    output               dwb_wre_o;              // From cpu of aeMB_edk32.v
  45    output [6:2]         fsl_adr_o;              // From cpu of aeMB_edk32.v
  46    output [31:0]        fsl_dat_o;              // From cpu of aeMB_edk32.v
  47    output               fsl_stb_o;              // From cpu of aeMB_edk32.v
  48    output [1:0]         fsl_tag_o;              // From cpu of aeMB_edk32.v
  49    output               fsl_wre_o;              // From cpu of aeMB_edk32.v
  50    output [IW-1:2]      iwb_adr_o;              // From cpu of aeMB_edk32.v
  51    output               iwb_stb_o;              // From cpu of aeMB_edk32.v
  52    // End of automatics
  53    /*AUTOINPUT*/
  54    // Beginning of automatic inputs (from unused autoinst inputs)
  55    input                dwb_ack_i;              // To cpu of aeMB_edk32.v
  56    input [31:0]         dwb_dat_i;              // To cpu of aeMB_edk32.v
  57    input                fsl_ack_i;              // To cpu of aeMB_edk32.v
  58    input [31:0]         fsl_dat_i;              // To cpu of aeMB_edk32.v
  59    input                iwb_ack_i;              // To cpu of aeMB_edk32.v
  60    input [31:0]         iwb_dat_i;              // To cpu of aeMB_edk32.v
  61    input                sys_clk_i;              // To cpu of aeMB_edk32.v
  62    input                sys_int_i;              // To cpu of aeMB_edk32.v
  63    input                sys_rst_i;              // To cpu of aeMB_edk32.v
  64    // End of automatics
  65    /*AUTOWIRE*/
  66
  67    aeMB_edk32
  68      #(/*AUTOINSTPARAM*/
  69        // Parameters
  70        .IW                              (IW),
  71        .DW                              (DW),
  72        .MUL                             (MUL),
  73        .BSF                             (BSF))
  74    cpu
  75      (/*AUTOINST*/
  76       // Outputs
  77       .dwb_adr_o                        (dwb_adr_o[DW-1:2]),
  78       .dwb_dat_o                        (dwb_dat_o[31:0]),
  79       .dwb_sel_o                        (dwb_sel_o[3:0]),
  80       .dwb_stb_o                        (dwb_stb_o),
  81       .dwb_wre_o                        (dwb_wre_o),
  82       .fsl_adr_o                        (fsl_adr_o[6:2]),
  83       .fsl_dat_o                        (fsl_dat_o[31:0]),
  84       .fsl_stb_o                        (fsl_stb_o),
  85       .fsl_tag_o                        (fsl_tag_o[1:0]),
  86       .fsl_wre_o                        (fsl_wre_o),
  87       .iwb_adr_o                        (iwb_adr_o[IW-1:2]),
  88       .iwb_stb_o                        (iwb_stb_o),
  89       // Inputs
  90       .dwb_ack_i                        (dwb_ack_i),
  91       .dwb_dat_i                        (dwb_dat_i[31:0]),
  92       .fsl_ack_i                        (fsl_ack_i),
  93       .fsl_dat_i                        (fsl_dat_i[31:0]),
  94       .iwb_ack_i                        (iwb_ack_i),
  95       .iwb_dat_i                        (iwb_dat_i[31:0]),
  96       .sys_int_i                        (sys_int_i),
  97       .sys_clk_i                        (sys_clk_i),
  98       .sys_rst_i                        (sys_rst_i));
  99
 100    // --- SIMULATION KERNEL ----------------------------------
 101    // synopsys translate_off
 102
 103    wire [IW-1:0]        iwb_adr = {iwb_adr_o, 2'd0};
 104    wire [DW-1:0]        dwb_adr = {dwb_adr_o,2'd0};
 105    wire [1:0]           wBRA = {cpu.rBRA, cpu.rDLY};
 106    wire [3:0]           wMSR = {cpu.xecu.rMSR_BIP, cpu.xecu.rMSR_C, cpu.xecu.rMSR_IE, cpu.xecu.rMSR_BE};
 107
 108
 109    `ifdef AEMB_SIM_KERNEL
 110    always @(posedge cpu.gclk) begin
 111       if (cpu.gena) begin
 112
 113          $write ("\n", ($stime/10));
 114          $writeh (" PC=", iwb_adr );
 115          $writeh ("\t");
 116
 117          case (wBRA)
 118            2'b00: $write(" ");
 119            2'b01: $write(".");
 120            2'b10: $write("-");
 121            2'b11: $write("+");
 122          endcase // case (cpu.wBRA)
 123
 124          case (cpu.rOPC)
 125            6'o00: if (cpu.rRD == 0) $write("   "); else $write("ADD");
 126            6'o01: $write("RSUB");
 127            6'o02: $write("ADDC");
 128            6'o03: $write("RSUBC");
 129            6'o04: $write("ADDK");
 130            6'o05: case (cpu.rIMM[1:0])
 131                     2'o0: $write("RSUBK");
 132                     2'o1: $write("CMP");
 133                     2'o3: $write("CMPU");
 134                     default: $write("XXX");
 135                   endcase // case (cpu.rIMM[1:0])
 136            6'o06: $write("ADDKC");
 137            6'o07: $write("RSUBKC");
 138
 139            6'o10: $write("ADDI");
 140            6'o11: $write("RSUBI");
 141            6'o12: $write("ADDIC");
 142            6'o13: $write("RSUBIC");
 143            6'o14: $write("ADDIK");
 144            6'o15: $write("RSUBIK");
 145            6'o16: $write("ADDIKC");
 146            6'o17: $write("RSUBIKC");
 147
 148            6'o20: $write("MUL");
 149            6'o21: case (cpu.rALT[10:9])
 150                     2'o0: $write("BSRL");
 151                     2'o1: $write("BSRA");
 152                     2'o2: $write("BSLL");
 153                     default: $write("XXX");
 154                   endcase // case (cpu.rALT[10:9])
 155            6'o22: $write("IDIV");
 156
 157            6'o30: $write("MULI");
 158            6'o31: case (cpu.rALT[10:9])
 159                     2'o0: $write("BSRLI");
 160                     2'o1: $write("BSRAI");
 161                     2'o2: $write("BSLLI");
 162                     default: $write("XXX");
 163                   endcase // case (cpu.rALT[10:9])
 164            6'o33: case (cpu.rRB[4:2])
 165                     3'o0: $write("GET");
 166                     3'o4: $write("PUT");
 167                     3'o2: $write("NGET");
 168                     3'o6: $write("NPUT");
 169                     3'o1: $write("CGET");
 170                     3'o5: $write("CPUT");
 171                     3'o3: $write("NCGET");
 172                     3'o7: $write("NCPUT");
 173                   endcase // case (cpu.rRB[4:2])
 174
 175            6'o40: $write("OR");
 176            6'o41: $write("AND");
 177            6'o42: if (cpu.rRD == 0) $write("   "); else $write("XOR");
 178            6'o43: $write("ANDN");
 179            6'o44: case (cpu.rIMM[6:5])
 180                     2'o0: $write("SRA");
 181                     2'o1: $write("SRC");
 182                     2'o2: $write("SRL");
 183                     2'o3: if (cpu.rIMM[0]) $write("SEXT16"); else $write("SEXT8");
 184                   endcase // case (cpu.rIMM[6:5])
 185
 186            6'o45: $write("MOV");
 187            6'o46: case (cpu.rRA[3:2])
 188                     3'o0: $write("BR");
 189                     3'o1: $write("BRL");
 190                     3'o2: $write("BRA");
 191                     3'o3: $write("BRAL");
 192                   endcase // case (cpu.rRA[3:2])
 193
 194            6'o47: case (cpu.rRD[2:0])
 195                     3'o0: $write("BEQ");
 196                     3'o1: $write("BNE");
 197                     3'o2: $write("BLT");
 198                     3'o3: $write("BLE");
 199                     3'o4: $write("BGT");
 200                     3'o5: $write("BGE");
 201                     default: $write("XXX");
 202                   endcase // case (cpu.rRD[2:0])
 203
 204            6'o50: $write("ORI");
 205            6'o51: $write("ANDI");
 206            6'o52: $write("XORI");
 207            6'o53: $write("ANDNI");
 208            6'o54: $write("IMMI");
 209            6'o55: case (cpu.rRD[1:0])
 210                     2'o0: $write("RTSD");
 211                     2'o1: $write("RTID");
 212                     2'o2: $write("RTBD");
 213                     default: $write("XXX");
 214                   endcase // case (cpu.rRD[1:0])
 215            6'o56: case (cpu.rRA[3:2])
 216                     3'o0: $write("BRI");
 217                     3'o1: $write("BRLI");
 218                     3'o2: $write("BRAI");
 219                     3'o3: $write("BRALI");
 220                   endcase // case (cpu.rRA[3:2])
 221            6'o57: case (cpu.rRD[2:0])
 222                     3'o0: $write("BEQI");
 223                     3'o1: $write("BNEI");
 224                     3'o2: $write("BLTI");
 225                     3'o3: $write("BLEI");
 226                     3'o4: $write("BGTI");
 227                     3'o5: $write("BGEI");
 228                     default: $write("XXX");
 229                   endcase // case (cpu.rRD[2:0])
 230
 231            6'o60: $write("LBU");
 232            6'o61: $write("LHU");
 233            6'o62: $write("LW");
 234            6'o64: $write("SB");
 235            6'o65: $write("SH");
 236            6'o66: $write("SW");
 237
 238            6'o70: $write("LBUI");
 239            6'o71: $write("LHUI");
 240            6'o72: $write("LWI");
 241            6'o74: $write("SBI");
 242            6'o75: $write("SHI");
 243            6'o76: $write("SWI");
 244
 245            default: $write("XXX");
 246          endcase // case (cpu.rOPC)
 247
 248          case (cpu.rOPC[3])
 249            1'b1: $writeh("\tr",cpu.rRD,", r",cpu.rRA,", h",cpu.rIMM);
 250            1'b0: $writeh("\tr",cpu.rRD,", r",cpu.rRA,", r",cpu.rRB,"  ");
 251          endcase // case (cpu.rOPC[3])
 252
 253
 254          // ALU
 255          $write("\t");
 256          $writeh(" A=",cpu.xecu.rOPA);
 257          $writeh(" B=",cpu.xecu.rOPB);
 258
 259          case (cpu.rMXALU)
 260            3'o0: $write(" ADD");
 261            3'o1: $write(" LOG");
 262            3'o2: $write(" SFT");
 263            3'o3: $write(" MOV");
 264            3'o4: $write(" MUL");
 265            3'o5: $write(" BSF");
 266            default: $write(" XXX");
 267          endcase // case (cpu.rMXALU)
 268          $writeh("=h",cpu.xecu.xRESULT);
 269
 270          // WRITEBACK
 271          $writeh("\tSR=", wMSR," ");
 272
 273          if (cpu.regf.fRDWE) begin
 274             case (cpu.rMXDST)
 275               2'o2: begin
 276                  if (dwb_stb_o) $writeh("R",cpu.rRW,"=RAM(h",cpu.regf.xWDAT,")");
 277                  if (fsl_stb_o) $writeh("R",cpu.rRW,"=FSL(h",cpu.regf.xWDAT,")");
 278               end
 279               2'o1: $writeh("R",cpu.rRW,"=LNK(h",cpu.regf.xWDAT,")");
 280               2'o0: $writeh("R",cpu.rRW,"=ALU(h",cpu.regf.xWDAT,")");
 281             endcase // case (cpu.rMXDST)
 282          end
 283
 284          // STORE
 285          if (dwb_stb_o & dwb_wre_o) begin
 286             $writeh("RAM(", dwb_adr ,")=", dwb_dat_o);
 287             case (dwb_sel_o)
 288               4'hF: $write(":L");
 289               4'h3,4'hC: $write(":W");
 290               4'h1,4'h2,4'h4,4'h8: $write(":B");
 291             endcase // case (dwb_sel_o)
 292
 293          end
 294
 295       end // if (cpu.gena)
 296
 297    end // always @ (posedge cpu.gclk)
 298    `endif //  `ifdef AEMB_SIM_KERNEL
 299
 300    // synopsys translate_on
 301
 302 endmodule // aeMB_sim
 303
 304 /*
 305  $Log: aeMB_sim.v,v $
 306  Revision 1.2  2008/06/06 09:36:02  sybreon
 307  single thread design
 308
 309  Revision 1.1  2007/12/23 20:40:45  sybreon
 310  Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.
 311
 312  */