1 /* $Id: aeMB_ibuf.v,v 1.10 2008/01/21 01:02:26 sybreon Exp $
3 ** AEMB INSTRUCTION BUFFER
4 ** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
6 ** This file is part of AEMB.
8 ** AEMB is free software: you can redistribute it and/or modify it
9 ** under the terms of the GNU Lesser General Public License as
10 ** published by the Free Software Foundation, either version 3 of the
11 ** License, or (at your option) any later version.
13 ** AEMB is distributed in the hope that it will be useful, but WITHOUT
14 ** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
16 ** Public License for more details.
18 ** You should have received a copy of the GNU Lesser General Public
19 ** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
22 module aeMB_ibuf (/*AUTOARG*/
24 rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, xIREG, rSTALL, iwb_stb_o,
26 rBRA, rMSR_IE, rMSR_BIP, iwb_dat_i, iwb_ack_i, sys_int_i, gclk,
31 output [4:0] rRA, rRD, rRB;
45 input [31:0] iwb_dat_i;
52 input gclk, grst, gena, oena;
59 wire [31:0] wIDAT = iwb_dat_i;
60 assign {rRB, rALT} = rIMM;
62 // TODO: Assign to FIFO not full.
63 assign iwb_stb_o = 1'b1;
65 reg [31:0] rSIMM, xSIMM;
68 wire [31:0] wXCEOP = 32'hBA2D0008; // Vector 0x08
69 wire [31:0] wINTOP = 32'hB9CE0010; // Vector 0x10
70 wire [31:0] wBRKOP = 32'hBA0C0018; // Vector 0x18
71 wire [31:0] wBRAOP = 32'h88000000; // NOP for branches
73 wire [31:0] wIREG = {rOPC, rRD, rRA, rRB, rALT};
77 // --- INTERRUPT LATCH --------------------------------------
78 // Debounce and latch onto the positive level. This is independent
79 // of the pipeline so that stalls do not affect it.
83 wire wSHOT = rDINT[0];
85 always @(posedge gclk)
88 // Beginning of autoreset for uninitialized flops
95 {rDINT[0], sys_int_i};
98 //(wIREG == wINTOP) ? 1'b0 :
99 (rFINT | wSHOT) & rMSR_IE;
102 wire fIMM = (rOPC == 6'o54);
103 wire fRTD = (rOPC == 6'o55);
104 wire fBRU = ((rOPC == 6'o46) | (rOPC == 6'o56));
105 wire fBCC = ((rOPC == 6'o47) | (rOPC == 6'o57));
107 // --- DELAY SLOT -------------------------------------------
109 always @(/*AUTOSENSE*/fBCC or fBRU or fIMM or fRTD or rBRA or rFINT
110 or wBRAOP or wIDAT or wINTOP) begin
111 xIREG <= (rBRA) ? wBRAOP :
112 (!fIMM & rFINT & !fRTD & !fBRU & !fBCC) ? wINTOP :
116 always @(/*AUTOSENSE*/fIMM or rBRA or rIMM or wIDAT or xIREG) begin
117 xSIMM <= (!fIMM | rBRA) ? { {(16){xIREG[15]}}, xIREG[15:0]} :
121 // --- PIPELINE --------------------------------------------
123 always @(posedge gclk)
126 // Beginning of autoreset for uninitialized flops
133 end else if (gena) begin
134 {rOPC, rRD, rRA, rIMM} <= #1 xIREG;
138 // --- STALL FOR MUL/BSF -----------------------------------
140 wire [5:0] wOPC = xIREG[31:26];
142 wire fMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
143 wire fBSF = (wOPC == 6'o21) | (wOPC == 6'o31);
145 always @(posedge gclk)
148 // Beginning of autoreset for uninitialized flops
152 rSTALL <= #1 (!rSTALL & (fMUL | fBSF)) | (oena & rSTALL);
155 endmodule // aeMB_ibuf
158 $Log: aeMB_ibuf.v,v $
159 Revision 1.10 2008/01/21 01:02:26 sybreon
162 Revision 1.9 2008/01/19 16:01:22 sybreon
163 Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus)
165 Revision 1.8 2007/12/25 22:15:09 sybreon
166 Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
168 Revision 1.7 2007/11/22 15:11:15 sybreon
169 Change interrupt to positive level triggered interrupts.
171 Revision 1.6 2007/11/14 23:39:51 sybreon
172 Fixed interrupt signal synchronisation.
174 Revision 1.5 2007/11/14 22:14:34 sybreon
175 Changed interrupt handling system (reported by M. Ettus).
177 Revision 1.4 2007/11/10 16:39:38 sybreon
178 Upgraded license to LGPLv3.
179 Significant performance optimisations.
181 Revision 1.3 2007/11/03 08:34:55 sybreon
184 Revision 1.2 2007/11/02 19:20:58 sybreon
185 Added better (beta) interrupt support.
186 Changed MSR_IE to disabled at reset as per MB docs.
188 Revision 1.1 2007/11/02 03:25:40 sybreon
189 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
190 Fixed various minor data hazard bugs.
191 Code compatible with -O0/1/2/3/s generated code.