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   1 /* $Id: aeMB_edk32.v,v 1.14 2008/01/19 16:01:22 sybreon Exp $
   2 **
   3 ** AEMB EDK 3.2 Compatible Core
   4 ** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
   5 **
   6 ** This file is part of AEMB.
   7 **
   8 ** AEMB is free software: you can redistribute it and/or modify it
   9 ** under the terms of the GNU Lesser General Public License as
  10 ** published by the Free Software Foundation, either version 3 of the
  11 ** License, or (at your option) any later version.
  12 **
  13 ** AEMB is distributed in the hope that it will be useful, but WITHOUT
  14 ** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15 ** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
  16 ** Public License for more details.
  17 **
  18 ** You should have received a copy of the GNU Lesser General Public
  19 ** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
  20 */
  21
  22 module aeMB_edk32 (/*AUTOARG*/
  23    // Outputs
  24    iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o,
  25    fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o,
  26    // Inputs
  27    sys_int_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, fsl_ack_i, dwb_dat_i,
  28    dwb_ack_i, sys_clk_i, sys_rst_i
  29    );
  30    // Bus widths
  31    parameter IW = 32; /// Instruction bus address width
  32    parameter DW = 32; /// Data bus address width
  33
  34    // Optional functions
  35    parameter MUL = 0; // Multiplier
  36    parameter BSF = 1; // Barrel Shifter
  37
  38    /*AUTOOUTPUT*/
  39    // Beginning of automatic outputs (from unused autoinst outputs)
  40    output [DW-1:2]      dwb_adr_o;              // From xecu of aeMB_xecu.v
  41    output [31:0]        dwb_dat_o;              // From regf of aeMB_regf.v
  42    output [3:0]         dwb_sel_o;              // From xecu of aeMB_xecu.v
  43    output               dwb_stb_o;              // From ctrl of aeMB_ctrl.v
  44    output               dwb_wre_o;              // From ctrl of aeMB_ctrl.v
  45    output [6:2]         fsl_adr_o;              // From xecu of aeMB_xecu.v
  46    output [31:0]        fsl_dat_o;              // From regf of aeMB_regf.v
  47    output               fsl_stb_o;              // From ctrl of aeMB_ctrl.v
  48    output [1:0]         fsl_tag_o;              // From xecu of aeMB_xecu.v
  49    output               fsl_wre_o;              // From ctrl of aeMB_ctrl.v
  50    output [IW-1:2]      iwb_adr_o;              // From bpcu of aeMB_bpcu.v
  51    output               iwb_stb_o;              // From ibuf of aeMB_ibuf.v
  52    // End of automatics
  53    /*AUTOINPUT*/
  54    // Beginning of automatic inputs (from unused autoinst inputs)
  55    input                dwb_ack_i;              // To ctrl of aeMB_ctrl.v
  56    input [31:0]         dwb_dat_i;              // To regf of aeMB_regf.v
  57    input                fsl_ack_i;              // To ctrl of aeMB_ctrl.v
  58    input [31:0]         fsl_dat_i;              // To regf of aeMB_regf.v
  59    input                iwb_ack_i;              // To ibuf of aeMB_ibuf.v, ...
  60    input [31:0]         iwb_dat_i;              // To ibuf of aeMB_ibuf.v
  61    input                sys_int_i;              // To ibuf of aeMB_ibuf.v
  62    // End of automatics
  63    /*AUTOWIRE*/
  64    // Beginning of automatic wires (for undeclared instantiated-module outputs)
  65    wire [10:0]          rALT;                   // From ibuf of aeMB_ibuf.v
  66    wire                 rBRA;                   // From bpcu of aeMB_bpcu.v
  67    wire                 rDLY;                   // From bpcu of aeMB_bpcu.v
  68    wire [31:0]          rDWBDI;                 // From regf of aeMB_regf.v
  69    wire [3:0]           rDWBSEL;                // From xecu of aeMB_xecu.v
  70    wire [15:0]          rIMM;                   // From ibuf of aeMB_ibuf.v
  71    wire                 rMSR_BIP;               // From xecu of aeMB_xecu.v
  72    wire                 rMSR_IE;                // From xecu of aeMB_xecu.v
  73    wire [1:0]           rMXALT;                 // From ctrl of aeMB_ctrl.v
  74    wire [2:0]           rMXALU;                 // From ctrl of aeMB_ctrl.v
  75    wire [1:0]           rMXDST;                 // From ctrl of aeMB_ctrl.v
  76    wire [1:0]           rMXSRC;                 // From ctrl of aeMB_ctrl.v
  77    wire [1:0]           rMXTGT;                 // From ctrl of aeMB_ctrl.v
  78    wire [5:0]           rOPC;                   // From ibuf of aeMB_ibuf.v
  79    wire [31:2]          rPC;                    // From bpcu of aeMB_bpcu.v
  80    wire [31:2]          rPCLNK;                 // From bpcu of aeMB_bpcu.v
  81    wire [4:0]           rRA;                    // From ibuf of aeMB_ibuf.v
  82    wire [4:0]           rRB;                    // From ibuf of aeMB_ibuf.v
  83    wire [4:0]           rRD;                    // From ibuf of aeMB_ibuf.v
  84    wire [31:0]          rREGA;                  // From regf of aeMB_regf.v
  85    wire [31:0]          rREGB;                  // From regf of aeMB_regf.v
  86    wire [31:0]          rRESULT;                // From xecu of aeMB_xecu.v
  87    wire [4:0]           rRW;                    // From ctrl of aeMB_ctrl.v
  88    wire [31:0]          rSIMM;                  // From ibuf of aeMB_ibuf.v
  89    wire                 rSTALL;                 // From ibuf of aeMB_ibuf.v
  90    wire [31:0]          xIREG;                  // From ibuf of aeMB_ibuf.v
  91    // End of automatics
  92
  93    input                sys_clk_i;
  94    input                sys_rst_i;
  95
  96    wire                 grst = sys_rst_i;
  97    wire                 gclk = sys_clk_i;
  98    wire                 gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i) & !rSTALL;
  99    wire                 oena = ((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i);
 100
 101    // --- INSTANTIATIONS -------------------------------------
 102
 103    aeMB_ibuf
 104      ibuf (/*AUTOINST*/
 105            // Outputs
 106            .rIMM                        (rIMM[15:0]),
 107            .rRA                         (rRA[4:0]),
 108            .rRD                         (rRD[4:0]),
 109            .rRB                         (rRB[4:0]),
 110            .rALT                        (rALT[10:0]),
 111            .rOPC                        (rOPC[5:0]),
 112            .rSIMM                       (rSIMM[31:0]),
 113            .xIREG                       (xIREG[31:0]),
 114            .rSTALL                      (rSTALL),
 115            .iwb_stb_o                   (iwb_stb_o),
 116            // Inputs
 117            .rBRA                        (rBRA),
 118            .rMSR_IE                     (rMSR_IE),
 119            .rMSR_BIP                    (rMSR_BIP),
 120            .iwb_dat_i                   (iwb_dat_i[31:0]),
 121            .iwb_ack_i                   (iwb_ack_i),
 122            .sys_int_i                   (sys_int_i),
 123            .gclk                        (gclk),
 124            .grst                        (grst),
 125            .gena                        (gena),
 126            .oena                        (oena));
 127
 128    aeMB_ctrl
 129      ctrl (/*AUTOINST*/
 130            // Outputs
 131            .rMXDST                      (rMXDST[1:0]),
 132            .rMXSRC                      (rMXSRC[1:0]),
 133            .rMXTGT                      (rMXTGT[1:0]),
 134            .rMXALT                      (rMXALT[1:0]),
 135            .rMXALU                      (rMXALU[2:0]),
 136            .rRW                         (rRW[4:0]),
 137            .dwb_stb_o                   (dwb_stb_o),
 138            .dwb_wre_o                   (dwb_wre_o),
 139            .fsl_stb_o                   (fsl_stb_o),
 140            .fsl_wre_o                   (fsl_wre_o),
 141            // Inputs
 142            .rDLY                        (rDLY),
 143            .rIMM                        (rIMM[15:0]),
 144            .rALT                        (rALT[10:0]),
 145            .rOPC                        (rOPC[5:0]),
 146            .rRD                         (rRD[4:0]),
 147            .rRA                         (rRA[4:0]),
 148            .rRB                         (rRB[4:0]),
 149            .rPC                         (rPC[31:2]),
 150            .rBRA                        (rBRA),
 151            .rMSR_IE                     (rMSR_IE),
 152            .xIREG                       (xIREG[31:0]),
 153            .dwb_ack_i                   (dwb_ack_i),
 154            .iwb_ack_i                   (iwb_ack_i),
 155            .fsl_ack_i                   (fsl_ack_i),
 156            .gclk                        (gclk),
 157            .grst                        (grst),
 158            .gena                        (gena));
 159
 160    aeMB_bpcu #(IW)
 161      bpcu (/*AUTOINST*/
 162            // Outputs
 163            .iwb_adr_o                   (iwb_adr_o[IW-1:2]),
 164            .rPC                         (rPC[31:2]),
 165            .rPCLNK                      (rPCLNK[31:2]),
 166            .rBRA                        (rBRA),
 167            .rDLY                        (rDLY),
 168            // Inputs
 169            .rMXALT                      (rMXALT[1:0]),
 170            .rOPC                        (rOPC[5:0]),
 171            .rRD                         (rRD[4:0]),
 172            .rRA                         (rRA[4:0]),
 173            .rRESULT                     (rRESULT[31:0]),
 174            .rDWBDI                      (rDWBDI[31:0]),
 175            .rREGA                       (rREGA[31:0]),
 176            .gclk                        (gclk),
 177            .grst                        (grst),
 178            .gena                        (gena));
 179
 180    aeMB_regf
 181      regf (/*AUTOINST*/
 182            // Outputs
 183            .rREGA                       (rREGA[31:0]),
 184            .rREGB                       (rREGB[31:0]),
 185            .rDWBDI                      (rDWBDI[31:0]),
 186            .dwb_dat_o                   (dwb_dat_o[31:0]),
 187            .fsl_dat_o                   (fsl_dat_o[31:0]),
 188            // Inputs
 189            .rOPC                        (rOPC[5:0]),
 190            .rRA                         (rRA[4:0]),
 191            .rRB                         (rRB[4:0]),
 192            .rRW                         (rRW[4:0]),
 193            .rRD                         (rRD[4:0]),
 194            .rMXDST                      (rMXDST[1:0]),
 195            .rPCLNK                      (rPCLNK[31:2]),
 196            .rRESULT                     (rRESULT[31:0]),
 197            .rDWBSEL                     (rDWBSEL[3:0]),
 198            .rBRA                        (rBRA),
 199            .rDLY                        (rDLY),
 200            .dwb_dat_i                   (dwb_dat_i[31:0]),
 201            .fsl_dat_i                   (fsl_dat_i[31:0]),
 202            .gclk                        (gclk),
 203            .grst                        (grst),
 204            .gena                        (gena));
 205
 206    aeMB_xecu #(DW, MUL, BSF)
 207      xecu (/*AUTOINST*/
 208            // Outputs
 209            .dwb_adr_o                   (dwb_adr_o[DW-1:2]),
 210            .dwb_sel_o                   (dwb_sel_o[3:0]),
 211            .fsl_adr_o                   (fsl_adr_o[6:2]),
 212            .fsl_tag_o                   (fsl_tag_o[1:0]),
 213            .rRESULT                     (rRESULT[31:0]),
 214            .rDWBSEL                     (rDWBSEL[3:0]),
 215            .rMSR_IE                     (rMSR_IE),
 216            .rMSR_BIP                    (rMSR_BIP),
 217            // Inputs
 218            .rREGA                       (rREGA[31:0]),
 219            .rREGB                       (rREGB[31:0]),
 220            .rMXSRC                      (rMXSRC[1:0]),
 221            .rMXTGT                      (rMXTGT[1:0]),
 222            .rRA                         (rRA[4:0]),
 223            .rRB                         (rRB[4:0]),
 224            .rMXALU                      (rMXALU[2:0]),
 225            .rBRA                        (rBRA),
 226            .rDLY                        (rDLY),
 227            .rALT                        (rALT[10:0]),
 228            .rSTALL                      (rSTALL),
 229            .rSIMM                       (rSIMM[31:0]),
 230            .rIMM                        (rIMM[15:0]),
 231            .rOPC                        (rOPC[5:0]),
 232            .rRD                         (rRD[4:0]),
 233            .rDWBDI                      (rDWBDI[31:0]),
 234            .rPC                         (rPC[31:2]),
 235            .gclk                        (gclk),
 236            .grst                        (grst),
 237            .gena                        (gena));
 238
 239
 240 endmodule // aeMB_edk32
 241
 242 /*
 243  $Log: aeMB_edk32.v,v $
 244  Revision 1.14  2008/01/19 16:01:22  sybreon
 245  Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus)
 246
 247  Revision 1.13  2007/12/25 22:15:09  sybreon
 248  Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
 249
 250  Revision 1.12  2007/12/23 20:40:44  sybreon
 251  Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.
 252
 253  Revision 1.11  2007/11/30 17:08:29  sybreon
 254  Moved simulation kernel into code.
 255
 256  Revision 1.10  2007/11/16 21:52:03  sybreon
 257  Added fsl_tag_o to FSL bus (tag either address or data).
 258
 259  Revision 1.9  2007/11/14 23:19:24  sybreon
 260  Fixed minor typo.
 261
 262  Revision 1.8  2007/11/14 22:14:34  sybreon
 263  Changed interrupt handling system (reported by M. Ettus).
 264
 265  Revision 1.7  2007/11/10 16:39:38  sybreon
 266  Upgraded license to LGPLv3.
 267  Significant performance optimisations.
 268
 269  Revision 1.6  2007/11/09 20:51:52  sybreon
 270  Added GET/PUT support through a FSL bus.
 271
 272  Revision 1.5  2007/11/08 17:48:14  sybreon
 273  Fixed data WISHBONE arbitration problem (reported by J Lee).
 274
 275  Revision 1.4  2007/11/08 14:17:47  sybreon
 276  Parameterised optional components.
 277
 278  Revision 1.3  2007/11/03 08:34:55  sybreon
 279  Minor code cleanup.
 280
 281  Revision 1.2  2007/11/02 19:20:58  sybreon
 282  Added better (beta) interrupt support.
 283  Changed MSR_IE to disabled at reset as per MB docs.
 284
 285  Revision 1.1  2007/11/02 03:25:40  sybreon
 286  New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
 287  Fixed various minor data hazard bugs.
 288  Code compatible with -O0/1/2/3/s generated code.
 289 */