16 wire [15:0] ser_r_odd;
17 wire ser_rklsb_odd, ser_rkmsb_odd;
22 always @(posedge ser_tx_clk) hold_k <= ser_tklsb;
23 always @(posedge ser_tx_clk) hold_dat <= ser_t[15:8];
24 assign ser_rklsb_odd = hold_k;
25 assign ser_rkmsb_odd = ser_tklsb;
26 assign ser_r_odd = {ser_t[7:0], hold_dat};
29 assign ser_rx_clk = ser_tx_clk;
30 assign ser_rkmsb = even ? ser_tkmsb : ser_rkmsb_odd;
31 assign ser_rklsb = even ? ser_tklsb : ser_rklsb_odd;
32 assign ser_r = error ^ (even ? ser_t : ser_r_odd);
34 endmodule // serdes_model