1 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRL16E.v,v 1.7 2005/03/14 22:32:58 yanx Exp $
2 ///////////////////////////////////////////////////////////////////////////////
3 // Copyright (c) 1995/2004 Xilinx, Inc.
5 ///////////////////////////////////////////////////////////////////////////////
8 // /___/ \ / Vendor : Xilinx
9 // \ \ \/ Version : 8.1i (I.13)
10 // \ \ Description : Xilinx Functional Simulation Library Component
11 // / / 16-Bit Shift Register Look-Up-Table with Clock Enable
12 // /___/ /\ Filename : SRL16E.v
13 // \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004
17 // 03/23/04 - Initial version.
20 `timescale 1 ps / 1 ps
23 module SRL16E (Q, A0, A1, A2, A3, CE, CLK, D);
25 parameter INIT = 16'h0000;
29 input A0, A1, A2, A3, CE, CLK, D;
34 assign Q = data[{A3, A2, A1, A0}];
39 while (CLK === 1'b1 || CLK===1'bX)
47 {data[15:0]} <= #100 {data[14:0], D};